DATASHEET

ISL6562
TM
Data Sheet
Microprocessor CORE Voltage Regulator
Two-Phase Buck PWM Controller
The ISL6562 two-phase current mode, PWM control IC
together with companion gate drivers, the HIP6601A,
HIP6602A, HIP6603A or HIP6604 and MOSFETs provides a
precision voltage regulation system for advanced
microprocessors. Two-phase power conversion is a marked
departure from earlier single phase converter configurations
previously employed to satisfy the ever increasing current
demands of modern microprocessors. Multi-phase
converters, by distributing the power and load current results
in smaller and lower cost transistors with fewer input and
output capacitors. These reductions accrue from the higher
effective conversion frequency with higher frequency ripple
current due to the phase interleaving process of this
topology. For example, a two phase converter operating at
350kHz per phase will have a ripple frequency of 700kHz.
Moreover, greater converter bandwidth of this design results
in faster response to load transients.
Outstanding features of this controller IC include
programmable VID codes from the microprocessor that
range from 1.050V to 1.825V with an accuracy of ±0.8%.
Pull up currents on these VID pins eliminates the need for
external pull up resistors.
Another feature of this controller IC is the PWRGD monitor
circuit which is held low until the CORE voltage increases, to
within 18% of the programmed voltage. Over-voltage, 24%
above programmed CORE voltage, results in the PWRGD
output going low to indicate that the CORE is above the
specified limit. Under voltage is also detected and results in
PWRGD going low if the CORE voltage falls 18% below the
programmed level. Over-current protection folds back the
output voltage to 95mV, reducing the regulator dissipation.
These features provide monitoring and protection for the
microprocessor and power system.
Ordering Information
PART NUMBER
ISL6562CB
TEMP. (oC)
0 to 70
ISL6562CB-T
16 Ld SOIC Tape and Reel
ISL6560/62EVAL1
Evaluation Platform
PKG. NO.
M16.15
File Number
9012
Features
• Two-Phase Power Conversion
• Precision Channel Current Sharing
• Precision CORE Voltage Regulation
- ±0.8% Accuracy
• Microprocessor Voltage Identification Input
- 5-Bit VID Input
- 1.050V to 1.825V in 25mV Steps
- Programmable “Droop” Voltage
• Fast Transient Recovery Time
• Over Current Protection
• High Ripple Frequency, (Channel Frequency
Times Number of Channels). . . . . . . . . . . . .100kHz to 2MHz
Applications
• VRM8.5 Modules
• Intel® Tualatin Processor Voltage Regulator
• Low Output Voltage, High Current DC/DC Converters
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
Pinout
ISL6562 (SOIC)
TOP VIEW
VID3 1
16 VCC
VID2 2
15 REF
VID1 3
14 CS-
VID0 4
13 PWM1
VID25mV 5
12 PWM2
COMP 6
PACKAGE
16 Ld SOIC
1
March 2001
FB 7
CT 8
11 CS+
10 PWRGD
9 GND
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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ISL6562
Block Diagram
VCC
REF
UVLO and
BIAS CIRCUITS
3V REFERENCE
PWRGD
OSCILLATOR
+
CT
-
X 0.82
UV
PWM1
CONTROL
LOGIC
+
-
X1.24
PWM2
OVP
VID3
CMP
VID2
+
E/A
D/A
VID1
-
+
-
CS+
CS-
VID0
VID25mV
FB
COMP
GND
Simplified Power System Diagram
FB
PWM 1
FB (Pin 7)
SYNCHRONOUS
RECTIFIED BUCK
CHANNEL
ISL6562
MICROPROCESSOR
PWM 2
SYNCHRONOUS
RECTIFIED BUCK
CHANNEL
A capacitor on this terminal sets the frequency of the internal
oscillator.
Functional Pin Description
VID3 1
16 VCC
VID2 2
15 REF
VID1 3
14 CS-
VID0 4
13 PWM1
VID25mV 5
12 PWM2
11 CS+
FB 7
10 PWRGD
CT 8
Inverting input of the internal transconductance error
amplifier.
CT (Pin 8)
VID
COMP 6
Current Sense Comparator. Pulling this pin to ground
disables the oscillator and drives both PWM outputs low.
9 GND
VID3 (Pin 1), VID2 (Pin 2), VID1 (Pin 3), VID0 (Pin 4)
and VID25mV (Pin 5)
Voltage Identification inputs from microprocessor. These pins
respond to TTL and 3.3V logic signals. The ISL6562 decodes
VID bits to establish the output voltage. See Table 1.
GND (Pin 9)
Bias and reference ground. All signals are referenced to this
pin.
PWRGD (Pin 10)
Open drain connection. A high voltage level at this pin with a
resistor connected to this terminal and VCC indicates that
CORE voltage is at the proper level,
CS+ (Pin 11) and CS- (Pin 14) These inputs monitor the
supply current to the converter positive input voltage. CS+ is
connected directly to the decoupled supply voltage and
current sampling resistor. CS- is connected to the other end
of the current sampling resistor and the upper drains of the
series transistors.
PWM2 (Pin 12) and PWM1 (Pin 13)
PWM outputs connected to the gate driver ICs.
REF (Pin 15)
COMP (Pin 6)
Three volt supply used to bias the output of the
transconductance amplifier.
Output of the internal transconductance error amplifier.
Voltage at this terminal sets the output current level of the
VCC (Pin 16)
Bias supply. Connect this pin to a 12V supply.
2
ISL6562
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 15V
CS+. CS- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V
PWRGD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC
All Other Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5V
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . TBD
Machine Model (Per EIAJ ED-4701 Method C-111). . . . . . . . TBD
Thermal Resistance (Note 1)
θJA (oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
106
Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
Maximum Operating Junction Temperature . . . . . . . . . . . . . . 125oC
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V ±10%
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VCC = 12V
-
5.8
9.0
mA
VCC ≤ VUVLO, VCC Rising
-
5.7
8.9
mA
5.4
6.4
6.9
V
0.1
0.4
0.8
V
VCC SUPPLY CURRENT
Input Supply Current
ICC
Input Supply Current, UVLO Mode
Undervoltage Lock Out Voltage
ICC(UVLO)
VUVLO
Undervoltage Lock Out Hysteresis
DAC and REFERENCE VOLTAGES
Minimum DAC Programed Voltage
VFB
DAC Programmed to 1.050V
1.042
1.050
1.058
V
Middle DAC Programed Voltage
VFB
DAC Programmed to 1.500V
1.488
1.500
1.512
V
Maximum DAC Programed Voltage
VFB
DAC Programmed to 1.825V
1.811
1.825
1.839
V
-
0.05
-
%
124
134
%
∆VFB
Line Regulation
VCC = 10V to 14V
Crowbar Trip Point at FB Input
VCROWBAR
Percent of Nominal DAC Voltage
114
Crowbar Reset Point at FB Input
VCROWBAR
Percent of Nominal DAC Voltage
50
60
70
%
Crowbar Response Time
ICROWBAR
Overvoltage to PWM Going Low
-
300
-
ns
2.952
3.000
3.048
V
300
-
-
µA
Reference Voltage
VREF
Output Current
IREF
0mA ≤ IREF ≤ 1mA
VID INPUTS
Input Low Voltage
VIL(VID)
-
-
0.6
V
Input High Voltage
VIH(VID)
2.2
-
-
V
10
20
40
µA
4.5
5.0
5.5
V
VID Pull-Up
IVID
VIDx = 0V or VIDx = 3V
Internal Pull-Up Voltage
OSCILLATOR
Maximum Frequency
fCT(MAX)
Frequency Variation
∆fCT
CT Charging Current
ICT
CT Charging Current
ICT
2.0
-
-
MHz
TA = 25oC, CT = 91pF
430
500
570
kHz
TA = 25oC, VFB in Regulation
TA = 25oC, VFB = 0V
130
150
170
µA
26
36
46
µA
ERROR AMPLIFIER
Output Resistance
RO(ERR)
-
200
-
kΩ
Transconductance
gm(ERR)
2.0
2.2
2.4
mS
3
ISL6562
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted
PARAMETER
SYMBOL
Output Current
TEST CONDITIONS
IO(ERR)
Input Bias Current
FB Forced to VOUT - 3%
IFB
MIN
TYP
MAX
UNITS
-
1
-
mA
-
5
100
nA
-
3.0
-
V
Maximum Output Voltage
VCOMP(MAX) FB Forced to VOUT - 3%
Output Disable Threshold
VCOMP(OFF)
560
720
800
mV
VFB(LOW)
375
425
500
mV
-
500
-
kHz
69
79
89
mV
FB Low Foldback Threshold
-3dB Bandwidth
BWERR
COMP = Open
VCS(TH)
CS+ = VCC, FB Forced to VOUT - 3%
CURRENT SENSE
Threshold Voltage
0.8 ≤ COMP ≤ 1V
Current Limit Foldback Voltage
VCS(FOLD)
-
0
15
mV
37
47
58
mV
ni
1 V ≤ VCOMP ≤ 3V
-
25
-
V/V
ICS+, ICS-
CS+ = CS- = VCC
-
0.5
5.0
µA
CS+ - (CS-) ≥ 89mV to PWM Going Low
-
50
-
ns
∆VCOMP/∆VCS
Input Bias Current
FB ≤ 375mV
Response Time
tCS
POWER GOOD COMPARATOR
Undervoltage Threshold
VPWRGD(UV) Percent of Nominal Output
76
82
88
%
Overvoltage Threshold
VPWRGD(OV) Percent of Nominal Output
114
124
134
%
Output Voltage Low
VOL(PWRGD) IPWRGD(SINK) = 100µA
-
30
200
mV
-
200
-
ns
Response Time
PWM OUTPUTS
Output Voltage Low
VOL(PWM)
IPWM(SINK) = 400µA
Output Voltage High
VOH(PWM)
IPWM(SOURCE) = 400µA
Output Current
IPWM
Duty Cycle Limit, by Design
DMAX
Per Phase, Relative to fCT
-
100
500
mV
4.5
5.0
5.5
V
0.4
1
-
mA
-
-
50
%
.
VOLTAGE IDENTIFICATION CODE AT
PROCESSOR PINS
VOLTAGE IDENTIFICATION CODE AT
PROCESSOR PINS
VID25mV
VID3
VID2
VID1
VID0
VCCCORE
(VDC)
0
0
1
0
0
1.050
0
1
1
0
0
1.450
1
0
1
0
0
1.075
1
1
1
0
0
1.475
0
0
0
1
1
1.100
0
1
0
1
1
1.500
1
0
0
1
1
1.125
1
1
0
1
1
1.525
0
0
0
1
0
1.150
0
1
0
1
0
1.550
1
0
0
1
0
1.175
1
1
0
1
0
1.575
0
0
0
0
1
1.200
0
1
0
0
1
1.600
1
0
0
0
1
1.225
1
1
0
0
1
1.625
0
0
0
0
0
1.250
0
1
0
0
0
1.650
1
0
0
0
0
1.275
1
1
0
0
0
1.675
0
1
1
1
1
1.300
0
0
1
1
1
1.700
1
1
1
1
1
1.325
1
0
1
1
1
1.725
0
1
1
1
0
1.350
0
0
1
1
0
1.750
1
1
1
1
0
1.375
1
0
1
1
0
1.775
0
1
1
0
1
1.400
0
0
1
0
1
1.800
1
1
1
0
1
1.425
1
0
1
0
1
1.825
4
VID25mV
VID3
VID2
VID1
VID0
VCCCORE
(VDC)
ISL6562
Small Outline Plastic Packages (SOIC)
N
INDEX
AREA
H
0.25(0.010) M
M16.15 (JEDEC MS-012-AC ISSUE C)
B M
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
E
-B1
2
INCHES
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
e
α
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
B S
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.3859
0.3937
9.80
10.00
3
E
0.1497
0.1574
3.80
4.00
4
e
0.050 BSC
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
N
α
16
0o
1.27
6
16
8o
0o
7
8o
Rev. 0 12/93
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