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Dual 3+1 PWM Controller with Current Monitor for
IMVP-7/VR12™ CPUs
ISL95839
Features
The ISL95839 Pulse Width Modulation (PWM) controller IC
provides a complete solution for IMVP-7/VR12™ compliant
microprocessor and graphic processor core power supplies. It
provides the control and protection for two Voltage Regulators
(VRs). The first VR, typical for Vcore, incorporates 2 integrated
drivers and can operate in 3-, 2- or 1-phase configurations. The
second VR, typical for Graphics, incorporates 1 integrated
driver. The two VRs share a serial control bus to communicate
with the CPU and achieve lower cost and smaller board area
compared with the two-chip approach.
• Serial data bus
• Dual outputs:
- Configurable 3-, 2- or 1-phase for the 1st output using two
integrated gate drivers
- 2nd output using an integrated gate driver
• R3™ Modulator
- Excellent transient response
- High light load efficiency
• 0.5% system accuracy over-temperature
Both VRs utilize Intersil’s Robust Ripple Regulator R3
Technology™. The R3 modulator has numerous advantages
compared to traditional modulators, including faster transient
response, variable switching frequency during load transients,
and improved light load efficiency due to its ability to
automatically change switching frequency.
• Supports multiple current sensing methods
- Lossless inductor DCR current sensing
- Precision resistor current sensing
• Differential remote voltage sensing
• Programmable VBOOT voltage at start-up
The ISL95839 has several other key features. Both outputs
support either DCR current sensing with a single NTC
thermistor for DCR temperature compensation, or more
precise resistor current sensing if desired. Both outputs come
with remote voltage sense, programmable VBOOT voltage,
IMAX, and switching frequency, adjustable overcurrent
protection and separate Power-Good signals.
• Resistor programmable IMAX, switching frequency for both
outputs
• Output current monitor (IMON and IMONG)
• Adaptive body diode conduction time reduction
Applications
• IMVP-7/VR12 compliant computers
Vin
VR2
Vin
0.91
VR1
VIN = 19V
0.90
ISL6208B
DRIVER
0.89
ISL95839
0.88
VOUT (V)
Vin
0.87
0.86
0.85
0.84
0.83
Vin
VIN = 12V
0.82
VIN = 8V
0.81
0.80
0
6
12
18
24
30
36
42
48
54
60
66
IOUT (A)
FIGURE 1. SIMPLIFIED APPLICATION CIRCUIT
May 9, 2013
FN8315.0
1
FIGURE 2. LOAD LINE REGULATION
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2013. All Rights Reserved
Intersil (and design) and R3 Technology™ are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL95839
Table of Contents
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Simplified Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Gate Driver Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiphase R3™ Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diode Emulation and Period Stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Start-up Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Regulation and Load Line Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential Voltage Sensing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase Current Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CCM Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dynamic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VR_HOT#/ALERT# Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FB2 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adaptive Body Diode Conduction Time Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supported Data and Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
10
11
12
12
16
16
16
18
18
19
19
20
20
20
21
Key Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Inductor DCR Current-Sensing Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Resistor Current-Sensing Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Compensator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Programming Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Current Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Slew Rate Compensation Circuit for VID Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Typical Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2
FN8315.0
May 9, 2013
ISL95839
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
ISL95839HRTZ
TEMP. RANGE
(°C)
PART MARKING
95839 HRTZ
PACKAGE
(Pb-Free)
-10 to +100
40 Ld 5x5 TQFN
PKG.
DWG. #
L40.5x5
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL95839. For more information on MSL please see techbrief TB363.
Pin Configuration
UGATE1G
BOOT1G
PHASE1G
LGATE1G
VR_ON
PGOODG
COMPG
FBG
RTNG
ISUMNG
ISL95839
(40 LD TQFN)
TOP VIEW
40 39 38 37 36 35 34 33 32 31
ISUMPG 1
30 BOOT2
IMONG 2
29 UGATE2
IMON 3
28 PHASE2
NTCG 4
27 LGATE2
SCLK 5
26 VCCP
GND PAD
(BOTTOM)
ALERT# 6
25 VDD
SDA 7
24 PWM3
VR_HOT# 8
23 LGATE1
FB2 9
22 PHASE1
NTC 10
21 UGATE1
BOOT1
PGOOD
COMP
FB
RTN
ISUMN
ISEN1
ISUMP
ISEN2
ISEN3
11 12 13 14 15 16 17 18 19 20
Pin Descriptions
PIN #
SYMBOL
2
IMONG
Output current monitor for VR2.
3
IMON
Output current monitor for VR1.
4
NTCG
The second thermistor input to VR_HOT# circuit. Use it to monitor VR2 temperature.
5, 6, 7
DESCRIPTION
SCLK, ALERT#, Communication bus between the CPU and the VRs.
SDA
8
VR_HOT#
Open drain thermal overload output indicator. Can be considered part of communication bus with CPU.
9
FB2
There is a switch between the FB2 pin and the FB pin. The switch is on when VR1 is in 3-phase and 2-phase mode and is off
in 1-phase mode. The components connecting to FB2 are used to adjust the compensation in 1-phase mode to achieve
optimum performance for VR1.
10
NTC
One of the thermistor inputs to VR_HOT# circuit. Use it to monitor VR1 temperature.
11
ISEN3
ISEN3 is the individual current sensing for VR1 phase 3.
3
FN8315.0
May 9, 2013
ISL95839
Pin Descriptions (Continued)
PIN #
SYMBOL
DESCRIPTION
12
ISEN2
Individual current sensing for VR1 Phase 2. When ISEN2 and PWM3 are both pulled to 5V VDD, the controller will disable VR1
Phases 3 and 2.
13
ISEN1
Individual current sensing for VR1 Phase 1.
14, 15
ISUMP, ISUMN VR1 droop current sense input.
16
RTN
VR1 remote voltage sensing return.
17
FB
18
COMP
This pin is the output of the error amplifier for VR1. Also, a resistor from this pin to GND programs IMAX for VR1, and VBOOT
for both VR1 and VR2.
19
PGOOD
Power-Good open-drain output indicating when VR1 is able to supply regulated voltage. Pull up externally with a 680Ω resistor
to VCCP or 1.9kΩ to 3.3V.
20
BOOT1
Connect an MLCC capacitor across the BOOT1 and the PHASE1 pins. The boot capacitor is charged through an internal boot
diode connected from the VCCP pin to the BOOT1 pin, each time the PHASE1 pin drops below VCCP minus the voltage
dropped across the internal boot diode.
21
UGATE1
Output of VR1 Phase-1 high-side MOSFET gate driver. Connect the UGATE1 pin to the gate of the Phase-1 high-side MOSFET.
22
PHASE1
Current return path for the VR1 Phase-1 high-side MOSFET gate driver. Connect the PHASE1 pin to the node consisting of the
high-side MOSFET source, the low-side MOSFET drain, and the output inductor of VR1 Phase 1.
23
LGATE1
Output of VR1 Phase-1 low-side MOSFET gate driver. Connect the LGATE1 pin to the gate of VR1 Phase-1 low-side MOSFET.
24
PWM3
PWM output for VR1 Phase 3. When PWM3 is pulled to 5V VDD, the controller will disable VR1 Phase 3.
25
VDD
5V bias power.
26
VCCP
Input voltage bias for the internal gate drivers. Connect +5V to the VCCP pin. Decouple with at least 1µF of an MLCC capacitor.
27
LGATE2
Output of VR1 Phase-2 low-side MOSFET gate driver. Connect the LGATE2 pin to the gate of VR1 Phase-2 low-side MOSFET.
28
PHASE2
Current return path for VR1 Phase-2 high-side MOSFET gate driver. Connect the PHASE2 pin to the node consisting of the
high-side MOSFET source, the low-side MOSFET drain, and the output inductor of VR1 Phase 2.
29
UGATE2
Output of VR1 Phase-2 high-side MOSFET gate driver. Connect the UGATE2 pin to the gate of VR1 Phase-2 high-side MOSFET.
30
BOOT2
Connect an MLCC capacitor across the BOOT2 and the PHASE2 pins. The boot capacitor is charged through an internal boot
diode connected from the VCCP pin to the BOOT2 pin, each time the PHASE2 pin drops below VCCP minus the voltage
dropped across the internal boot diode.
31
BOOT1G
Connect an MLCC capacitor across the BOOT1G and the PHASE1G pins. The boot capacitor is charged through an internal
boot diode connected from the VCCP pin to the BOOT1G pin, each time the PHASE1G pin drops below VCCP minus the voltage
dropped across the internal boot diode.
32
UGATE1G
Output of VR2 Phase-1 high-side MOSFET gate driver. Connect the UGATE1G pin to the gate of VR2 Phase-1 high-side MOSFET.
33
PHASE1G
Current return path for VR2 Phase-1 high-side MOSFET gate driver. Connect the PHASE1G pin to the node consisting of the
high-side MOSFET source, the low-side MOSFET drain, and the output inductor of VR2 Phase 1.
34
LGATE1G
Output of VR2 Phase-1 low-side MOSFET gate driver. Connect the LGATE1G pin to the gate of VR2 Phase-1 low-side MOSFET.
35
VR_ON
36
PGOODG
Power-Good open-drain output indicating when VR2 is able to supply regulated voltage. Pull-up externally with a 680Ω
resistor to VCCP or 1.9kΩ to 3.3V.
37
COMPG
This pin is the output of the error amplifier for VR2. Also, a resistor from this pin to GND programs IMAX for VR2 and TMAX for
both VR1 and VR2.
38
FBG
39
RTNG
40, 1
ISUMNG and
ISUMPG
Bottom
Pad
GND
This pin is the inverting input of the error amplifier for VR1.
Controller enable input. A high level logic signal on this pin enables the controller.
This pin is the inverting input of the error amplifier for VR2.
VR2 remote voltage sensing return.
VR2 droop current sense input. When ISUMNG is pulled to 5V VDD, all the communication to VR2 is disabled.
Signal common of the IC. Unless otherwise stated, signals are referenced to the GND pin. In addition, it is the return path for
all the low-side MOSFET gate drivers. It should also be used as the thermal pad for heat removal.
4
FN8315.0
May 9, 2013
ISL95839
Block Diagram
COMPG
+
RTNG

+
+
_
FBG
E/A
BOOT1G
VR2
MODULATOR
IDROOPG
ISUMPG
+
ISUMNG
_
DRIVER
UGATE1G
PHASE1G
CURRENT
SENSE
DRIVER
LGATE1G
PGOODG
IMONG
OC FAULT
OV FAULT
NTCG
T_MONITOR
TEMP
MONITOR
NTC
VDD
VR_HOT#
VCCP
IMAX
VBOOT
TMAX
SET (A/D)
PROG
VR_ON
SDA
DIGITAL
INTERFACE
ALERT#
A/D
IDROOPG
IDROOP
D/A
DAC2
DAC1
MODE
SCLK
PWM3
MODE2
MODE1
BOOT2
VREADY
DRIVER
UGATE2
PHASE2
COMP
+
RTN
FB
FB2

+
_
FB2
CIRCUIT
VR1
MODULATOR
+
E/A
DRIVER
BOOT1
IDROOP
DRIVER
ISUMP
+
ISUMN
_
CURRENT
SENSE
UGATE1
PHASE1
ISEN3
ISEN2
LGATE2
DRIVER
CURRENT
BALANCING
OC FAULT
ISEN1
LGATE1
PGOOD
IBAL FAULT
OV FAULT
IMON
5
GND
FN8315.0
May 9, 2013
ISL95839
Simplified Application Circuit
+5V
VDD
BOOT1G
NTCG
oC
Vin
VCCP
Rntcg
UGATE1G
PGOODG
PGOODG
L4
PHASE1G
GT Vcore
LGATE1G
ISUMPG
COMPG
Rng
RCOMPG
Rig
Vsumng
ISUMNG
FBG
Rdroopg
Rsum4
oC
Cng
Cvsumng
Rimong
IMONG
Cimong
V+5
VCCSENSEG
VSSSENSEG
Vin
RTNG
VCC
UGATE
PHASE
ISL6208
BOOT
PWM LGATE
GND
L3
FCCM
PWM3
SDA
ALERT#
SCLK
SDA
ALERT#
SCLK
BOOT2
ISL95839
UGATE2
L2
PHASE2
CPU Vcore
LGATE2
Rntc
BOOT1
NTC
oC
L1
UGATE1
VR_HOT#
PGOOD
VR_ON
VR_HOT#
PGOOD
VR_ON
PHASE1
LGATE1
Rsum3
FB2
ISUMP
Rsum2
Rn
oC
Cn
COMP
RCOMP
Ri
Vsumn
ISUMN
FB
Cisen1 Cisen2 Cisen3
Rdroop
Rsum1
Cvsumn
Risen3
ISEN3
Risen2
ISEN2
Risen1
ISEN1
VCCSENSE
VSSSENSE
RTN
IMON
Rimon
GND
Cimon
FIGURE 3. TYPICAL ISL95839 APPLICATION CIRCUIT USING INDUCTOR DCR SENSING
6
FN8315.0
May 9, 2013
ISL95839
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +28V
Boot Voltage (BOOT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V
Boot-to-Phase Voltage
(BOOT-PHASE) -0.3V to +7V(DC) . . . . . . . . . . . . . . . .-0.3V to +9V (<10ns)
Phase Voltage (PHASE) . . . . . . . . . . . . . . . . -7V (<20ns Pulse Width, 10µJ)
UGATE Voltage (UGATE) . . . . . . . . . . . . . . . . . . . PHASE - 0.3V (DC) to BOOT
. . . . . . . . . . . . . . . . . . . . PHASE - 5V (<20ns Pulse Width, 10µJ) to BOOT
LGATE Voltage . . . . . . . . . . . . -2.5V (<20ns Pulse Width, 5µJ) to VDD+0.3V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VDD +0.3V)
Open Drain Outputs, PGOOD, VR_HOT#, ALERT#. . . . . . . . . . -0.3V to +7V
ESD Rating
Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . 2kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . . 200V
Charged Device Model (Tested per JESD22-C101A) . . . . . . . . . . . . . . 1k
Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
40 Ld TQFN Package (Notes 4, 5) . . . . . . .
32
4
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Battery Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.75V to 25V
Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Operating Conditions: VDD = 5V, TA = -10°C to +100°C, fSW = 300kHz, unless otherwise noted. Boldface limits
apply over the operating temperature range, -10°C to +100°C
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
6.4
8.0
mA
1
µA
4.5
V
INPUT POWER SUPPLY
+5V Supply Current
IVDD
VR_ON = 1V
VR_ON = 0V
POWER-ON-RESET THRESHOLDS
VDD Power-On-Reset Threshold
VIN Power-On-Reset Threshold
VDDPORr
VDD rising
VDDPORf
VDD falling
4.35
4.00
VINPOR
4.15
4.40
V
4.75
V
SYSTEM AND REFERENCES
System Accuracy
%Error (VOUT)
No load; closed loop, active mode range,
VID = 0.75V to 1.52V,
VID = 0.5V to 0.745V
VID = 0.25V to 0.495V
-0.5
+0.5
%
-6
+6
mV
+10
mV
1.1055
V
-10
1.0945
Internal VBOOT
1.100
Maximum Output Voltage
VOUT(max)
VID = [11111111]
1.52
V
Minimum Output Voltage
VOUT(min)
VID = [00000001]
0.25
V
CHANNEL FREQUENCY
300kHz Configuration
fSW_300k
277
300
323
kHz
350kHz Configuration
fSW_350k
324
350
376
kHz
400kHz Configuration
fSW_400k
370
400
430
kHz
450kHz Configuration
fSW_450k
412
445
478
kHz
+0.2
mV
AMPLIFIERS
IFB = 0A
Current-Sense Amplifier Input Offset
Error Amp DC Gain
AV0
Error Amp Gain-Bandwidth Product
GBW
7
CL = 20pF
-0.2
90
dB
18
MHz
FN8315.0
May 9, 2013
ISL95839
Electrical Specifications Operating Conditions: VDD = 5V, TA = -10°C to +100°C, fSW = 300kHz, unless otherwise noted. Boldface limits
apply over the operating temperature range, -10°C to +100°C (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
1
mV
ISEN
Imbalance Voltage
Maximum of ISENs - Minimum of ISENs
Input Bias Current
20
nA
POWER-GOOD AND PROTECTION MONITORS
PGOOD Low Voltage
VOL
IPGOOD = 4mA
PGOOD Leakage Current
IOH
PGOOD = 3.3V
PGOOD Delay
tpgd
0.15
0.4
V
1
µA
2.6
ms
ALERT# Low
7
12
VR_HOT# Low
7
Ω
12
Ω
ALERT# Leakage Current
1
µA
VR_HOT# Leakage Current
1
µA
CURRENT MONITOR
IMON and IMONG Output Current
IIMON
ICCMAX Alert Trip Voltage
VIMONMAX
ICCMAX Alert Reset Voltage
ISUM- pin current = 40µA
9.7
10
10.3
µA
ISUM- pin current = 20µA
4.8
5
5.2
µA
ISUM- pin current = 4µA
0.875
1
1.125
µA
Rising
1.2
Falling
1.14
V
1.8
V
IMON Voltage Clamp
V
GATE DRIVER
UGATE Pull-Up Resistance
RUGPU
200mA Source Current
1.0
UGATE Source Current
IUGSRC
UGATE - PHASE = 2.5V
2.0
UGATE Sink Resistance
RUGPD
250mA Sink Current
1.0
UGATE Sink Current
IUGSNK
UGATE - PHASE = 2.5V
2.0
LGATE Pull-Up Resistance
RLGPU
250mA Source Current
1.0
LGATE Source Current
ILGSRC
LGATE - VSSP = 2.5V
2.0
1.5
Ω
A
1.5
Ω
1.5
Ω
A
A
LGATE Sink Resistance
RLGPD
250mA Sink Current
0.5
LGATE Sink Current
ILGSNK
LGATE - VSSP = 2.5V
4.0
0.9
Ω
A
UGATE to LGATE Deadtime
tUGFLGR
UGATE falling to LGATE rising, no load
17
ns
LGATE to UGATE Deadtime
tLGFUGR
LGATE falling to UGATE rising, no load
29
ns
15
Ω
0.2
µA
BOOTSTRAP SWITCH
On Resistance
RF
Reverse Leakage
IR
VR = 25V
PROTECTION
Overvoltage Threshold
OVH
VSEN rising above setpoint for >1µs
145
175
200
One ISEN above another ISEN for >3.2ms
VR1 Overcurrent Threshold
3-Phase - PS0 and 1-Phase - all states
56
60
64
µA
3-Phase - PS1
37
40
43
µA
3-Phase - PS2
18
20
22
µA
2-Phase - PS0
56
60
64
µA
VR2 Overcurrent Threshold
8
23
mV
Current Imbalance Threshold (VR1)
mV
2-Phase - PS1 and PS2
27
30
33
µA
1-Phase - all states
56
60
64
µA
FN8315.0
May 9, 2013
ISL95839
Electrical Specifications Operating Conditions: VDD = 5V, TA = -10°C to +100°C, fSW = 300kHz, unless otherwise noted. Boldface limits
apply over the operating temperature range, -10°C to +100°C (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
0.3
V
LOGIC THRESHOLDS
VR_ON Input Low
VIL
VR_ON Input High
VIH
0.7
V
PWM3
PWM Output Low
V0L
Sinking 5mA
PWM Output High
V0H
Sourcing 5mA
PWM Tri-State Leakage
1.0
3.5
PWM = 2.5V
V
4.2
V
1
µA
NTC and NTCG
NTC Source Current
NTC = 1.3V
58
60
62
µA
VR_HOT# Trip Voltage (VR1 and VR2)
Falling
0.881
0.893
0.905
V
VR_HOT# Reset Voltage
(VR1 and VR2)
Rising
0.924
0.936
0.948
V
Therm_Alert Trip Voltage
(VR1 and VR2)
Falling
0.920
0.932
0.944
V
Therm_Alert Reset Voltage
(VR1 and VR2)
Rising
0.962
0.974
0.986
V
-1
0
INPUTS
VR_ON Leakage Current
IVR_ON
VR_ON = 0V
VR_ON = 1V
SCLK, SDA Leakage
3.5
VR_ON = 0V, SCLK and SDA = 0V and 1V
-1
VR_ON = 1V, SCLK and SDA = 1V
-2
µA
6
µA
1
µA
1
µA
VR_ON = 1V, SDA = 0V
-21
µA
VR_ON = 1V, SCLK= 0V
-42
µA
SLEW RATE (For VID Change)
Fast Slew Rate
10
mV/µs
Slow Slew Rate
2.5
mV/µs
NOTE:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
9
FN8315.0
May 9, 2013
ISL95839
Gate Driver Timing Diagram
PWM
tLGFUGR
tFU
tRU
1V
UGATE
1V
LGATE
tRL
tFL
tUGFLGR
Theory of Operation
Multiphase R3™ Modulator
The ISL95839 is a multiphase regulator implementing Intel™
IMVP-7/VR12™ protocol. It has two voltage regulators, VR1 and
VR2, on one chip. VR1 can be programmed for 1-, 2- or 3-phase
operation, and VR2 is 1-phase operation. The following description
is based on VR1, but also applies to VR2 because they are based
on the same architecture.
than conventional hysteretic mode and fixed PWM mode
controllers. Unlike conventional hysteretic mode converters, the
ISL95839 uses an error amplifier that allows the controller to
maintain a 0.5% output voltage accuracy.
MASTER
CLOCK
gmVo
The ISL95839 uses Intersil patented R3™ (Robust Ripple
Regulator™) modulator. The R3™ modulator combines the best
features of fixed frequency PWM and hysteretic PWM while
eliminating many of their shortcomings. Figure 4 conceptually
shows the multiphase R3™ modulator circuit, and Figure 5 shows
the operation principles.
Inside the IC, the modulator uses the master clock circuit to
generate the clocks for the slave circuits. The modulator
discharges the ripple capacitor Crm with a current source equal
to gmVo, where gm is a gain factor. Crm voltage Vcrm is a
sawtooth waveform traversing between the VW and COMP
voltages. It resets to VW when it hits COMP, and generates a
one-shot master clock signal. A phase sequencer distributes the
master clock signal to the slave circuits. If VR1 is in 3-phase
mode, the master clock signal will be distributed to the three
phases, and the Clock1~3 signals will be 120° out-of-phase. If
VR1 is in 2-phase mode, the master clock signal will be
distributed to Phases 1 and 2, and the Clock1 and Clock2 signals
will be 180° out-of-phase. If VR1 is in 1-phase mode, the master
clock signal will be distributed to Phase 1 only and will be the
Clock1 signal.
Each slave circuit has its own ripple capacitor Crs, whose voltage
mimics the inductor ripple current. A gm amplifier converts the
inductor voltage into a current source to charge and discharge
Crs. The slave circuit turns on its PWM pulse upon receiving the
clock signal, and the current source charges Crs. When Crs
voltage VCrs hits VW, the slave circuit turns off the PWM pulse,
and the current source discharges Crs.
MASTER CLOCK CIRCUIT
MASTER
CLOCK
COMP
Phase
Vcrm
Sequencer
VW
Clock1
Clock2
Clock3
Crm
SLAVE CIRCUIT 1
VW
Clock1
S
R
Q
PWM1 Phase1
L1
IL1
Vcrs1
Vo
Co
gm
Crs1
SLAVE CIRCUIT 2
VW
Clock2
S
R
Q
PWM2 Phase2
L2
IL2
Vcrs2
gm
Crs2
SLAVE CIRCUIT 3
VW
Clock3
S
R
Q
PWM3 Phase3
L3
IL3
Vcrs3
gm
Crs3
FIGURE 4. R3™ MODULATOR CIRCUIT
Since the controller works with Vcrs, which are large-amplitude
and noise-free synthesized signals, it achieves lower phase jitter
10
FN8315.0
May 9, 2013
ISL95839
VW
HYSTERETIC
W INDOW
Vcrm
COMP
Master
Clock
rises as the COMP voltage rises, making the PWM pulses wider.
During load release response, the COMP voltage falls. It takes
the master clock circuit longer to generate the next master clock
signal so the PWM pulse is held off until needed. The VW voltage
falls as the COMP voltage falls, reducing the current PWM pulse
width. This kind of behavior gives the controller excellent
response speed.
The fact that all the phases share the same VW window voltage
also ensures excellent dynamic current balance among phases.
Clock1
PW M1
Diode Emulation and Period Stretching
Clock2
PW M2
Clock3
Phase
PW M3
UGATE
VW
LGATE
Vcrs2 Vcrs3
Vcrs1
FIGURE 5. R3™ MODULATOR OPERATION PRINCIPLES IN
STEADY STATE
IL
FIGURE 7. DIODE EMULATION
ISL95839 can operate in diode emulation (DE) mode to improve
light load efficiency. In DE mode, the low-side MOSFET conducts
when the current is flowing from source to drain and doesn’t allow
reverse current, emulating a diode. As Figure 7 shows, when
LGATE is on, the low-side MOSFET carries current, creating
negative voltage on the phase node due to the voltage drop across
the ON-resistance. The controller monitors the current through
monitoring the phase node voltage. It turns off LGATE when the
phase node voltage reaches zero to prevent the inductor current
from reversing the direction and creating unnecessary power loss.
VW
COMP
Vcrm
Master
Clock
Clock1
If the load current is light enough, as Figure 7 shows, the inductor
current will reach and stay at zero before the next phase node
pulse and the regulator is in discontinuous conduction mode
(DCM). If the load current is heavy enough, the inductor current
will never reach 0A, and the regulator is in CCM although the
controller is in DE mode.
PWM1
Clock2
PWM2
Clock3
PWM3
VW
Vcrs1
Vcrs3
Vcrs2
FIGURE 6. R3™ MODULATOR OPERATION PRINCIPLES IN LOAD
INSERTION RESPONSE
Figure 6 shows the operation principles during load insertion
response. The COMP voltage rises during load insertion,
generating the master clock signal more quickly, so the PWM
pulses turn on earlier, increasing the effective switching
frequency, which allows for higher control loop bandwidth than
conventional fixed frequency PWM controllers. The VW voltage
11
Figure 8 shows the operation principle in diode emulation mode at
light load. The load gets incrementally lighter in the three cases
from top to bottom. The PWM on-time is determined by the VW
window size, therefore is the same, making the inductor current
triangle the same in the three cases. The controller clamps the
master ripple capacitor voltage Vcrm and the slave ripple capacitor
voltage Vcrs in DE mode to make it mimic the inductor current. It
takes the Vcrm longer to hit COMP, naturally stretching the
switching period. The inductor current triangles move further apart
from each other such that the inductor current average value is
equal to the load current. The reduced switching frequency helps
increase light load efficiency.
FN8315.0
May 9, 2013
ISL95839
TABLE 1. VID TABLE
CCM/DCM BOUNDARY
VW
VID
Vcrs
HEX
VO (V)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0.00000
0
0
0
0
0
0
0
1
0
1
0.25000
0
0
0
0
0
0
1
0
0
2
0.25500
0
0
0
0
0
0
1
1
0
3
0.26000
0
0
0
0
0
1
0
0
0
4
0.26500
0
0
0
0
0
1
0
1
0
5
0.27000
0
0
0
0
0
1
1
0
0
6
0.27500
0
0
0
0
0
1
1
1
0
7
0.28000
0
0
0
0
1
0
0
0
0
8
0.28500
0
0
0
0
1
0
0
1
0
9
0.29000
0
0
0
0
1
0
1
0
0
A
0.29500
0
0
0
0
1
0
1
1
0
B
0.30000
0
0
0
0
1
1
0
0
0
C
0.30500
0
0
0
0
1
1
0
1
0
D
0.31000
0
0
0
0
1
1
1
0
0
E
0.31500
0
0
0
0
1
1
1
1
0
F
0.32000
0
0
0
1
0
0
0
0
1
0
0.32500
0
0
0
1
0
0
0
1
1
1
0.33000
0
0
0
1
0
0
1
0
1
2
0.33500
0
0
0
1
0
0
1
1
1
3
0.34000
0
0
0
1
0
1
0
0
1
4
0.34500
0
0
0
1
0
1
0
1
1
5
0.35000
0
0
0
1
0
1
1
0
1
6
0.35500
0
0
0
1
0
1
1
1
1
7
0.36000
0
0
0
1
1
0
0
0
1
8
0.36500
0
0
0
1
1
0
0
1
1
9
0.37000
0
0
0
1
1
0
1
0
1
A
0.37500
0
0
0
1
1
0
1
1
1
B
0.38000
0
0
0
1
1
1
0
0
1
C
0.38500
Voltage Regulation and Load Line
Implementation
0
0
0
1
1
1
0
1
1
D
0.39000
0
0
0
1
1
1
1
0
1
E
0.39500
After the start sequence, the controller regulates the output
voltage to the value set by the VID information per Table 1. The
controller will control the no-load output voltage to an accuracy of
±0.5% over the range of 0.25V to 1.52V. A differential amplifier
allows voltage sensing for precise voltage regulation at the
microprocessor die.
0
0
0
1
1
1
1
1
1
F
0.40000
0
0
1
0
0
0
0
0
2
0
0.40500
0
0
1
0
0
0
0
1
2
1
0.41000
0
0
1
0
0
0
1
0
2
2
0.41500
0
0
1
0
0
0
1
1
2
3
0.42000
0
0
1
0
0
1
0
0
2
4
0.42500
0
0
1
0
0
1
0
1
2
5
0.43000
0
0
1
0
0
1
1
0
2
6
0.43500
iL
VW
LIGHT DCM
Vcrs
iL
VW
DEEP DCM
Vcrs
iL
FIGURE 8. PERIOD STRETCHING
Start-up Timing
With the controller's VDD voltage above the POR threshold, the
start-up sequence begins when VR_ON exceeds the logic high
threshold. Figure 9 shows the typical start-up timing of VR1 and
VR2. The controller uses digital soft-start to ramp-up DAC to the
voltage programmed by the SetVID command. PGOOD is asserted
high and ALERT# is asserted low at the end of the ramp up. Similar
results occur if VR_ON is tied to VDD, with the soft-start sequence
starting 2.6ms after VDD crosses the POR threshold.
VDD
SLEW RATE
VR_ON
2.5mV/µs
VID
COMMAND
VOLTAGE
VID
2.6ms
DAC
PGOOD
…...
ALERT#
FIGURE 9. VR1 SOFT-START WAVEFORMS
12
FN8315.0
May 9, 2013
ISL95839
TABLE 1. VID TABLE (Continued)
TABLE 1. VID TABLE (Continued)
VID
VID
HEX
VO (V)
7
6
5
4
3
2
1
0
7
0.44000
0
1
0
0
1
1
1
0
4
E
0.63500
2
8
0.44500
0
1
0
0
1
1
1
1
4
F
0.64000
1
2
9
0.45000
0
1
0
1
0
0
0
0
5
0
0.64500
1
0
2
A
0.45500
0
1
0
1
0
0
0
1
5
1
0.65000
0
1
1
2
B
0.46000
0
1
0
1
0
0
1
0
5
2
0.65500
1
1
0
0
2
C
0.46500
0
1
0
1
0
0
1
1
5
3
0.66000
0
1
1
0
1
2
D
0.47000
0
1
0
1
0
1
0
0
5
4
0.66500
1
0
1
1
1
0
2
E
0.47500
0
1
0
1
0
1
0
1
5
5
0.67000
0
1
0
1
1
1
1
2
F
0.48000
0
1
0
1
0
1
1
0
5
6
0.67500
0
0
1
1
0
0
0
0
3
0
0.48500
0
1
0
1
0
1
1
1
5
7
0.68000
0
0
1
1
0
0
0
1
3
1
0.49000
0
1
0
1
1
0
0
0
5
8
0.68500
0
0
1
1
0
0
1
0
3
2
0.49500
0
1
0
1
1
0
0
1
5
9
0.69000
0
0
1
1
0
0
1
1
3
3
0.50000
0
1
0
1
1
0
1
0
5
A
0.69500
0
0
1
1
0
1
0
0
3
4
0.50500
0
1
0
1
1
0
1
1
5
B
0.70000
0
0
1
1
0
1
0
1
3
5
0.51000
0
1
0
1
1
1
0
0
5
C
0.70500
0
0
1
1
0
1
1
0
3
6
0.51500
0
1
0
1
1
1
0
1
5
D
0.71000
0
0
1
1
0
1
1
1
3
7
0.52000
0
1
0
1
1
1
1
0
5
E
0.71500
0
0
1
1
1
0
0
0
3
8
0.52500
0
1
0
1
1
1
1
1
5
F
0.72000
0
0
1
1
1
0
0
1
3
9
0.53000
0
1
1
0
0
0
0
0
6
0
0.72500
0
0
1
1
1
0
1
0
3
A
0.53500
0
1
1
0
0
0
0
1
6
1
0.73000
0
0
1
1
1
0
1
1
3
B
0.54000
0
1
1
0
0
0
1
0
6
2
0.73500
0
0
1
1
1
1
0
0
3
C
0.54500
0
1
1
0
0
0
1
1
6
3
0.74000
0
0
1
1
1
1
0
1
3
D
0.55000
0
1
1
0
0
1
0
0
6
4
0.74500
0
0
1
1
1
1
1
0
3
E
0.55500
0
1
1
0
0
1
0
1
6
5
0.75000
0
0
1
1
1
1
1
1
3
F
0.56000
0
1
1
0
0
1
1
0
6
6
0.75500
0
1
0
0
0
0
0
0
4
0
0.56500
0
1
1
0
0
1
1
1
6
7
0.76000
0
1
0
0
0
0
0
1
4
1
0.57000
0
1
1
0
1
0
0
0
6
8
0.76500
0
1
0
0
0
0
1
0
4
2
0.57500
0
1
1
0
1
0
0
1
6
9
0.77000
0
1
0
0
0
0
1
1
4
3
0.58000
0
1
1
0
1
0
1
0
6
A
0.77500
0
1
0
0
0
1
0
0
4
4
0.58500
0
1
1
0
1
0
1
1
6
B
0.78000
0
1
0
0
0
1
0
1
4
5
0.59000
0
1
1
0
1
1
0
0
6
C
0.78500
0
1
0
0
0
1
1
0
4
6
0.59500
0
1
1
0
1
1
0
1
6
D
0.79000
0
1
0
0
0
1
1
1
4
7
0.60000
0
1
1
0
1
1
1
0
6
E
0.79500
0
1
0
0
1
0
0
0
4
8
0.60500
0
1
1
0
1
1
1
1
6
F
0.80000
0
1
0
0
1
0
0
1
4
9
0.61000
0
1
1
1
0
0
0
0
7
0
0.80500
0
1
0
0
1
0
1
0
4
A
0.61500
0
1
1
1
0
0
0
1
7
1
0.81000
0
1
0
0
1
0
1
1
4
B
0.62000
0
1
1
1
0
0
1
0
7
2
0.81500
0
1
0
0
1
1
0
0
4
C
0.62500
0
1
1
1
0
0
1
1
7
3
0.82000
0
1
0
0
1
1
0
1
4
D
0.63000
0
1
1
1
0
1
0
0
7
4
0.82500
7
6
5
4
3
2
1
0
0
0
1
0
0
1
1
1
2
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
1
0
1
0
0
0
1
0
1
0
0
1
0
0
0
1
0
0
0
13
HEX
VO (V)
FN8315.0
May 9, 2013
ISL95839
TABLE 1. VID TABLE (Continued)
TABLE 1. VID TABLE (Continued)
VID
VID
HEX
VO (V)
7
6
5
4
3
2
1
0
5
0.83000
1
0
0
1
1
1
0
0
9
C
1.02500
7
6
0.83500
1
0
0
1
1
1
0
1
9
D
1.03000
1
7
7
0.84000
1
0
0
1
1
1
1
0
9
E
1.03500
0
0
7
8
0.84500
1
0
0
1
1
1
1
1
9
F
1.04000
0
0
1
7
9
0.85000
1
0
1
0
0
0
0
0
A
0
1.04500
1
0
1
0
7
A
0.85500
1
0
1
0
0
0
0
1
A
1
1.05000
1
1
0
1
1
7
B
0.86000
1
0
1
0
0
0
1
0
A
2
1.05500
1
1
1
1
0
0
7
C
0.86500
1
0
1
0
0
0
1
1
A
3
1.06000
1
1
1
1
1
0
1
7
D
0.87000
1
0
1
0
0
1
0
0
A
4
1.06500
0
1
1
1
1
1
1
0
7
E
0.87500
1
0
1
0
0
1
0
1
A
5
1.07000
0
1
1
1
1
1
1
1
7
F
0.88000
1
0
1
0
0
1
1
0
A
6
1.07500
1
0
0
0
0
0
0
0
8
0
0.88500
1
0
1
0
0
1
1
1
A
7
1.08000
1
0
0
0
0
0
0
1
8
1
0.89000
1
0
1
0
1
0
0
0
A
8
1.08500
1
0
0
0
0
0
1
0
8
2
0.89500
1
0
1
0
1
0
0
1
A
9
1.09000
1
0
0
0
0
0
1
1
8
3
0.90000
1
0
1
0
1
0
1
0
A
A
1.09500
1
0
0
0
0
1
0
0
8
4
0.90500
1
0
1
0
1
0
1
1
A
B
1.10000
1
0
0
0
0
1
0
1
8
5
0.91000
1
0
1
0
1
1
0
0
A
C
1.10500
1
0
0
0
0
1
1
0
8
6
0.91500
1
0
1
0
1
1
0
1
A
D
1.11000
1
0
0
0
0
1
1
1
8
7
0.92000
1
0
1
0
1
1
1
0
A
E
1.11500
1
0
0
0
1
0
0
0
8
8
0.92500
1
0
1
0
1
1
1
1
A
F
1.12000
1
0
0
0
1
0
0
1
8
9
0.93000
1
0
1
1
0
0
0
0
B
0
1.12500
1
0
0
0
1
0
1
0
8
A
0.93500
1
0
1
1
0
0
0
1
B
1
1.13000
1
0
0
0
1
0
1
1
8
B
0.94000
1
0
1
1
0
0
1
0
B
2
1.13500
1
0
0
0
1
1
0
0
8
C
0.94500
1
0
1
1
0
0
1
1
B
3
1.14000
1
0
0
0
1
1
0
1
8
D
0.95000
1
0
1
1
0
1
0
0
B
4
1.14500
1
0
0
0
1
1
1
0
8
E
0.95500
1
0
1
1
0
1
0
1
B
5
1.15000
1
0
0
0
1
1
1
1
8
F
0.96000
1
0
1
1
0
1
1
0
B
6
1.15500
1
0
0
1
0
0
0
0
9
0
0.96500
1
0
1
1
0
1
1
1
B
7
1.16000
1
0
0
1
0
0
0
1
9
1
0.97000
1
0
1
1
1
0
0
0
B
8
1.16500
1
0
0
1
0
0
1
0
9
2
0.97500
1
0
1
1
1
0
0
1
B
9
1.17000
1
0
0
1
0
0
1
1
9
3
0.98000
1
0
1
1
1
0
1
0
B
A
1.17500
1
0
0
1
0
1
0
0
9
4
0.98500
1
0
1
1
1
0
1
1
B
B
1.18000
1
0
0
1
0
1
0
1
9
5
0.99000
1
0
1
1
1
1
0
0
B
C
1.18500
1
0
0
1
0
1
1
0
9
6
0.99500
1
0
1
1
1
1
0
1
B
D
1.19000
1
0
0
1
0
1
1
1
9
7
1.00000
1
0
1
1
1
1
1
0
B
E
1.19500
1
0
0
1
1
0
0
0
9
8
1.00500
1
0
1
1
1
1
1
1
B
F
1.20000
1
0
0
1
1
0
0
1
9
9
1.01000
1
1
0
0
0
0
0
0
C
0
1.20500
1
0
0
1
1
0
1
0
9
A
1.01500
1
1
0
0
0
0
0
1
C
1
1.21000
1
0
0
1
1
0
1
1
9
B
1.02000
1
1
0
0
0
0
1
0
C
2
1.21500
7
6
5
4
3
2
1
0
0
1
1
1
0
1
0
1
7
0
1
1
1
0
1
1
0
0
1
1
1
0
1
1
0
1
1
1
1
0
0
1
1
1
1
0
1
1
1
0
1
1
0
1
0
14
HEX
VO (V)
FN8315.0
May 9, 2013
ISL95839
TABLE 1. VID TABLE (Continued)
TABLE 1. VID TABLE (Continued)
VID
VID
HEX
VO (V)
7
6
5
4
3
2
1
0
3
1.22000
1
1
1
0
1
0
1
0
E
A
1.41500
C
4
1.22500
1
1
1
0
1
0
1
1
E
B
1.42000
1
C
5
1.23000
1
1
1
0
1
1
0
0
E
C
1.42500
1
0
C
6
1.23500
1
1
1
0
1
1
0
1
E
D
1.43000
1
1
1
C
7
1.24000
1
1
1
0
1
1
1
0
E
E
1.43500
1
0
0
0
C
8
1.24500
1
1
1
0
1
1
1
1
E
F
1.44000
0
1
0
0
1
C
9
1.25000
1
1
1
1
0
0
0
0
F
0
1.44500
0
0
1
0
1
0
C
A
1.25500
1
1
1
1
0
0
0
1
F
1
1.45000
1
0
0
1
0
1
1
C
B
1.26000
1
1
1
1
0
0
1
0
F
2
1.45500
1
1
0
0
1
1
0
0
C
C
1.26500
1
1
1
1
0
0
1
1
F
3
1.46000
1
1
0
0
1
1
0
1
C
D
1.27000
1
1
1
1
0
1
0
0
F
4
1.46500
1
1
0
0
1
1
1
0
C
E
1.27500
1
1
1
1
0
1
0
1
F
5
1.47000
1
1
0
0
1
1
1
1
C
F
1.28000
1
1
1
1
0
1
1
0
F
6
1.47500
1
1
0
1
0
0
0
0
D
0
1.28500
1
1
1
1
0
1
1
1
F
7
1.48000
1
1
0
1
0
0
0
1
D
1
1.29000
1
1
1
1
1
0
0
0
F
8
1.48500
1
1
0
1
0
0
1
0
D
2
1.29500
1
1
1
1
1
0
0
1
F
9
1.49000
1
1
0
1
0
0
1
1
D
3
1.30000
1
1
1
1
1
0
1
0
F
A
1.49500
1
1
0
1
0
1
0
0
D
4
1.30500
1
1
1
1
1
0
1
1
F
B
1.50000
1
1
0
1
0
1
0
1
D
5
1.31000
1
1
1
1
1
1
0
0
F
C
1.50500
1
1
0
1
0
1
1
0
D
6
1.31500
1
1
1
1
1
1
0
1
F
D
1.51000
1
1
0
1
0
1
1
1
D
7
1.32000
1
1
1
1
1
1
1
0
F
E
1.51500
1
1
0
1
1
0
0
0
D
8
1.32500
1
1
1
1
1
1
1
1
F
F
1.52000
1
1
0
1
1
0
0
1
D
9
1.33000
1
1
0
1
1
0
1
0
D
A
1.33500
1
1
0
1
1
0
1
1
D
B
1.34000
1
1
0
1
1
1
0
0
D
C
1.34500
1
1
0
1
1
1
0
1
D
D
1.35000
1
1
0
1
1
1
1
0
D
E
1.35500
1
1
0
1
1
1
1
1
D
F
1.36000
1
1
1
0
0
0
0
0
E
0
1.36500
7
6
5
4
3
2
1
0
1
1
0
0
0
0
1
1
C
1
1
0
0
0
1
0
0
1
1
0
0
0
1
0
1
1
0
0
0
1
1
1
0
0
0
1
1
0
0
1
1
0
1
1
1
1
1
1
0
0
0
0
1
E
1
1.37000
1
1
1
0
0
0
1
0
E
2
1.37500
1
1
1
0
0
0
1
1
E
3
1.38000
1
1
1
0
0
1
0
0
E
4
1.38500
1
1
1
0
0
1
0
1
E
5
1.39000
1
1
1
0
0
1
1
0
E
6
1.39500
1
1
1
0
0
1
1
1
E
7
1.40000
1
1
1
0
1
0
0
0
E
8
1.40500
1
1
1
0
1
0
0
1
E
9
1.41000
15
HEX
VO (V)
Rdroop
VCCSENSE
Vdroop
FB
VR LOCAL VO
CATCH
RESISTOR
Idroop
E/A
COMP

VIDs
VID
DAC
VDAC
RTN
VSSSENSE
INTERNAL TO IC
X1
VSS
CATCH
RESISTOR
FIGURE 10. DIFFERENTIAL SENSING AND LOAD LINE
IMPLEMENTATION
FN8315.0
May 9, 2013
ISL95839
As the load current increases from zero, the output voltage will
droop from the VID table value by an amount proportional to the
load current to achieve the load line. The controller can sense the
inductor current through the intrinsic DC Resistance (DCR) of the
inductors (as shown in Figure 3 on page 6) or through resistors in
series with the inductors (as shown in Figure 4 on page 10). In
both methods, capacitor Cn voltage represents the inductor total
currents. A droop amplifier converts Cn voltage into an internal
current source with the gain set by resistor Ri. The current source
is used for load line implementation, current monitor and
overcurrent protection.
Figure 10 shows the load line implementation. The controller
drives a current source Idroop out of the FB pin, described by
Equation 1.
V Cn
I droop = ----------Ri
Rewriting Equation 4 and substitution of Equation 2 gives:
VCCSENSE – VSS SENSE = V DAC – R droop  I droop
Equation 5 is the exact equation required for load line
implementation.
The VCCSENSE and VSSSENSE signals come from the processor die.
The feedback will be open circuit in the absence of the processor. As
Figure 10 shows, it is recommended to add a “catch” resistor to feed
the VR local output voltage back to the compensator, and add
another “catch” resistor to connect the VR local output ground to the
RTN pin. These resistors, typically 10Ω~100Ω, will provide voltage
feedback if the system is powered up without a processor installed.
Phase Current Balancing
(EQ. 1)
When using inductor DCR current sensing, a single NTC element
is used to compensate the positive temperature coefficient of the
copper winding thus sustaining the load line accuracy with
reduced cost.
Idroop flows through resistor Rdroop and creates a voltage drop,
as shown in Equation 2.
V droop = R droop  I droop
(EQ. 2)
Vdroop is the droop voltage required to implement load line.
Changing Rdroop or scaling Idroop can both change the load line
slope. Since Idroop also sets the overcurrent protection level, it is
recommended to first scale Idroop based on OCP requirement,
then select an appropriate Rdroop value to obtain the desired
load line slope.
Current Monitor
The controller provides the current monitor function. IMON and
IMONG pin reports the inductor current for bothe VRs respectively.
The IMON pin outputs a high-speed analog current source that is
1/4 of the droop current flowing out of the FB pin as Equation 3:
(EQ. 5)
Rdcr3
L3
ISEN3
Phase3
Risen
Cisen
INTERNAL
TO IC
ISEN2
ISEN1
IL3
L2
Phase2
Risen
Cisen
Phase1
Risen
Rpcb3
Rdcr2
Rpcb2
Vo
IL2
Rdcr1
L1
Rpcb1
IL1
Cisen
FIGURE 11. CURRENT BALANCING CIRCUIT
The controller monitors individual phase average current by
monitoring the ISEN1, ISEN2, and ISEN3 voltages. Figure 11
shows the recommended current balancing circuit. Each phase
node voltage is averaged by a low-pass filter consisting of Risen
and Cisen, and presented to the corresponding ISEN pin. Risen
should be routed to inductor phase-node pad in order to eliminate
the effect of phase node parasitic PCB DCR. Equations 6 thru 8
give the ISEN pin voltages:
(EQ. 3)
V ISEN1 =  R dcr1 + R pcb1   I L1
(EQ. 6)
A resistor Rimon is connected to the IMON pin to convert the IMON
pin current to voltage. A capacitor should be paralleled with Rimon to
filter the voltage information.
V ISEN2 =  R dcr2 + R pcb2   I L2
(EQ. 7)
V ISEN3 =  R dcr3 + R pcb3   I L3
(EQ. 8)
I IMON = 0.25  I droop
The IMON pin voltage range is 0V to 1.2V. The controller monitors
the IMON pin voltage and considers that ISL95839 has reached
ICCMAX when IMON pin voltage is 1.2V.
IMONG pin has the same operation principle as IMON pin.
Differential Voltage Sensing
Figure 10 also shows the differential voltage sensing scheme.
VCCSENSE and VSSSENSE are the remote voltage sensing signals
from the processor die. A unity gain differential amplifier senses
the VSSSENSE voltage and adds it to the DAC output. The error
amplifier regulates the inverting and the non-inverting input
voltages to be equal, as shown in Equation 4:
VCC SENSE + V
droop
= V DAC + VSS SENSE
16
(EQ. 4)
where Rdcr1, Rdcr2 and Rdcr3 are inductor DCR; Rpcb1, Rpcb2
and Rpcb3 are parasitic PCB DCR between the inductor output
side pad and the output voltage rail; and IL1, IL2 and IL3 are
inductor average currents.
The controller will adjust the phase pulse-width relative to the
other phases to make VISEN1 = VISEN2 = VISEN3, thus to achieve
IL1 = IL2 = IL3, when there are Rdcr1 = Rdcr2 = Rdcr3 and
Rpcb1 = Rpcb2 = Rpcb3.
Using the same components for L1, L2 and L3 will provide a good
match of Rdcr1, Rdcr2 and Rdcr3. Board layout will determine
Rpcb1, Rpcb2 and Rpcb3. It is recommended to have symmetrical
layout for the power delivery path between each inductor and the
output voltage rail, such that Rpcb1 = Rpcb2 = Rpcb3.
FN8315.0
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ISL95839
Phase3
Risen
ISEN3
Cisen
INTERNAL
TO IC
ISEN2
Cisen
L3
V3p
Rdcr3
IL3
Risen
The controller will make VISEN1 = VISEN2 = VISEN3, as shown in
Equations 12 and 13:
Rpcb3
V3n
Risen
L2
V2p
Phase2
Risen
Rdcr2
IL2
Risen
Rpcb2
Vo
(EQ. 12)
V 1n + V 2p + V 3n = V 1n + V 2n + V 3p
(EQ. 13)
Rewriting Equation 12 gives Equation 14:
V 1p – V 1n = V 2p – V 2n
(EQ. 14)
V2n
and rewriting Equation 13 gives Equation 15:
Risen
L1
V1p
ISEN1
Cisen
V 1p + V 2n + V 3n = V 1n + V 2p + V 3n
Rdcr1
V 2p – V 2n = V 3p – V 3n
(EQ. 15)
Rpcb1
Combining Equations 14 and 15 gives:
Phase1
Risen
IL1
Risen
V 1p – V 1n = V 2p – V 2n = V 3p – V 3n
V1n
(EQ. 16)
Therefore:
Risen
FIGURE 12. DIFFERENTIAL-SENSING CURRENT BALANCING CIRCUIT
Sometimes, it is difficult to implement symmetrical layout. For
the circuit shown in Figure 11, asymmetric layout causes
different Rpcb1, Rpcb2 and Rpcb3 thus current imbalance.
Figure 12 shows a recommended differential-sensing current
balancing circuit. The current sensing traces should be routed to
the inductor pads so they only pick up the inductor DCR voltage.
Each ISEN pin sees the average voltage of three sources: its own
phase inductor phase-node pad, and the other two phases
inductor output side pads. Equations 9 thru 11 give the ISEN pin
voltages:
V ISEN1 = V 1p + V 2n + V 3n
(EQ. 9)
V ISEN2 = V 1n + V 2p + V 3n
(EQ. 10)
V ISEN3 = V 1n + V 2n + V 3p
(EQ. 11)
17
R dcr1  I L1 = R dcr2  I L2 = R dcr3  I L3
(EQ. 17)
Current balancing (IL1 = IL2 = IL3) will be achieved when there is
Rdcr1 = Rdcr2 = Rdcr3. Rpcb1, Rpcb2 and Rpcb3 will not have any
effect.
Since the slave ripple capacitor voltages mimic the inductor
currents, R3™ modulator can naturally achieve excellent current
balancing during steady state and dynamic operations. Figure 13
shows current balancing performance of the evaluation board
with load transient of 12A/51A at different rep rates. The
inductor currents follow the load current dynamic change with
the output capacitors supplying the difference. The inductor
currents can track the load current well at low rep rate, but
cannot keep up when the rep rate gets into the hundred-kHz
range, where it’s out of the control loop bandwidth. The controller
achieves excellent current balancing in all cases.
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ISL95839
CCM Switching Frequency
REP RATE = 10kHz
REP RATE = 25kHz
The resistor from COMPG and GND sets four different switching
frequencies: 300kHz, 350kHz, 400kHz and 450kHz. Please refer
to Table 8 on page 27 for details.
To improve the efficiency at low VID, fixed on-time and period
stretching will be implemented and CCM switching frequency will
be proportional to the VID. The switching frequency will be
stretched to 150kHz when VID = 0.25V. The VID starting to period
stretching will be 0.5V*fSW_SET/300. For example, period
stretching will start at VID = 0.5V with 300kHz switching
frequency setting, and period stretching will start at VID = 0.75V
with 450kHz switching frequency setting.
Modes of Operation
TABLE 2. VR1 MODES OF OPERATION
PWM3
To
External
Driver
ISEN2
To
Power
Stage
CONFIG.
3-phase
CPU VR
Config.
REP RATE = 50kHz
PS
MODE
OCP
THRESHOLD
(µA)
0
3-phase CCM
60
1
2-phase CCM
40
2
1-phase DE
20
3
Tied to 5V
2-phase
CPU VR
Config.
0
2-phase CCM
60
1
1-phase CCM
30
2
1-phase DE
1-phase
CPU VR
Config.
0
3
Tied to
5V
1-phase CCM
60
1
2
1-phase DE
3
REP RATE = 100kHz
VR1 can be configured for 3, 2 or 1-phase operation. Table 2
shows VR1 configurations and operational modes, programmed
by the PWM3 pin and the ISEN2 pin status, and the PS
command. For 2-phase configuration, tie the PWM3 pin to 5V. In
this configuration, phases 1 and 2 are active. For 1-phase
configuration, tie the PWM3 pin and the ISEN2 pin to 5V. In this
configuration, only phase-1 is active.
REP RATE = 200kHz
In 3-phase configuration, VR1 operates in 3-phase CCM in PS0. It
enters 2-phase CCM mode in PS1 by dropping phase 3 and
reducing the overcurrent and the way-overcurrent protection
levels to 2/3 of the initial values. It enters 1-phase DE mode in
PS2 and PS3 by dropping phase 2, phase 3 and reducing the
overcurrent and the way-overcurrent protection levels to 1/3 of
the initial values.
In 2-phase configuration, VR1 operates in 2-phase CCM in PS0. It
enters 1-phase CCM mode in PS1, and enters 1-phase DE mode
in PS2 and PS3 by dropping phase 2, and reducing the
overcurrent and the way-overcurrent protection levels to 1/2 of
the initial values.
FIGURE 13. CURRENT BALANCING DURING DYNAMIC OPERATION.
CH1: IL1, CH2: ILOAD, CH3: IL2, CH4: IL3
18
In 1-phase configuration, VR1 operates in 1-phase CCM in PS0
and PS1, and enters 1-phase DE mode in PS2 and PS3.
FN8315.0
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ISL95839
Table 3 shows VR2 operational modes, programmed by the PS
command. VR2 operates in CCM in PS0 and PS1, and enters DE
mode in PS2 and PS3.
VR2 can be disabled completely by tying ISUMNG to 5V, and all
communication to VR2 will be rejected.
TABLE 3. VR2 MODES OF OPERATION
PS
0
OCP THRESHOLD
(µA)
MODE
1-phase CCM
VR_HOT#/ALERT# Behavior
VR Temperature
Temp Zone
Bit 7 =1
7
1
Bit 6 =1
3% Hysteris
1111 1111
10
0111 1111
0011 1111
Bit 5 =1
12
60
1
2
The R3™ modulator intrinsically has voltage feed-forward. The
output voltage is insensitive to a fast slew rate input voltage change.
0001 1111
Temp Zone
Register
2
8
0001 1111 0011 1111 0111 1111 1111 1111 0111 1111 0011 1111 0001 1111
Status 1
3
= “011”
= “001”
Register = “001”
1-phase DE
3
Dynamic Operation
VR1 and VR2 behave the same during dynamic operation. The
controller responds to VID changes by slewing to the new voltage
at a slew rate indicated in the SetVID command. There are three
SetVID slew rates, namely SetVID_fast, SetVID_slow and
SetVID_decay.
SetVID_fast command prompts the controller to enter CCM and
to actively drive the output voltage to the new VID value at a
minimum 10mV/µs slew rate.
SetVID_slow command prompts the controller to enter CCM and
to actively drive the output voltage to the new VID value at a
minimum 2.5mV/µs slew rate.
S e tV ID _ d e c a y
S e tV ID _ fa s t/s lo w
Vo
GerReg
Status1
SVID
ALERT#
4
VR_HOT#
5
13
6
14
9
GerReg
Status1
15
16
11
FIGURE 15. VR_HOT#/ALERT# BEHAVIOR
The controller drives 60µA current source out of the NTC pin and
the NTCG pin alternatively at approximately 36kHz frequency
with 50% duty cycle. The current source flows through the
respective NTC resistor networks on the pins and creates
voltages that are monitored by the controller through an A/D
converter (ADC) to generate the TZONE value. Table 4 shows the
programming table for TZONE. The user needs to scale the NTC
and the NTCG network resistance such that it generates the NTC
(and NTCG) pin voltage that corresponds to the left-most column.
Do not use any capacitor to filter the voltage.
TABLE 4. TZONE TABLE
V ID
t3
t1
T _ a le r t
t2
ALERT#
FIGURE 14. SETVID DECAY PRE-EMPTIVE BEHAVIOR
SetVID_decay command prompts the controller to enter DE mode.
The output voltage will decay down to the new VID value at a slew
rate determined by the load. If the voltage decay rate is too fast, the
controller will limit the voltage slew rate at 10mV/µs.
ALERT# will be asserted low at the end of SetVID_fast and
SetVID_slow VID transitions.
Figure 14 shows SetVID Decay Pre-Emptive behavior. The
controller receives a SetVID_decay command at t1. The VR
enters DE mode and the output voltage Vo decays down slowly.
At t2, before Vo reaches the intended VID target of the
SetVID_decay command, the controller receives a SetVID_fast (or
SetVID_slow) command to go to a voltage higher than the actual
Vo. The controller will turn around immediately and slew Vo to the
new target voltage at the slew rate specified by the SetVID
command. At t3, Vo reaches the new target voltage and the
controller asserts the ALERT# signal.
VNTC (V)
TMAX (%)
TZONE
0.84
>100
FFh
0.88
100
FFh
0.92
97
7Fh
0.96
94
3Fh
1.00
91
1Fh
1.04
88
0Fh
1.08
85
07h
1.12
82
03h
1.16
79
01h
1.2
76
01h
>1.2
<76
00h
Figure 15 shows how the NTC and the NTCG network should be
designed to get correct VR_HOT#/ALERT# behavior when the
system temperature rises and falls, manifested as the NTC and the
NTCG pin voltage falls and rises. The series of events are:
1. The temperature rises so the NTC pin (or the NTCG pin)
voltage drops. TZONE value changes accordingly.
2. The temperature crosses the threshold where TZONE register
Bit 6 changes from 0 to 1.
3. The controller changes Status_1 register bit 1 from 0 to 1.
19
FN8315.0
May 9, 2013
ISL95839
4. The controller asserts ALERT#.
5. The CPU reads Status_1 register value to know that the alert
assertion is due to TZONE register Bit 6 flipping.
Adaptive Body Diode Conduction Time
Reduction
14. The controller asserts ALERT#.
In DCM, the controller turns off the low-side MOSFET when the
inductor current approaches zero. During on-time of the low-side
MOSFET, phase voltage is negative and the amount is the
MOSFET rDS(ON) voltage drop, which is proportional to the
inductor current. A phase comparator inside the controller
monitors the phase voltage during on-time of the low-side
MOSFET and compares it with a threshold to determine the
zero-crossing point of the inductor current. If the inductor current
has not reached zero when the low-side MOSFET turns off, it’ll
flow through the low-side MOSFET body diode, causing the phase
node to have a larger voltage drop until it decays to zero. If the
inductor current has crossed zero and reversed the direction
when the low-side MOSFET turns off, it’ll flow through the
high-side MOSFET body diode, causing the phase node to have a
spike until it decays to zero. The controller continues monitoring
the phase voltage after turning off the low-side MOSFET and
adjusts the phase comparator threshold voltage accordingly in
iterative steps such that the low-side MOSFET body diode
conducts for approximately 40ns to minimize the body
diode-related loss.
15. The CPU reads Status_1 register value to know that the alert
assertion is due to TZONE register Bit 5 flipping.
Protections
6. The controller clears ALERT#.
7. The temperature continues rising.
8. The temperature crosses the threshold where TZONE register
Bit 7 changes from 0 to 1.
9. The controllers asserts VR_HOT# signal. The CPU throttles
back and the system temperature starts dropping eventually.
10. The temperature crosses the threshold where TZONE register
Bit 6 changes from 1 to 0. This threshold is 1 ADC step lower
than the one when VR_HOT# gets asserted, to provide 3%
hysteresis.
11. The controllers de-asserts VR_HOT# signal.
12. The temperature crosses the threshold where TZONE register
Bit 5 changes from 1 to 0. This threshold is 1 ADC step lower
than the one when ALERT# gets asserted during the
temperature rise to provide 3% hysteresis.
13. The controller changes Status_1 register bit 1 from 1 to 0.
16. The controller clears ALERT#.
FB2 Function
C1 R2
CONTROLLER IN
3- AND 2-PHASE
MODE
C2 R3
C3.1
C2 R3
C3.2
FB2
R1
VSEN
VSEN
E/A
FB
VREF
C1 R2
CONTROLLER IN
1-PHASE MODE
The controller determines overcurrent protection (OCP) by
comparing the average value of the droop current Idroop with an
internal current source threshold as Table 2 shows. It declares OCP
when Idroop is above the threshold for 120µs.
C3.1
FB2
C3.2
R1
COMP
FB
VREF
E/A
COMP
FIGURE 16. FB2 FUNCTION
Figure 16 shows the FB2 function. A switch (called FB2 switch)
turns on to short the FB and the FB2 pins when the controller is in
2-phase mode. Capacitors C3.1 and C3.2 are in parallel, serving as
part of the compensator. When the controller enters 1-phase
mode, the FB2 switch turns off, removing C3.2 and leaving only
C3.1 in the compensator. The compensator gain will increase with
the removal of C3.2. By properly sizing C3.1 and C3.2, the
compensator can be optimal for both 3-, 2-phase mode and
1-phase mode.
When the FB2 switch is off, C3.2 is disconnected from the FB pin.
However, the controller still actively drives the FB2 pin voltage to
follow the FB pin voltage such that C3.2 voltage always follows
C3.1 voltage. When the controller turns on the FB2 switch, C3.2
will be reconnected to the compensator smoothly.
The FB2 function ensures excellent transient response in both 3-,
2-phase mode and 1-phase mode. If one decides not to use the
FB2 function, simply populate C3.1 only.
20
VR1 and VR2 both provide overcurrent, current-balance and
overvoltage fault protections. The controller also provides
over-temperature protection. The following discussion is based on
VR1 and also applies to VR2.
For overcurrent conditions above 1.5x the OCP level, the PWM
outputs will immediately shut off and PGOOD will go low to
maximize protection. This protection is also referred to as
way-overcurrent protection or fast-overcurrent protection, for
short-circuit protection.
The controller monitors the ISEN pin voltages to determine
current-balance protection. If the difference of one ISEN pin
voltage and the average ISENs pin voltage is greater than 9mV for
at least 3.2ms, the controller will declare a fault and latch off.
The controller takes the same actions for all of the above fault
protections: de-assertion of both PGOODs and turn-off of all the
high-side and low-side power MOSFETs. Any residual inductor
current will decay through the MOSFET body diodes.
The controller will declare an overvoltage fault and de-assert PGOOD
if the output voltage exceeds the VID set value by +200mV. The
controller will immediately declare an OV fault, de-assert PGOOD,
and turn on the low-side power MOSFETs. The low-side power
MOSFETs remain on until the output voltage is pulled down below
the VID set value when all power MOSFETs are turned off. If the
output voltage rises above the VID set value +200mV again, the
protection process is repeated. This behavior provides the
maximum amount of protection against shorted high-side power
MOSFETs while preventing output ringing below ground.
FN8315.0
May 9, 2013
ISL95839
The overvoltage fault threshold is 1.7V when output voltage
ramps up from 0V. And the overvoltage fault threshold is restored
to VID set value + 200mV after the output voltage settles.
All the above fault conditions can be reset by bringing VR_ON low
or by bringing VDD below the POR threshold. When VR_ON and
VDD return to their high operating levels, a soft-start will occur.
TABLE 6. SUPPORTED DATA AND CONFIGURATION
REGISTERS (Continued)
INDEX
REGISTER
NAME
ICC max
Data register containing the ICC max Refer to
the platform supports, set at start-up by Table 7
resistors Rprog1 and Rprog2. The
platform design engineer programs this
value during the design process. Binary
format in amps, i.e., 100A = 64h
22h
Temp max
Not supported
24h
SR-fast
Slew Rate Normal. The fastest slew rate 0Ah
the platform VR can sustain. Binary
format in mV/µs. i.e., 0Ah = 10mV/µs.
25h
SR-slow
Is 4x slower than normal. Binary format 02h
in mV/µs. i.e., 02h = 2.5mV/µs
26h
VBOOT
If programmed by the platform, the VR 00h
supports VBOOT voltage during start-up
ramp. The VR will ramp to VBOOT and
hold at VBOOT until it receives a new
SetVID command to move to a different
voltage.
30h
Vout max
FBh
This register is programmed by the
master and sets the maximum VID the
VR will support. If a higher VID code is
received, the VR will respond with “not
supported” acknowledge.
31h
VID Setting
Data register containing currently
programmed VID voltage. VID data
format.
DEFAULT
VALUE
32h
Power State Register containing the current
programmed power state.
33h
Voltage
Offset
00h
Sets offset in VID steps added to the
VID setting for voltage margining. Bit 7
is a sign bit, 0 = positive margin,
1 = negative margin. Remaining 7 bits
are # VID steps for the margin.
00h = no margin,
01h = +1 VID step
02h = +2 VID steps...
34h
Multi VR
Config
Data register that configures multiple
VRs behavior on the same SVID bus.
TABLE 5. FAULT PROTECTION SUMMARY
FAULT TYPE
Overcurrent
120µs
Phase Current
Unbalance
3.2ms
Way-Overcurrent
(1.5xOC)
PROTECTION
ACTION
PWM tri-state,
PGOOD latched
low
FAULT
RESET
VR_ON
toggle or
VDD toggle
Immediately
Overvoltage +200mV
PGOOD latched
low. Actively pulls
the output voltage
to below VID value,
then tri-state.
1.7V overvoltage
during output voltage
ramp up from 0V
Supported Data and Configuration Registers
The controller supports the following data and configuration
registers.
TABLE 6. SUPPORTED DATA AND CONFIGURATION
REGISTERS
INDEX
REGISTER
NAME
DESCRIPTION
00h
Vendor ID
Uniquely identifies the VR vendor.
Assigned by Intel.
12h
01h
Product ID
Uniquely identifies the VR product.
Intersil assigns this number.
24h
02h
Product
Revision
Uniquely identifies the revision of the
VR control IC. Intersil assigns this data.
05h
Protocol ID
Identifies what revision of SVID protocol 01h
the controller supports.
06h
Capability
Identifies the SVID VR capabilities and 81h
which of the optional telemetry
registers are supported.
10h
Status_1
Data register read after ALERT# signal. 00h
Indicating if a VR rail has settled, has
reached VRHOT condition or has
reached ICC max.
11h
Status_2
Data register showing status_2
communication.
12h
Temperature Data register showing temperature
Zone
zones that have been entered.
00h
1Ch
Status_2_
LastRead
00h
This register contains a copy of the
Status_2 data that was last read with
the GetReg (Status_2) command.
21
DEFAULT
VALUE
21h
Table 5 summarizes the fault protections.
FAULT DURATION
BEFORE
PROTECTION
DESCRIPTION
00h
00h
VR1: 00h
VR2: 01h
00h
FN8315.0
May 9, 2013
ISL95839
Key Component Selection
1
 sns = -------------------------------------------------------R sum
R ntcnet  --------------N
------------------------------------------  C n
R sum
R ntcnet + --------------N
Inductor DCR Current-Sensing Network
Phase1
Phase2
Phase3
Rsum
where N is the number of phases.
Rsum
ISUM+
Rsum
L
L
L
Rntcs
Rp
DCR
DCR
DCR
Cn Vcn
Rntc
Ro
Ri
ISUM-
Ro
Ro
Io
FIGURE 17. DCR CURRENT-SENSING NETWORK
Figure 17 shows the inductor DCR current-sensing network for a
3-phase solution. An inductor current flows through the DCR and
creates a voltage drop. Each inductor has two resistors in Rsum
and Ro connected to the pads to accurately sense the inductor
current by sensing the DCR voltage drop. The Rsum and Ro
resistors are connected in a summing network as shown, and feed
the total current information to the NTC network (consisting of
Rntcs, Rntc and Rp) and capacitor Cn. Rntc is a negative
temperature coefficient (NTC) thermistor, used to
temperature-compensate the inductor DCR change.
The inductor output side pads are electrically shorted in the
schematic, but have some parasitic impedance in actual board
layout, which is why one cannot simply short them together for the
current-sensing summing network. It is recommended to use
1Ω~10ΩRo to create quality signals. Since Ro value is much smaller
than the rest of the current sensing circuit, the following analysis will
ignore it for simplicity.
The summed inductor current information is presented to the
capacitor Cn. Equations 18 thru 22 describe the
frequency-domain relationship between inductor total current
Io(s) and Cn voltage VCn(s):


R ntcnet

DCR
V Cn  s  =  ------------------------------------------  -------------  I o  s   A cs  s 
R sum
N 

 R ntcnet + -------------
N
(EQ. 18)
 R ntcs + R ntc   R p
R ntcnet = ---------------------------------------------------R ntcs + R ntc + R p
(EQ. 19)
s
1 + ------L
A cs  s  = ----------------------s
1 + ------------ sns
(EQ. 20)
DCR
 L = ------------L
(EQ. 21)
22
(EQ. 22)
Transfer function Acs(s) always has unity gain at DC. The inductor
DCR value increases as the winding temperature increases,
giving higher reading of the inductor DC current. The NTC Rntc
values decrease as its temperature decreases. Proper selections
of Rsum, Rntcs, Rp and Rntc parameters ensure that VCn
represent the inductor total DC current over the temperature
range of interest.
There are many sets of parameters that can properly
temperature-compensate the DCR change. Since the NTC network
and the Rsum resistors form a voltage divider, Vcn is always a
fraction of the inductor DCR voltage. It is recommended to have a
higher ratio of Vcn to the inductor DCR voltage, so the droop circuit
has a higher signal level to work with.
A typical set of parameters that provide good temperature
compensation are: Rsum = 3.65kΩ, Rp = 11kΩ, Rntcs = 2.61kΩ
and Rntc = 10kΩ (ERT-J1VR103J). The NTC network parameters
may need to be fine tuned on actual boards. One can apply full
load DC current and record the output voltage reading
immediately; then record the output voltage reading again when
the board has reached the thermal steady state. A good NTC
network can limit the output voltage drift to within 2mV. It is
recommended to follow the Intersil evaluation board layout and
current-sensing network parameters to minimize engineering
time.
VCn(s) also needs to represent real-time Io(s) for the controller to
achieve good transient response. Transfer function Acs(s) has a
pole wsns and a zero wL. One needs to match wL and wsns so
Acs(s) is unity gain at all frequencies. By forcing wL equal to wsns
and solving for the solution, Equation 23 gives the Cn value.
L
C n = --------------------------------------------------------------R sum
R ntcnet  --------------N
----------------------------------------- DCR
R sum
R ntcnet + --------------N
(EQ. 23)
For example, given N = 3, Rsum = 3.65kΩ, Rp = 11kΩ,
Rntcs = 2.61kΩ, Rntc = 10kΩ, DCR = 0.9mΩ and L = 0.36µH,
Equation 23 gives Cn = 0.397µF.
Assuming the compensator design is correct, Figure 18 shows the
expected load transient response waveforms if Cn is correctly
selected. When the load current Icore has a square change, the
output voltage Vcore also has a square response.
If Cn value is too large or too small, VCn(s) will not accurately
represent real-time Io(s) and will worsen the transient response.
Figure 19 shows the load transient response when Cn is too
small. Vcore will sag excessively upon load insertion and may
create a system failure. Figure 20 shows the transient response
when Cn is too large. Vcore is sluggish in drooping to its final
value. There will be excessive overshoot if load insertion occurs
during this time, which may potentially hurt the CPU reliability.
FN8315.0
May 9, 2013
ISL95839
ISUM+
io
Rntcs
Cn.1
Cn.2 Vcn
Rp
Vo
Rntc
FIGURE 18. DESIRED LOAD TRANSIENT RESPONSE WAVEFORMS
Rn
OPTIONAL
Rip
io
ISUM-
Ri
Cip
OPTIONAL
FIGURE 22. OPTIONAL CIRCUITS FOR RING BACK REDUCTION
Vo
FIGURE 19. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO SMALL
io
Figure 22 shows two optional circuits for reduction of the ring
back.
Vo
FIGURE 20. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO LARGE
io
Figure 21 shows the output voltage ring back problem during
load transient response. The load current io has a fast step
change, but the inductor current iL cannot accurately follow.
Instead, iL responds in first order system fashion due to the
nature of current loop. The ESR and ESL effect of the output
capacitors makes the output voltage Vo dip quickly upon load
current change. However, the controller regulates Vo according to
the droop current idroop, which is a real-time representation of iL;
therefore it pulls Vo back to the level dictated by iL, causing the
ring back problem. This phenomenon is not observed when the
output capacitor have very low ESR and ESL, such as all ceramic
capacitors.
iL
Vo
RING
BACK
FIGURE 21. OUTPUT VOLTAGE RING BACK PROBLEM
Cn is the capacitor used to match the inductor time constant. It
usually takes the parallel of two (or more) capacitors to get the
desired value. Figure 22 shows that two capacitors Cn.1 and Cn.2
are in parallel. Resistor Rn is an optional component to reduce
the Vo ring back. At steady state, Cn.1 + Cn.2 provides the desired
Cn capacitance. At the beginning of io change, the effective
capacitance is less because Rn increases the impedance of the
Cn.1 branch. As Figure 19 explains, Vo tends to dip when Cn is too
small, and this effect will reduce the Vo ring back. This effect is
more pronounced when Cn.1 is much larger than Cn.2. It is also
more pronounced when Rn is bigger. However, the presence of
Rn increases the ripple of the Vn signal if Cn.2 is too small. It is
recommended to keep Cn.2 greater than 2200pF. Rn value
usually is a few ohms. Cn.1, Cn.2 and Rn values should be
determined through tuning the load transient response
waveforms on an actual board.
Rip and Cip form an R-C branch in parallel with Ri, providing a
lower impedance path than Ri at the beginning of io change. Rip
and Cip do not have any effect at steady state. Through proper
selection of Rip and Cip values, idroop can resemble io rather than
iL, and Vo will not ring back. The recommended value for Rip is
100Ω. Cip should be determined through tuning the load
transient response waveforms on an actual board. The
recommended range for Cip is 100pF~2000pF. However, it
should be noted that the Rip -Cip branch may distort the idroop
waveform. Instead of being triangular as the real inductor
23
FN8315.0
May 9, 2013
ISL95839
current, idroop may have sharp spikes, which may adversely
affect idroop average value detection and therefore may affect
OCP accuracy. User discretion is advised.
Resistor Current-Sensing Network
Phase1
Phase2
Phase3
L
L
L
DCR
DCR
DCR


R ntcnet

DCR
V Cn =  ------------------------------------------  -------------  I o
R sum
N 

 R ntcnet + -------------
N
(EQ. 27)
Substitution of Equation 27 into Equation 1 gives Equation 28:
R ntcnet
DCR
1
I droop = -----  ------------------------------------------  -------------  I o
N
R sum
Ri
R ntcnet + --------------N
(EQ. 28)
Therefore:
R ntcnet  DCR  I o
R i = ---------------------------------------------------------------------------------R sum
N   R ntcnet + ---------------  I droop

N 
Rsum
Rsum
ISUM+
Rsum
Rsen
Rsen
Rsen
Vcn
Ro
Cn
Ri
ISUM-
Ro
Ro
Io
FIGURE 23. RESISTOR CURRENT-SENSING NETWORK
Figure 23 shows the resistor current-sensing network for a
2-phase solution. Each inductor has a series current-sensing
resistor Rsen. Rsum and Ro are connected to the Rsen pads to
accurately capture the inductor current information. The Rsum
and Ro resistors are connected to capacitor Cn. Rsum and Cn
form a filter for noise attenuation. Equations 24 thru 26 give
VCn(s) expression:
R sen
V Cn  s  = -------------  I o  s   A Rsen  s 
N
1
A Rsen  s  = --------------------------s
1 + ---------------- Rsen
(EQ. 24)
(EQ. 25)
(EQ. 29)
Substitution of Equation 19 and application of the OCP condition
in Equation 29 gives Equation 30:
 R ntcs + R ntc   R p
----------------------------------------------------  DCR  I omax
R ntcs + R ntc + R p
R i = ----------------------------------------------------------------------------------------------------------------------------  R ntcs + R ntc   R p R sum
N   ---------------------------------------------------- + ---------------  I droopmax
N 
 R ntcs + R ntc + R p
(EQ. 30)
where Iomax is the full load current, Idroopmax is the
corresponding droop current. For example, given N = 3,
Rsum = 3.65kΩ, Rp = 11kΩ, Rntcs = 2.61kΩ, Rntc = 10kΩ,
DCR = 0.9mΩ, Iomax = 94A and Idroopmax = 50µA, Equation 30
gives Ri = 467Ω.
For resistor sensing, Equation 31 gives the DC relationship of
Vcn(s) and Io(s).
R sen
V Cn = -------------  I o
N
(EQ. 31)
Substitution of Equation 31 into Equation 1 gives Equation 32:
1 R sen
I droop = -----  -------------  I o
N
Ri
(EQ. 32)
Therefore:
1
 Rsen = ----------------------------R sum
---------------  C n
N
(EQ. 26)
Transfer function ARsen(s) always has unity gain at DC.
Current-sensing resistor Rsen value will not have significant
variation over-temperature, so there is no need for the NTC
network.
The recommended values are Rsum = 1kΩ and Cn = 5600pF.
Overcurrent Protection
Refer to Equation 1 on page 16 and Figures 17, 21 and 23;
resistor Ri sets the droop current Idroop. Tables 2 and 3 show the
internal OCP threshold. It is recommended to design Idroop
without using the RCOMP resistor.
For example, the OCP threshold is 60µA for 3-phase solution. We
will design Idroop to be 50µA at full load, so the OCP trip level is
1.2x of the full load current.
For inductor DCR sensing, Equation 27 gives the DC relationship
of Vcn(s) and Io(s).
24
R sen  I o
R i = --------------------------N  I droop
(EQ. 33)
Substitution of Equation 33 and application of the OCP condition
in Equation 29 gives Equation 34:
R sen  I omax
R i = -------------------------------------N  I droopmax
(EQ. 34)
where Iomax is the full load current, Idroopmax is the
corresponding droop current. For example, given N = 3,
Rsen = 1mΩ, Iomax = 94A and Idroopmax = 50µA, Equation 34
gives Ri = 627Ω.
Load Line Slope
Refer to Figure 10.
For inductor DCR sensing, substitution of Equation 28 into
Equation 2 gives the load line slope expression:
R droop
R ntcnet
V droop
DCR
LL = ------------------- = -------------------  ------------------------------------------  ------------Io
Ri
R sum
N
R ntcnet + --------------N
(EQ. 35)
FN8315.0
May 9, 2013
ISL95839
For resistor sensing, substitution of Equation 32 into Equation 2
gives the load line slope expression:
R sen  R droop
V droop
LL = ------------------- = --------------------------------------N  Ri
Io
(EQ. 36)
Substitution of Equation 29 and rewriting Equation 35, or
substitution of Equation 33 and rewriting Equation 36 give the
same result in Equation 37:
Io
R droop = ----------------  LL
I droop
T1(s) is the total loop gain of the voltage loop and the droop loop.
It always has a higher crossover frequency than T2(s) and has
more meaning of system stability.
T2(s) is the voltage loop gain with closed droop loop. It has more
meaning of output voltage response.
Design the compensator to get stable T1(s) and T2(s) with
sufficient phase margin, and output impedance equal or smaller
than the load line slope.
(EQ. 37)
L
One can use the full load condition to calculate Rdroop. For
example, given Iomax = 94A, Idroopmax = 50µA and LL = 1.9mΩ,
Equation 37 gives Rdroop = 3.57kΩ.
Q1
GATE Q2
DRIVER
Vin
It is recommended to start with the Rdroop value calculated by
Equation 37, and fine tune it on the actual board to get accurate
load line slope. One should record the output voltage readings at
no load and at full load for load line slope calculation. Reading
the output voltage at lighter load instead of full load will increase
the measurement error.
20W

EA
MOD.
COMP
VID
ISOLATION
TRANSFORMER
CHANNEL B
LOOP GAIN =
CHANNEL A
Figure 18 shows the desired load transient response waveforms.
Figure 24 shows the equivalent circuit of a voltage regulator (VR)
with the droop function. A VR is equivalent to a voltage source
(= VID) and output impedance Zout(s). If Zout(s) is equal to the
load line slope LL, i.e., constant output impedance, in the entire
frequency range, Vo will have square response when Io has a
square change.
i
io
Cout
LOAD LINE SLOPE
Compensator
Zout(s) = LL
Vo
CHANNEL A
CHANNEL B
NETWORK
ANALYZER EXCITATION OUTPUT
FIGURE 25. LOOP GAIN T1(s) MEASUREMENT SET-UP
o
L
VO
Q1
VID
VR
LOAD
V
o
VIN
GATE Q2
DRIVER
COUT
I
O
LOAD LINE SLOPE
20 
FIGURE 24. VOLTAGE REGULATOR EQUIVALENT CIRCUIT
Intersil provides a Microsoft Excel-based spreadsheet to help
design the compensator and the current sensing network, so the
VR achieves constant output impedance as a stable system.
Please go to http://www.intersil.com/en/support.html to request
spreadsheet.
A VR with active droop function is a dual-loop system consisting of
a voltage loop and a droop loop which is a current loop. However,
neither loop alone is sufficient to describe the entire system. The
spreadsheet shows two loop gain transfer functions, T1(s) and
T2(s), that describe the entire system. Figure 25 conceptually
shows T1(s) measurement set-up and Figure 26 conceptually
shows T2(s) measurement set-up. The VR senses the inductor
current, multiplies it by a gain of the load line slope, then adds it
on top of the sensed output voltage and feeds it to the
compensator. T(1) is measured after the summing node, and T2(s)
is measured in the voltage loop before the summing node. The
spreadsheet gives both T1(s) and T2(s) plots. However, only T2(s)
can be actually measured on an ISL95839 regulator.
25
EA
MOD.
COMP
CHANNEL B
LOOP GAIN =
CHANNEL A
VID
ISOLATION
TRANSFORMER
CHANNEL A
CHANNEL B
NETWORK
ANALYZER
EXCITATION OUTPUT
FIGURE 26. LOOP GAIN T2(s) MEASUREMENT SET-UP
FN8315.0
May 9, 2013
Compensation & Current Sensing Network Design for Intersil Multiphase R^3 Regulators.
26
Revision 9.1
Attention: 1. "Analysis ToolPak" Add-in is required. (To turn it on in MS Excel 2003, go to Tools--Add-Ins, and check "Analysis ToolPak").
2. Green cells require user input
Compensator Parameters
C3
Operation Parameters
Controller Part Number: IS
ISL95839
L95836
§
s · §
s ·
C2 R3
C1 R2
¸ ˜ ¨1 ¸
KZi ˜ Zi ˜ ¨¨1 Phase Number:
3
2Sf z1 ¸¹ ¨©
2Sf z 2 ¸¹
©
AV ( s )
Vin:
12 volts
§
· §
·
R1
s
s
FB
¸ ˜ ¨1 ¸
Vo:
1 volts
s ˜ ¨1 COMP
¨
2Sf p1 ¸¹ ¨©
2Sf p 2 ¸¹
OPAMP
©
Full Load Current:
94 Amps
Vref
Rcomp
Estimated Full-Load Efficiency:
85 %
Number of Output Bulk Capacitors:
4
Recommended Value
User-Selected Value
Capacitance of Each Output Bulk Capacitor:
470 uF
R1
3.572 k :
R1
3.57 k :
ESR of Each Output Bulk Capacitor:
4.5 m :
ESL of Each Output Bulk Capacitor:
0.2 nH
R2
270.237 k :
R2
267 k :
Number of Output Ceramic Capacitors:
28
R3
0.699 k :
R3
0.499 k :
Capacitance of Each Output Ceramic Capacitor:
10 uF
C1
497.168 pF
C1
150 pF
C2
505.690 pF
C2
470 pF
ESR of Each Output Ceramic Capacitor:
3 m:
ESL of Each Output Ceramic Capacitor:
3 nH
C3
31.478 pF
C3
47 pF
Switching Frequency:
300 kHz
Rcomp
274 k :
Y
Use User-Selected Value (Y/N)?
Inductance Per Phase:
0.36 uH
Disable Droop Function (Y/N)? N
CPU Socket Resistance:
0.9 m :
Performance and Stability
Desired Load-Line Slope:
1.9 m :
Desired Idroop Current at Full Load:
50 uA
T1 Bandwidth: 118kHz
T2 Bandwidth: 38kHz
(This sets the over-current protection level)
T1 Phase Margin: 74.1°
T2 Phase Margin: 85.9°
Current Sensing Network Parameters
Phase1
Phase2
Rsum
Rsum
L
L
DCR
DCR
7V
0DJQLWXGHPRKP
(
(
(
(
(
(
Ro
Do The Following
For Resistor
Operation Parameters
Sensing
<-- Rsense
Inductor DCR
0.9 m :
Rsum
3.65 k :
<-- 0.001k
Rntc
10 k :
<-- 1000k
Rntcs
2.61 k :
<-- 1000k
Rp
11 k :
<-- 1000k
Vo
These Rsum and Cn values are used to "fool" the spreadsheet
so it can calculate for resistor-sensing application
They should not be used on the actual schematics
COMP Pin Voltage During Reading of Rcomp Value
(Only On Controllers With COMP Pin Resistor Reader Function)
( ( ( ( ( ( ( (
Loop Gain, Phase Curve
7V
7V
3KDVHGHJUHH
3KDVHGHJUHH
Recommended Value Copy To User Selected Value
------->
Cn
0.397 uF
Cn
0.397 uF
Ri
467 :
Ri 467.239 :
)UHTXHQF\+]
Output Impedance Z(f), Phase Curve
Voltage Threshold
COMP Pin Voltage
(
(
(
(
)UHTXHQF\+]
(
(
(
7LPHPV
(
Output Impedance Z(f), Gain Curve
)UHTXHQF\+]
ISUM-
Ri
Ro
(
DCR
Ro
&2033LQ9ROWDJH9
*DLQG%
7V
Cn
RNTC
( ( ( ( ( ( ( (
)UHTXHQF\+]
Note: COMP pin voltage needs to reach or cross the
threshold voltage at "Time"=1ms.
The above COMP pin waveform
passes
FN8315.0
May 9, 2013
FIGURE 27. SCREENSHOT OF THE COMPENSATOR DESIGN SPREADSHEET
ISL95839
(
RNTCS
L
Rp
1.3
Loop Gain, Gain Curve
ISUM+
Rsum
Changing the settings in red requires deep understanding of control loop design
Place the 2nd compensator pole fp2 at:
1.5 xfs (Switching Frequency)
7XQH.ȦLWRJHWWKHGHVLUHGORRSJDLQEDQGZLGWK
Tune the compensator gain factor KȦi:
5HFRPPHQGHG.ȦLUDQJHLVa
Phase3
ISL95839
Programming Resistors
TABLE 8. RCOMPG PROGRAMMING TABLE
There are two programming resistors: RCOMP and RCOMPG.
Table 7 shows how to select RCOMP based on VBOOT and VR1
ICCMAX register settings. VR1 can power to 0V VBOOT or an
internally-set VBOOT based on RCOMP value. When the controller
works with an actual CPU, select RCOMP such that VR1 powers
up to VBOOT = 0V as required by the SVID command. In the
absence of a CPU, such as testing of the VR alone, select RCOMP
such that VR1 powers up to the internally-set VBOOT, which by
default is 1.1V. Determine the maximum current VR1 can
support and set the VR1 ICCMAX register value accordingly by
selecting the appropriate RCOMP value. The CPU will read the
VR1 ICCMAX register value and ensure that the CPU CORE current
doesn’t exceed the value specified by VR1 ICCMAX.
Table 8 shows how to select RCOMPG based on VR1 and VR2 CCM
switching frequency and VR2 ICCMAX register settings. There are
four switching frequencies to choose from: 300kHz, 350kHz,
400kHz, and 450kHz. There are also three VR2 ICCMAX values to
choose.
TABLE 7. RCOMP PROGRAMMING TABLE
RCOMP
(kΩ)
RCOMPG
(kΩ)
MIN
TYP
MAX
SWITCHING
FREQUENCY (kHz)
VR2 ICCMAX (A)
12.0
13.2
14.4
450
33
15.8
17.0
18.2
450
24
19.6
20.8
22.0
450
18
23.4
24.6
25.8
400
18
27.2
28.4
29.6
400
24
31.2
33.7
36.1
400
33
86.2
88.9
91.6
350
33
97.3
100.3
103.3
350
24
108.3
111.7
115.1
350
18
119.5
123.2
126.8
300
18
132.5
136.6
140.6
300
24
147.2
151.8
156.3
300
33
Current Balancing
MIN
TYP
MAX
VBOOT (V)
VR1 ICCMAX (A)
2.7
2.85
3.0
0
99
5.0
5.6
6.2
0
94
8.4
9.4
10.4
0
80
12.0
13.2
14.4
0
70
15.8
17.0
18.2
0
60
19.6
20.8
22.0
0
53
23.4
24.6
25.8
0
48
27.2
28.4
29.6
0
43
31.2
33.7
36.1
0
38
38.8
41.3
43.7
0
33
46.4
48.9
51.3
0
24
54.0
56.5
58.9
0
18
62.1
64.1
66.0
1.1
18
69.5
71.7
73.8
1.1
24
76.9
79.3
81.7
1.1
33
86.2
88.9
91.6
1.1
38
97.3
100.3
103.3
1.1
43
108.3
111.7
115.1
1.1
48
119.5
123.2
126.8
1.1
53
132.5
136.6
140.6
1.1
60
147.2
151.8
156.3
1.1
70
162.0
167.0
172.0
1.1
80
178.7
184.2
189.7
1.1
94
210.1
216.6
open
1.1
99
27
Refer to Figures 3 and 4. The controller achieves current
balancing through matching the ISEN pin voltages. Risen and
Cisen form filters to remove the switching ripple of the phase
node voltages. It is recommended to use rather long RisenCisen
time constant such that the ISEN voltages have minimal ripple
and represent the DC current flowing through the inductors.
Recommended values are Rs = 10kΩ and Cs = 0.22µF.
FN8315.0
May 9, 2013
ISL95839
Slew Rate Compensation Circuit for VID
Transition
Rdroop
Vcore
Rvid Cvid
OPTIONAL
FB
Ivid
Idroop_vid
COMP
E/A
 VDACDAC
VIDs
RTN
X1
INTERNAL TO
IC
VID
VSSSENSE
VSS
During a large VID transition, the DAC steps through the VIDs at a
controlled slew rate. For example, the DAC may change a tick
(5mV) per 0.5µs, controlling output voltage Vcore slew rate at
10mV/µs.
Figure 28 shows the waveforms of VID transition. During VID
transition, the output capacitor is being charged and discharged,
causing Cout x dVcore/dt current on the inductor. The controller
senses the inductor current increase during the up transition, as
the Idroop_vid waveform shows, and will droop the output voltage
Vcore accordingly, making Vcore slew rate slow. Similar behavior
occurs during the down transition. To get the correct Vcore slew
rate during VID transition, one can add the Rvid-Cvid branch,
whose current Ivid cancels Idroop_vid.
It’s recommended to choose the R, C values from the reference
design as a starting point. then tweak the actual values on the
board to get the best performance.
During normal transient response, the FB pin voltage is held
constant, therefore is virtual ground in small signal sense. The Rvid
- Cvid network is between the virtual ground and the real ground,
and hence has no effect on transient response.
VID
Vfb
Ivid
Vcore
Idroop_vid
FIGURE 28. SLEW RATE COMPENSATION CIRCUIT FOR VID
TRANSITION
28
FN8315.0
May 9, 2013
IN
R18
10UF
10UF
22UF
22UF
C127
22UF
22UF
C129
22UF
C125
C124
22UF
22UF
22UF
C123
C122
C117
470UF
22UF
C118
C120
22UF
---------------------------------
C119
C121
C113
22UF
470UF
C114
22UF
10
VSUMNG R131
3.65K
VSUMPG R127
PLACE NEAR L1
10
FN8315.0
May 9, 2013
FIGURE 29. ISL95839 1+1 REFERENCE DESIGN
10UF
C33
10UF
---------------------------------
22UF
22UF
C67
22UF
C63
22UF
22UF
C59
22UF
C302
470UF
470UF
470UF
C301
C53
22UF
22UF
C54
22UF
10UF
22UF
C315
C52
C39
470UF
C40
22UF
C41
22UF
VSUMN
C47
R88
3.65K
10
C68
C64
C60
C48
10UF
10UF
C319
10UF
C318
10UF
C317
C316
10UF
10UF
C314
C313
3300PF 649
IN
VSUMN
10UF
R109
C312
383
C81
10UF
R38
R30
C311
C13
CPUVSSSENSE
0.01UF
----
DNP
----
10UF
IN
OPTIONAL
C310
CPUVCCSENSE
10
C20
R17
IN
1UF
1UF
C22
C16
BOOT1
PGOOD
IN
0.1UF
11K
----------> R42 R41
CPUVCORE
VSUMP
C130
680PF
C19
2K
0.22UF
R155
IN
OUT
VSUMP R63
R11
1000PF 133K
PGOOD
C18
R7
1.91K +3.3V
OUT
C3
2200PF
2.1K
CPUVCORE
OUT
Q3
OUT
71.5K
C11
118
Q2
0.36UH
0.22UF
C30
0
R19
R10
56PF
+5V
L1
R56
+5V
DNP
C6
R4
IN
10K 2.61K
NTC
IN
COMP
EP
FB
470K NTC
ISUMN
UGATE1
RTN
3.83K
PHASE1
NTC
ISUMP
R46
FB2
ISEN1
27.4K
R49
1
PWM3
LGATE1
VR_HOT#
R80
IN
R37
VDD
ISL95839HRTZ
SDA
OUT
+5V
VCCP
------------------------------------------------------------------COMPONENT
PART NUMBER (MANUFACTURER)
------------------------------------------------------------------EEFLX0D471R4(PANASONIC)
- C39,C52,C301,C302,C113,C117
2TPW470M4R(SANYO)
T520V277M2R5A(1_E4R5-6666(KEMET)
------------------------------------------------------------------GRM21BR61C226KE15L(TDK)
- C40,C41,C47,C48,C53,C54
C59-C68,C114,C115,C118-C127
(KYOCERA,MURATA,TAIYO,SAMSUNG)
------------------------------------------------------------------- C310-C319
GRM21BR61C106KE15L(TDK)
(KYOCERA,MURATA,TAIYO,SAMSUNG)
------------------------------------------------------------------25SP56M(SANYO)
- C24,C25
------------------------------------------------------------------- L1,L4
MPCH1040LR36(NEC-TOKIN)
ETQP4LR36AFC(PANASONIC)
------------------------------------------------------------------BSC052N03LS-T(INFINEON)
- Q2,Q16
------------------------------------------------------------------BSC011N03LS-T(INFINEON)
- Q3,Q17
------------------------------------------------------------------ERT-J1VR103J-T(PANASONIC)
- R42,R43
------------------------------------------------------------------- R20,R45
NCP18WM474J03RB-T(MURATA)
-------------------------------------------------------------------
C27
C24
LGATE2
U1
---------------------------------
BOOT1G
PHASE1G
UGATE1G
VR_ON
LGATE1G
FBG
PHASE2
ALERT#
R4 = 71.5K
VBOOT = 1.1V
ICCMAX = 24A
COMPG
VR_ON
----
R8
130
54.9
---R5
499
75
---R12
130
R214
R213
BOOT2
UGATE2
SCLK
43
VIN
IN
IMON
NTCG
-------CONTROLLER
SIDE PULL-UP
R202
VR_HOT#
0.22UF
IMONG
ISEN2
IN
C30
0
ISUMPG
IMON
ISEN3
SDA
R1 97.6K
-----
IN
--------
----C12
ALERT#
-------CPU
SIDE PULL-UP
97.6K
0.01UF
330PF
IN
C14
R56
ISL95839
--------
C87
1UF
SCLK
3.83K
IN
----
VTT
NTC
R26
PGOODG
R20
470K
0.01UF
C8
R54
27.4K
RTNG
R112
ISUMNG
IMONG
10K
NTC
+3.3V
IN
C25
1.91K
C115
PGGODG
OUT
R183
OUT
3300PF 649
10
VSUMNG
IN
PLACE NEAR L4
56UF
R32
C112
R39
383
C93
GTVCORE
OUT
Q17
56UF
R9
1000PF 133K
2.61K
R36
11K
C94
R31
L4
0.36UH
---->
C51
R25
2.1K
R43
56PF
C97
2200PF
Q16
OUT
29
R23
C86
C88
VSUMPG
IN
0.1UF
IN
118
0.01UF
GTVSSSENSE
C90
----
28.7K
DNP
R24
R2
C95
IN
2K
0.22UF
GTVCCSENSE
680P
-----
----C89
----
10
R55
C99
OPTIONAL
R16
IN
330PF
GTVCORE
C110
R2 = 28.7K
FSW = 400KHZ
ICCMAX_GT = 24A
ISL95839
Layout Guidelines
ISL95839
PIN #
SYMBOL
LAYOUT GUIDELINES
BOTTOM PAD
GND
Connect this ground pad to the ground plane through low impedance path. Recommend use of at least 5 vias to connect
to ground planes in PCB internal layers.
2
IMONG
3
IMON
Connect a resistor in parallel with a capacitor from IMON and IMONG pins to ground respectively. Place the resistors and
capacitors as close as possible to the controller.
4
NTCG
5, 6, 7
8
The NTC thermistor needs to be placed close to the thermal source that is monitored to determine AXG Vcore thermal
throttling. Recommend placing it at the hottest spot of the AXG Vcore VR.
SCLK,
Follow Intel recommendation.
ALERT#, SDA
VR_HOT#
No special consideration.
9
FB2
Place the compensator components in general proximity of the controller.
10
NTC
The NTC thermistor needs to be placed close to the thermal source that is monitored to determine CPU Vcore thermal
throttling. Recommend placing it at the hottest spot of the CPU Vcore VR.
11
ISEN3
12
ISEN2
13
ISEN1
Each ISEN pin has a capacitor (Cisen) decoupling it to VSUMN, then through another capacitor (Cvsumn) to GND. Place Cisen
capacitors as close as possible to the controller and keep the following loops small:
1. Any ISEN pin to another ISEN pin
2. Any ISEN pin to GND
The red traces in the following drawing show the loops that need to minimized.
Phase1
L3
Ro
Risen
ISEN3
Cisen
Phase2
Vo
L2
Ro
Risen
ISEN2
Cisen
Phase3
Risen
ISEN1
GND
14
ISUMP
15
ISUMN
L1
Ro
Vsumn
Cisen
Cvsumn
Place the current sensing circuit in general proximity of the controller.
Place capacitor Cn very close to the controller.
Place the NTC thermistor next to VR1 phase-1 inductor (L1) so it senses the inductor temperature correctly.
Each phase of the power stage sends a pair of VSUMP and VSUMN signals to the controller. Run these two signals traces in
parallel fashion with decent width (>20mil).
IMPORTANT: Sense the inductor current by routing the sensing circuit to the inductor pads. Route R63 and R71 to VR1
phase-1 side pad of inductor L1. Route R88 to the output side pad of inductor L1. Route R65 and R72 to VR1 phase-2 side
pad of inductor L2. Route R90 to the output side pad of inductor L2. If possible, route the traces on a different layer from
the inductor pad layer and use vias to connect the traces to the center of the pads. If no via is allowed on the pad, consider
routing the traces into the pads from the inside of the inductor. The following drawings show the two preferred ways of
routing current sensing traces.
INDUCTOR
INDUCTOR
VIAS
CURRENT-SENSING TRACES
30
CURRENT-SENSING TRACES
FN8315.0
May 9, 2013
ISL95839
Layout Guidelines (Continued)
ISL95839
PIN #
SYMBOL
16
RTN
Place the RTN filter in close proximity of the controller for good decoupling.
17
FB
Place the compensator components in general proximity of the controller.
LAYOUT GUIDELINES
18
COMP
19
PGOOD
No special consideration.
20
BOOT1
Use decent wide trace (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close.
21
UGATE1
22
PHASE1
Run these two traces in parallel fashion with decent width (>30mil). Avoid any sensitive analog signal trace from crossing
over or getting close. Recommend routing PHASE1 trace to VR1 phase-1 high-side MOSFET (Q2 and Q8) source pins instead
of general copper.
23
LGATE1
Place the RTNG filter in close proximity of the controller for good decoupling.
24
PWM3
No special consideration.
25
VDD
A capacitor decouples it to GND. Place it in close proximity of the controller.
26
VCCP
A capacitor decouples it to GND. Place it in close proximity of the controller.
27
LGATE2
Use decent width (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close.
28
PHASE2
29
UGATE2
Run these two traces in parallel fashion with decent width (>30mil). Avoid any sensitive analog signal trace from crossing
over or getting close. Recommend routing PHASE2 trace to VR1 phase-2 high-side MOSFET (Q4 and Q10) source pins
instead of general copper.
30
BOOT2
Use decent wide trace (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close.
31
BOOT1G
Use decent wide trace (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close.
32
UGATE1G
33
PHASE1G
Run these two traces in parallel fashion with decent width (>30mil). Avoid any sensitive analog signal trace from crossing
over or getting close. Recommend routing PHASE1G trace to VR2 phase-1 high-side MOSFET source pins instead of general
copper
34
LGATE1G
Use decent width (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close.
35
VR_ON
No special consideration.
36
PGOODG
No special consideration.
37
COMPG
Place the compensator components in general proximity of the controller.
38
FBG
39
RTNG
40
ISUMNG
1
ISUMPG
Place the RTNG filter in close proximity of the controller for good decoupling.
Place the current sensing circuit in general proximity of the controller.
Place capacitor Cn very close to the controller.
Place the NTC thermistor next to VR2 phase-1 inductor (L1) so it senses the inductor temperature correctly.
See ISUMN and ISUMP pins for layout guidelines of current-sensing trace routing.
31
FN8315.0
May 9, 2013
ISL95839
Typical Performance
FIGURE 30. VR1 SOFT-START, VIN = 19V, IO = 5A, VID = 1.1V,
CH1: VR_ON, CH2: VR1 VO, CH3: PGOOD
FIGURE 31. VR2 SOFT-START, VIN = 19V, IO = 5A, VID = 1.1V,
CH1: VR_ON, CH2: VR2 VO, CH3: PGOODG
FIGURE 32. 1 VR1 AND VR2 SOFT-START, VIN = 7V, Io_VR1 = 30A,
Io_VR2 = 30A, VID = 1.1V, CH1: VR1 VO, CH2: VR2 VO,
CH3: PGOOD, CH4: PHASE1G
FIGURE 33. 1 VR1 AND VR2 SOFT-START, VIN = 20V, IO_VR1 = 30A,
IO_VR2 = 30A, VID = 1.1V, CH1: VR1 VO, CH2: VR2 VO,
CH3: PGOOD, CH4: PHASE1G
FIGURE 34. VR1 SHUT DOWN, VIN = 12V, IO = 5A, VID = 1.1V,
CH1: PGOOD, CH2: VR1 VO, CH3: VR_ON, CH4: COMP
FIGURE 35. VR2 SHUT DOWN, VIN = 12V, IO = 5A, VID = 1.1V,
CH1: PGOODG, CH2: VR2 VO, CH3: VR_ON,
CH4: COMPG
32
FN8315.0
May 9, 2013
ISL95839
Typical Performance (Continued)
FIGURE 36. VR1 PRE-CHARGED START UP, VIN = 19V, VID = 1.1V,
V_PRE-CHARGE VOLTAGE = 0.5V, CH1: PHASE1,
CH2: VR1 VO, CH3: VR_ON, CH4: PGOOD
FIGURE 37. VR2 PRE-CHARGED START UP, VIN = 19V, VID = 1.1V,
V_PRE-CHARGE VOLTAGE = 1.3V, CH1: PHASE1G,
CH2: VR2 VO, CH3: VR_ON, CH4: PGOODG
FIGURE 38. VR1 STEADY STATE, VIN = 19V, IO = 94A, VID = 0.9V
CH1: PHASE1, CH2: VR1 VO, CH3: PHASE2,
CH4: PHASE3
FIGURE 39. VR1 LOAD RELEASE RESPONSE, VIN = 12V, VID = 0.9V,
IO = 28A/94A, SLEW TIME= 150ns, LL = 1.9mΩ,
CH1: PHASE1, CH2: VR1 VO, CH3: PHASE2,
CH4: PHASE3
FIGURE 40. VR1 LOAD INSERTION RESPONSE, VIN = 12V, VID = 0.9V, IO = 28A/94A, SLEW TIME= 150ns, LL = 1.9mΩ, CH1: PHASE1,
CH2: VR1 VO, CH3: PHASE2, CH4: PHASE
33
FN8315.0
May 9, 2013
ISL95839
Typical Performance (Continued)
FIGURE 41. VR1 PS2 LOAD TRANSIENT RESPONSE, VIN = 19V,
VID = 0.6V, IO = 1A/5A, SLEW TIME= 150ns,
LL = 1.9mΩ,CH1: PHASE1, CH2: VR1 VO
FIGURE 42. VR2 PS2 LOAD TRANSIENT RESPONSE, VIN = 19V,
VID = 0.6V, IO = 1A/5A, SLEW TIME= 150ns,
LL = 3.9mΩ,CH1: PHASE1G, CH2: VR2 VO
FIGURE 43. VR1 SETVID-FAST RESPONSE, IO = 5A,
VID = 0.3V - 0.9V, CH1: PHASE1, CH2: VR1 VO,
CH3: SDA, CH4: ALERT#
FIGURE 44. VR2 SETVID-FAST RESPONSE, IO = 5A,
VID = 0.5V - 0.8V, CH1: PHASE1G, CH2: VR2 VO,
CH3: SDA, CH4: ALERT#
FIGURE 45. VR1 SETVID-SLOW RESPONSE, IO = 5A,
VID = 0.3V - 0.9V, CH1: PHASE1, CH2: VR1 VO,
CH3: SDA, CH4: ALERT#
FIGURE 46. VR2 SETVID-SLOW RESPONSE, IO = 5A,
VID = 0.4V - 0.9V, CH1: PHASE1G, CH2: VR2 VO,
CH3: SDA, CH4: ALERT#
34
FN8315.0
May 9, 2013
ISL95839
Typical Performance (Continued)
FIGURE 47. VR1 SETVID DECAY PRE_EMPTIVE BEHAVIOR, SETVID-FAST 0.8V AFTER SETVID DECAY 0V FROM 0.9V, IO = 4A, CH1: PHASE1,
CH2: VR1 VO, CH3: SDA, CH4: PHASE2
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
DATE
REVISION
May 9, 2013
FN8315.0
CHANGE
Initial Release.
About Intersil
Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management
semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal
computing and high-end consumer markets. For more information about Intersil, visit our website at www.intersil.com.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting
www.intersil.com/en/support/ask-an-expert.html. Reliability reports are also available from our website at
http://www.intersil.com/en/support/qualandreliability.html#reliability
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
35
FN8315.0
May 9, 2013
ISL95839
Package Outline Drawing
L40.5x5
40 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 9/10
5.00
4X 3.60
A
B
36X 0.40
6
PIN #1 INDEX AREA
(4X)
3.50
5.00
6
PIN 1
INDEX AREA
0.15
40X 0.4± 0 .1
BOTTOM VIEW
TOP VIEW
0.20
b
4
0.10 M C A B
PACKAGE OUTLINE
0.40
0.750
SEE DETAIL “X”
SIDE VIEW
3.50
5.00
0.050
// 0.10 C
C
BASE PLANE
SEATING PLANE
0.08 C
(36X 0.40
0.2 REF
(40X 0.20)
C
(40X 0.60)
5
0.00 MIN
0.05 MAX
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.27mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
7.
JEDEC reference drawing: MO-220WHHE-1
either a mold or mark feature.
36
FN8315.0
May 9, 2013
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