DATASHEET

ISL6268
®
Data Sheet
August 22, 2006
High-Performance Notebook PWM
Controller
Features
• High performance R3 technology
The ISL6268 IC is a Single-Phase Synchronous-Buck PWM
controller featuring Intersil's Robust Ripple Regulator (R3)
technology that delivers truly superior dynamic response to
input voltage and output load transients. Integrated
MOSFET drivers and bootstrap diode result in fewer
components and smaller implementation area.
Intersil’s R3 technology combines the best features of
fixed-frequency PWM and hysteretic PWM while eliminating
many of their shortcomings. R3 technology employs an
innovative modulator that synthesizes an AC ripple voltage
signal VR, analogous to the output inductor ripple current. The
AC signal VR enters a window comparator where the lower
threshold is the error amplifier output VCOMP, and the upper
threshold is a programmable voltage reference VW, resulting
in generation of the PWM signal. The voltage reference VW
sets the steady-state PWM frequency. Both edges of the
PWM can be modulated in response to input voltage
transients and output load transients, much faster than
conventional fixed-frequency PWM controllers. Unlike a
conventional hysteretic converter, the ISL6268 has an error
amplifier that provides ±1% voltage regulation at the FB pin.
The ISL6268 has a 1.5ms digital soft-start and can be
started into a pre-biased output voltage. A resistor divider is
used to program the output voltage setpoint. The ISL6268
normally operates in continuous-conduction-mode (CCM),
automatically entering diode-emulation-mode (DEM) at low
load for optimum efficiency. In CCM the converter operates
as a synchronous rectifier. In DEM the low-side MOSFET
stays off, blocking negative current flow from the output
inductor.
Pinout
FN6348.0
• Fast transient response
• ±1% regulation accuracy: -10°C to +100°C
• Wide input voltage range: +7.0V to +25.0V
• Output voltage range: +0.6V to +3.3V
• Wide output load range: 0A to 25A
• Diode emulation mode for increased light load efficiency
• Programmable PWM frequency: 200kHz to 600kHz
• Pre-biased output start-up capability
• Integrated MOSFET drivers and bootstrap diode
• Internal digital soft-start
• Power good monitor
• Fault protection
- Undervoltage protection
- Soft crowbar overvoltage protection
- Low-side MOSFET r DS(on) overcurrent protection
- Over-temperature protection
- Fault identification by PGOOD pull-down resistance
• Pb-free plus anneal available (RoHS compliant)
Applications
• PCI express graphical processing unit
• Auxiliary power rail
• VRM
• Network adapter
Ordering Information
ISL6268 (16 LD SSOP)
TOP VIEW
PHASE 1
16 UG
PGOOD 2
15 BOOT
VIN 3
14 PVCC
13 LG
VCC 4
EN 5
12 PGND
11 ISEN
COMP 6
10 VO
FB 7
9 FSET
GND 8
1
PART
NUMBER
ISL6268CAZ
(Note)
PART
MARKING TEMP (°C)
6268CAZ
ISL6268CAZ-T 6268CAZ
(Note)
PACKAGE
PKG.
DWG. #
-10 to +100 16 Ld QSOP M16.15A
(Pb-free)
16 Ld QSOP Tape and
Reel (Pb-free)
M16.15A
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Block Diagram
VIN
VO
GND
PWM FREQUENCY
CONTROL
+
VREF
VW
−
2
+
−
gmVIN
EN
−
FSET
−
VCC
+
R
PWM
Q
OVP
+
gmVO
−
−
UVP
CR
VCOMP
+
S
+
BOOT
+
EA
DRIVER
−
POR
DIGITAL SOFT-START
PWM CONTROL
FB
COMP
−
ISEN
OCP
+
IOC
30Ω
90Ω
UG
60Ω
PHASE
SHOOT THROUGH
PROTECTION
PVCC
DRIVER
LG
150°OT
PGND
PGOOD
FN6348.0
August 22, 2006
FIGURE 1. SCHEMATIC BLOCK DIAGRAM
ISL6268
+
−
VR
−
+
ISL6268
Typical Application
ISL6268
VIN
7V-25V
PGOOD
VIN
CIN
RPGOOD
QHIGH_SIDE
5V
PVCC
UG
RVCC
VCC
BOOT
CVCC
CPVCC
CBOOT
GND
VOUT
LOUT
0.6V-3.3V
PHASE
COUT
RSEN
ISEN
QLOW_SIDE
EN
LG
RCOMP
COMP
PGND
CCOMP1
FB
VO
CCOMP2
FSET
RFSET
RBOTTOM
3
CFSET
RTOP
FN6348.0
August 22, 2006
ISL6268
Absolute Voltage Ratings
Thermal Information
ISEN, VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +28V
VCC, PGOOD to GND . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V
PVCC to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V
GND to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to GND, VCC +3.3V
VO, FB, COMP, FSET . . . . . . . . . . . . . . . -0.3V to GND, VCC +0.3V
PHASE to GND (DC) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +28V
(<100ns Pulse Width, 10µJ) . . . . . . . . . . . . . . . . . . . . . . . . . -5.0V
BOOT to GND, or PGND . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V
BOOT to PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
UG (DC) . . . . . . . . . . . . . . . . . . . . . . .-0.3V to PHASE, BOOT +0.3V
(<200ns Pulse Width, 20µJ) . . . . . . . . . . . . . . . . . . . . . . . . -4.0V
LG (DC) . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to PGND, PVCC +0.3V
(<100ns Pulse Width, 4µJ) . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V
Thermal Resistance (Typical, Note 1)
θJA (°C/W)
QSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
105
Junction Temperature Range. . . . . . . . . . . . . . . . . .-55°C to +150°C
Operating Temperature Range . . . . . . . . . . . . . . . .-10°C to +100°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300°C
Recommended Operating Conditions
Ambient Temperature Range. . . . . . . . . . . . . . . . . .-10°C to +100°C
Supply Voltage (VIN to GND) . . . . . . . . . . . . . . . . . . . . . . 7V to 25V
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V ±5%
PVCC to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V ±5%
CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational section of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
These specifications apply for TA = -10°C to +100°C, unless otherwise stated.
All typical specifications TA = +25°C, VCC = 5V, PVCC = 5V
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
EN = 5V, VIN = 7V
-
6.5
10
µA
EN = 5V, VIN = 25V
-
26
35
µA
-
0.1
1.0
µA
-
1.7
2.5
mA
VIN
IVIN
VIN Input Bias Current
IVIN_SHDN EN = GND, VIN = 25V
VIN Shutdown Current
VCC and PVCC
VCC Input Bias Current
IVCC
EN = 5V, FB = 0.65V, VIN = 7V to 25V
VCC Shutdown Current
IVCC_SHDN EN = GND, VCC = 5V
-
0.1
1.0
µA
PVCC Shutdown Current
IPVCC_SHDN EN = GND, PVCC = 5V
-
0.1
1.0
µA
VCC POR THRESHOLD
Rising VCC POR Threshold Voltage
VVCC_THR
4.35
4.45
4.55
V
Falling VCC POR Threshold Voltage
V
4.10
4.20
4.30
V
VCC_THF
REGULATION
Reference Voltage
VREF
Regulation Accuracy
FB connected to COMP
-
0.6
-
V
-1
-
+1
%
200
-
600
kHz
PWM
Frequency Range
FSW
-12
-
+12
%
0.60
-
3.30
V
VO = 0.60V
-
1.3
-
µA
VO = 3.30V
-
7.0
-
µA
FB = 0.60V
-0.5
-
+0.5
µA
FSW = 300kHz
Frequency-Set Accuracy
VO Range
VVO
IVO
VO Input Leakage
ERROR AMPLIFIER
FB Input Bias Current
IFB
COMP Source Current
ICOMP_SRC FB = 0.40V, COMP = 3.20V
-
2.5
-
mA
COMP Sink Current
ICOMP_SNK FB = 0.80V, COMP = 0.30V
-
0.3
-
mA
COMP High Clamp Voltage
VCOMP_HC FB = 0.40V, Sink 50µA
3.10
3.40
3.65
V
COMP Low Clamp Voltage
VCOMP_LC FB = 0.80V, Source 50µA
0.09
0.15
0.21
V
4
FN6348.0
August 22, 2006
ISL6268
Electrical Specifications
These specifications apply for TA = -10°C to +100°C, unless otherwise stated.
All typical specifications TA = +25°C, VCC = 5V, PVCC = 5V (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER GOOD
PGOOD Pull-Down Impedance
PGOOD Leakage Current
RPG_SS
PGOOD = 5mA Sink
75
95
125
Ω
RPG_UV
PGOOD = 5mA Sink
75
95
125
Ω
RPG_OV
PGOOD = 5mA Sink
50
63
85
Ω
RPG_OC
PGOOD = 5mA Sink
25
32
45
Ω
IPGOOD
PGOOD = 5V
-
0.1
1.0
µA
-
5.0
-
mA
2.20
2.75
3.30
ms
PGOOD Maximum Sink Current (Note 2)
PGOOD Soft-Start Delay
TSS
EN High to PGOOD High
GATE DRIVER
UG Pull-Up Resistance
RUGPU
200mA Source Current
-
1.0
1.5
Ω
UG Source Current (Note 2)
IUGSRC
UG - PHASE = 2.5V
-
2.0
-
A
UG Sink Resistance
RUGPD
250mA Sink Current
-
1.0
1.5
Ω
UG Sink Current (Note 2)
IUGSNK
UG - PHASE = 2.5V
-
2.0
-
A
LG Pull-Up Resistance
RLGPU
250mA Source Current
-
1.0
1.5
Ω
LG Source Current (Note 2)
ILGSRC
LG - PGND = 2.5V
-
2.0
-
A
LG Sink Resistance
RLGPD
250mA Sink Current
-
0.5
0.9
Ω
LG Sink Current (Note 2)
ILGSNK
LG - PGND = 2.5V
-
4.0
-
A
UG to LG Deadtime
tUGFLGR
UG falling to LG rising, no load
-
21
-
ns
LG to UG Deadtime
tLGFUGR
LG falling to UG rising, no load
-
14
-
ns
BOOTSTRAP DIODE
Forward Voltage
VF
PVCC = 5V, IF = 2mA
-
0.58
-
V
Reverse Leakage
IR
VR = 25V
-
0.2
-
µA
CONTROL INPUTS
EN High Threshold
VENTHR
2.0
-
-
V
EN Low Threshold
VENTHF
-
-
1.0
V
IENL
EN = 0V
-
0.1
1.0
µA
IENH
EN = 5.0V
-
0.1
1.0
µA
IOC
ISEN sourcing
19
26
33
µA
ISEN Short-Circuit Threshold
ISC
ISEN sourcing
-
50
-
µA
UVP Threshold
VUV
81
84
87
%
OVP Rising Threshold
VOVR
113
116
119
%
OVP Falling Threshold
VOVF
100
103
106
%
TOTR
-
150
-
°C
TOTHYS
-
25
-
°C
EN Leakage
PROTECTION
ISEN OCP Threshold
OTP Rising Threshold (Note 2)
OTP Hysteresis (Note 2)
NOTE:
2. Guaranteed by characterization.
5
FN6348.0
August 22, 2006
ISL6268
Functional Pin Descriptions
PHASE (Pin 1)
The PHASE pin detects the voltage polarity of the PHASE
node and is also the current return path for the UG high-side
MOSFET gate driver. Connect the PHASE pin to the node
consisting of the high-side MOSFET source, the low-side
MOSFET drain, and the output inductor.
PGOOD (Pin 2)
The PGOOD pin is an open-drain output that indicates when
the converter is able to supply regulated voltage. Connect
the PGOOD pin to +5V through a pull-up resistor.
VIN (Pin 3)
The VIN pin measures the converter input voltage which is a
required input to the R3 PWM modulator. Connect across
the drain of the high-side MOSFET to the GND pin.
VCC (Pin 4)
The VCC pin is the input bias voltage for the IC. Connect
+5V from the VCC pin to the GND pin. Decouple with at least
1µF of a MLCC capacitor from the VCC pin to the GND pin.
EN (Pin 5)
The EN pin is the on/off switch of the IC. The soft-start
sequence begins when the EN pin is pulled above the rising
threshold voltage VENTHR and VCC is above the power-on
reset (POR) rising threshold voltage VVCC_THR . When the
EN pin is pulled below the falling threshold voltage VENTHF,
PWM immediately stops.
VO (Pin 10)
The VO pin measures the converter output voltage and is
used exclusively as an input to the R3 PWM modulator.
Connect at the physical location where the best output
voltage regulation is desired.
ISEN (Pin 11)
The ISEN pin programs the threshold of the OCP
overcurrent fault protection. Program the desired OCP
threshold with a resistor connected across the ISEN and
PHASE pins. The OCP threshold is programmed to detect
the peak current of the output inductor. The peak current is
the sum of the DC and AC components of the inductor
current.
PGND (Pin 12)
The PGND pin conducts the turn-off transient current
through the LG gate driver. The PGND pin must be
connected to complete the pull-down circuit of the LG gate
driver. The PGND pin should be connected to the source of
the low-side MOSFET through a low impedance path,
preferably in parallel with the trace connecting the LG pin to
the gate of the low-side MOSFET. The adaptive
shoot-through protection circuit measures the low-side
MOSFET gate-source voltage from the LG pin to the PGND
pin.
LG (Pin 13)
The LG pin is the output of the low-side MOSFET gate
driver. Connect to the gate of the low-side MOSFET.
PVCC (Pin 14)
COMP (Pin 6)
The COMP pin is the output of the control-loop error
amplifier. Compensation components for the control-loop
connect across the COMP and FB pins.
The PVCC pin is the input voltage bias for the LG low-side
MOSFET gate driver. Connect +5V from the PVCC pin to the
PGND pin. Decouple with at least 1µF of an MLCC capacitor
across the PVCC and PGND pins.
FB (Pin 7)
BOOT (Pin 15)
The FB pin is the inverting input of the control-loop error
amplifier. The converter output voltage regulates to 600mV
from the FB pin to the GND pin. Program the desired output
voltage with a resistor network connected across the VO,
FB, and GND pins. Select the resistor values such that FB to
GND is 600mV when the converter output voltage is at the
programmed regulation value.
The BOOT pin stores the input voltage for the UG high-side
MOSFET gate driver. Connect an MLCC capacitor across
the BOOT and PHASE pins. The boot capacitor is charged
through an internal boot diode connected from the PVCC pin
to the BOOT pin, each time the PHASE pin drops below
PVCC minus the voltage dropped across the internal boot
diode.
GND (Pin 8)
UG (Pin 16)
Signal common of the IC. Unless otherwise stated, signals
are referenced to the GND pin, not the PGND pin.
The UG pin is the output of the high-side MOSFET gate
driver. Connect to the gate of the high-side MOSFET.
FSET (Pin 9)
The FSET pin programs the PWM switching frequency.
Program the desired PWM frequency with a resistor and a
capacitor connected across the FSET and GND pins.
6
FN6348.0
August 22, 2006
ISL6268
Theory of Operation
Power-On Reset
Modulator
The ISL6268 is a hybrid of fixed frequency PWM control, and
variable frequency hysteretic control. Intersil’s R3 technology
can simultaneously affect the PWM switching frequency and
PWM duty cycle in response to input voltage and output load
transients. The term “Ripple” in the name “Robust Ripple
Regulator” refers to the converter output inductor ripple
current, not the converter output ripple voltage. The R3
modulator synthesizes an AC signal VR, which is an ideal
representation of the output inductor ripple current. The
duty-cycle of VR is the result of charge and discharge
current through a ripple capacitor CR. The current through
CR is provided by a transconductance amplifier gm that
measures the VIN and VO pin voltages. The positive slope
of VR can be written as:
V RPOS = ( g m ) • ( V IN – V OUT )
(EQ. 1)
The ISL6268 is disabled until the voltage at the VCC pin has
increased above the rising power-on reset (POR) VCCR
threshold voltage. The controller will become once again
disabled when the voltage at the VCC pin decreases below
the falling POR VCCF threshold voltage.
EN, Soft-Start, and PGOOD
The ISL6268 uses a digital soft-start circuit to ramp the
output voltage of the converter to the programmed regulation
setpoint at a predictable slew rate. The slew rate of the
soft-start sequence has been selected to limit the inrush
current through the output capacitors as they charge to the
desired regulation voltage. When the EN pin is pulled above
the rising EN threshold voltage VENTHR the PGOOD
Soft-Start Delay TSS begins and the output voltage begins to
rise. The output voltage enters regulation in approximately
1.5ms and the PGOOD pin goes to high impedance once TSS
has elapsed.
The negative slope of VR can be written as:
V RNEG = g m ⋅ V OUT
(EQ. 2)
1.5ms
where gm is the gain of the transconductance amplifier.
A window voltage VW is referenced with respect to the error
amplifier output voltage VCOMP, creating an envelope into
which the ripple voltage VR is compared. The amplitude of
VW is set by a resistor connected across the FSET and GND
pins. The VR, VCOMP, and VW signals feed into a window
comparator in which VCOMP is the lower threshold voltage
and VW is the higher threshold voltage. Figure 2 shows
PWM pulses being generated as VR traverses the VW and
VCOMP thresholds . The PWM switching frequency is
proportional to the slew rates of the positive and negative
slopes of VR; the PWM switching frequency is inversely
proportional to the voltage between VW and VCOMP.
VOUT
VCC and PVCC
EN
PGOOD
2.75ms
FIGURE 3. SOFT-START SEQUENCE
Ripple Capacitor Voltage CR
Window Voltage VW
Error Amplifier Voltage VCOMP
The PGOOD pin indicates when the converter is capable of
supplying regulated voltage. The PGOOD pin is an
undefined impedance if VCC has not reached the rising POR
threshold VCCR, or if VCC is below the falling POR threshold
VCCF. The ISL6268 features a unique fault-identification
capability that can drastically reduce trouble-shooting time
and effort. The pull-down resistance of the PGOOD pin
corresponds to the fault status of the controller. During
soft-start or if an undervoltage fault occurs, the PGOOD
pull-down resistance is 95Ω, or 32Ω for an overcurrent fault,
or 63Ω for an overvoltage fault.
PWM
FIGURE 2. MODULATOR WAVEFORMS DURING LOAD
TRANSIENT
7
FN6348.0
August 22, 2006
ISL6268
TABLE 1. PGOOD PULL-DOWN RESISTANCE
CONDITION
PGOOD RESISTANCE
VCC below POR
Undefined
Soft Start or Undervoltage
95Ω
Overvoltage
63Ω
Overcurrent
32Ω
The ISL6268 has internal gate-drivers for the high-side and
low-side N-Channel MOSFETs. The LG gate-driver is
optimized for low duty-cycle applications where the low-side
MOSFET conduction losses are dominant, requiring a low
r DS(on) MOSFET. The LG pull-down resistance is small in
order to clamp the gate of the MOSFET below the VGS(th) at
turn-off. The current transient through the gate at turnoff can
be considerable because the switching charge of a low
r DS(on) MOSFET can be large. Adaptive shoot-through
protection prevents a gate-driver output from turning on until
the opposite gate-driver output has fallen below
approximately 1V. The dead-time shown in Figure 4 is
extended by the additional period that the falling gate voltage
stays above the 1V threshold. The high-side gate-driver
output voltage is measured across the UG and PHASE pins
while the low-side gate-driver output voltage is measured
across the LG and PGND pins. The power for the LG
gate-driver is sourced directly from the PVCC pin. The power
for the UG gate-driver is sourced from a “boot” capacitor
connected across the BOOT and PHASE pins. The boot
capacitor is charged from a 5V bias supply through a “boot
diode” each time the low-side MOSFET turns on, pulling the
PHASE pin low. The ISL6268 has an integrated boot diode
connected from the PVCC pin to the BOOT pin.
tLGFUGR
tUGFLGR
improvement in light-load efficiency is achieved by allowing
the converter to operate in diode-emulation-mode (DEM),
where the low-side MOSFET behaves as a smart-diode,
forcing the device to block negative inductor current flow.
Positive-going inductor current flows from either the source
of the high-side MOSFET, or the drain of the low-side
MOSFET. Negative-going inductor current usually flows into
the drain of the low-side MOSFET. When the low-side
MOSFET conducts positive inductor current, the phase
voltage will be negative with respect to the GND and PGND
pins. Conversely, when the low-side MOSFET conducts
negative inductor current, the phase voltage will be positive
with respect to the GND and PGND pins. Negative inductor
current occurs when the output load current is less than half
the inductor ripple current. Sinking negative inductor through
the low-side MOSFET lowers efficiency through
unnecessary conduction losses. Efficiency can be further
improved with a reduction of unnecessary switching losses
by reducing the PWM frequency. It is characteristic of the R3
architecture for the PWM frequency to decrease while in
diode emulation. The extent of the frequency reduction is
proportional to the reduction of load current. Upon entering
DEM, the PWM frequency makes an initial step-reduction
because of a 33% step-increase of the window voltage V W.
The converter will automatically enter DEM after the PHASE
pin has detected positive voltage, while the LG gate-driver
pin is high, for eight consecutive PWM pulses. The converter
will return to CCM on the following cycle after the PHASE pin
detects negative voltage, indicating that the body diode of
the low-side MOSFET is conducting positive inductor
current.
Overcurrent and Short Circuit Protection
The overcurrent protection (OCP) and short circuit protection
(SCP) setpoint is programmed with resistor RSEN that is
connected across the ISEN and PHASE pins. The PHASE
pin is connected to the drain terminal of the low-side
MOSFET.
The SCP setpoint is internally set to twice the OCP setpoint.
When an OCP or SCP fault is detected, the PGOOD pin will
pull down to 32Ω and latch off the converter. The fault will
remain latched until the EN pin has been pulled below the
falling EN threshold voltage VENTHF or if VCC has decayed
below the falling POR threshold voltage VVCC_THF.
50%
UG
LG
50%
FIGURE 4. LG AND UG DEAD-TIME
Diode Emulation
The ISL6268 normally operates in continuous conduction
mode (CCM), minimizing conduction losses by forcing the
low-side MOSFET to operate as a synchronous rectifier. An
8
The OCP circuit does not directly detect the DC load current
leaving the converter. The OCP circuit detects the peak of
positive-flowing output inductor current. The low-side
MOSFET drain current ID is assumed to be equal to the
positive output inductor current when the high-side MOSFET
is off. The inductor current develops a negative voltage
across the r DS(on) of the low-side MOSFET that is
measured shortly after the LG gate-driver output goes high.
The ISEN pin sources the OCP sense current ISEN, through
the OCP programming resistor RSEN, forcing the ISEN pin to
0V with respect to the GND pin. The negative voltage across
FN6348.0
August 22, 2006
ISL6268
the PHASE and GND pins is nulled by the voltage dropped
across RSEN as ISEN conducts through it. An OCP fault
occurs if ISEN rises above the OCP threshold current IOC
while attempting to null the negative voltage across the
PHASE and GND pins. ISEN must exceed IOC on all the
PWM pulses that occur within 20µs. If ISEN falls below IOC
on a PWM pulse before 20µs has elapsed, the timer will be
reset. An SCP fault will occur within 10µs when ISEN
exceeds twice IOC. The relationship between ID and ISEN is
written as:
(EQ. 3)
I SEN • R SEN = I D • r DS ( on )
The value of RSEN is then written as:
I PP
⎛ I + --------⎞ • OC SP • r DS ( on )
⎝ FL
2 ⎠
R SEN = -------------------------------------------------------------------------I OC
(EQ. 4)
state that suspends the PWM , forcing the LG and UG
gate-driver outputs low. The status of the PGOOD pin does
not change nor does the converter latch-off. The PWM
remains suspended until the IC temperature falls below the
hysteresis temperature TOTHYS at which time normal PWM
operation resumes. The OTP state can be reset if the EN pin
is pulled below the falling EN threshold voltage VENTHF or if
VCC decays below the falling POR threshold voltage
V
VCC_THF. All other protection circuits function normally
during OTP. It is likely that the IC will detect an UVP fault
because in the absence of PWM, the output voltage
immediately decays below the undervoltage threshold VUV;
the PGOOD pin will pull down to 95Ω and latch-off the
converter. The UVP fault will remain latched until the EN pin
has been pulled below the falling EN threshold voltage
VENTHF or if VCC has decayed below the falling POR
threshold voltage VVCC_THF.
where:
Programming the Output Voltage
- RSEN (Ω) is the resistor used to program the overcurrent
setpoint
- ISEN is the current sense current that is sourced from the
ISEN pin
- IOC is the ISEN threshold current sourced from the ISEN
pin that will activate the OCP circuit
- IFL is the maximum continuous DC load current
- IPP is the inductor peak-to-peak ripple current
- OCSP is the desired overcurrent setpoint expressed as a
multiplier relative to IFL
When the converter is in regulation there will be 600mV from
the FB pin to the GND pin. Connect a two-resistor voltage
divider across the VO pin and the GND pin with the output
node connected to the FB pin. Scale the voltage-divider
network such that the FB pin is 600mV with respect to the
GND pin when the converter is regulating at the desired
output voltage. The output voltage can be programmed from
600mV to 3.3V.
Overvoltage Protection
When an OVP fault is detected, the PGOOD pin will pull
down to 63Ω and latch-off the converter. The OVP fault will
remain latched until the EN pin has been pulled below the
falling EN threshold voltage VENTHF or if VCC has decayed
below the falling POR threshold voltage VVCC_THF.
The OVP fault detection circuit triggers after the voltage
across the FB and GND pins has increased above the rising
overvoltage threshold VOVR. After the converter has
latched-off in response to an OVP fault, the LG gate-driver
output will retain the ability to toggle the low-side MOSFET
on and off in response to the output voltage transversing the
VOVR and VOVF thresholds.
Undervoltage Protection
When a UVP fault is detected, the PGOOD pin will pull down
to 95Ω and latch-off the converter. The fault will remain
latched until the EN pin has been pulled below the falling EN
threshold voltage VENTHF or if VCC has decayed below the
falling POR threshold voltage VVCC_THF. The UVP fault
detection circuit triggers after the voltage across the FB and
GND pins has fallen below the undervoltage threshold VUV.
Programming the output voltage is written as:
R BOTTOM
V REF = V OUT • -------------------------------------------------R TOP + R BOTTOM
(EQ. 5)
where:
- VOUT is the desired output voltage of the converter
- VREF is the voltage that the converter regulates to
between the FB pin and the GND pin
- RTOP is the voltage-programming resistor that connects
from the FB pin to the VO pin. In addition to setting the
output voltage, this resistor is part of the loop
compensation network
- RBOTTOM is the voltage-programming resistor that
connects from the FB pin to the GND pin
Beginning with RTOP between 1kΩ to 5kΩ, calculating
RBOTTOM is written as:
V REF • R
TOP
R BOTTOM = -----------------------------------V OUT – V REF
(EQ. 6)
Over-Temperature
When the temperature of the ISL6268 increases above the
rising threshold temperature TOTR, the IC will enter an OTP
9
FN6348.0
August 22, 2006
ISL6268
Programming the PWM Switching Frequency
The ISL6268 does not use a clock signal to produce PWM.
The PWM switching frequency FSW is programmed by the
resistor RFSET that is connected from the FSET pin to the
GND pin. The approximate PWM switching frequency is
written as:
1
F SW = --------------------------K ⋅ R FSET
(EQ. 7)
Estimating the value of RFSET is written as:
1
R FSET = -------------------K • F SW
(EQ. 8)
R2
C2
C1
R1
COMP
-
FB
EA
+
where:
- FSW is the PWM switching frequency
- RFSET is the FSW programming resistor
- K = 75 x 10-12
It is recommended that whenever the control loop
compensation network is modified, FSW should be checked
for the correct frequency and if necessary, adjust RFSET.
REF
FSET
RFSET
CFSET
R3
MODULATOR
Compensation Design
VO
The LC output filter has a double pole at its resonant frequency
that causes the phase to abruptly roll downward. The R3
modulator used in the ISL6268 makes the LC output filter
resemble a first order system in which the closed loop stability
can be achieved with a Type II compensation network.
Your local Intersil representative can provide a PC-based
tool that can be used to calculate compensation network
component values and help simulate the loop frequency
response. The compensation network consists of the internal
error amplifier of the ISL6268 and the external components R1,
R2, C1, and C2, as well as the frequency setting components
RFSET and CFSET (all identified in Figure 5).
VOUT
VIN
VIN
QHIGH_SIDE
UG
PHASE
LOUT
DCR
GATE DRIVERS
QLOW_SIDE
COUT
LG
GND
CESR
ISL6268
FIGURE 5. COMPENSATION REFERENCE CIRCUIT
10
FN6348.0
August 22, 2006
ISL6268
General Application Design
This document is intended to provide a high-level explanation
of the steps necessary to create a single-phase power
converter. It is assumed that the reader is familiar with many
of the basic skills and techniques referenced in the following
sections. In addition to this document, Intersil provides
complete reference designs that include schematics, bills of
materials, and example board layouts.
Selecting the LC Output Filter
The duty cycle of an ideal buck converter is a function of the
input and the output voltage. This relationship is written as:
V OUT
D = --------------V IN
(EQ. 9)
The output inductor peak-to-peak ripple current is written as:
V OUT • ( 1 – D )
I PP = ------------------------------------F SW • L OUT
The important parameters for the bulk input capacitance are
the voltage rating and the RMS current rating. For reliable
operation, select bulk capacitors with voltage and current
ratings above the maximum input voltage and capable of
supplying the RMS current required by the switching circuit.
Their voltage rating should be at least 1.25 times greater
than the maximum input voltage, while a voltage rating of 1.5
times is a preferred rating. Figure 6 is a graph of the input
RMS ripple current, normalized relative to output load current,
as a function of duty cycle that is adjusted for converter
efficiency. The ripple current calculation is written as:
•
(EQ. 11)
DCR
where ILOAD is the converter output DC current.
The copper loss can be significant so attention has to be
given to the DCR selection. Another factor to consider when
choosing the inductor is its saturation characteristics at
elevated temperature. A saturated inductor could cause
destruction of circuit components, as well as nuisance OCP
faults.
A DC/DC buck regulator must have output capacitance
COUT into which ripple current IPP can flow. Current IPP
develops a corresponding ripple voltage VPP across COUT,
which is the sum of the voltage drop across the capacitor
ESR and of the voltage change stemming from charge
moved in and out of the capacitor. These two voltages are
written as:
∆V ESR = I PP • E SR
(EQ. 12)
and
I PP
∆V C = -------------------------------------8 • C OUT • F
(EQ. 13)
SW
If the output of the converter has to support a load with high
pulsating current, several capacitors will need to be paralleled
to reduce the total ESR until the required VPP is achieved.
The inductance of the capacitor can cause a brief voltage dip
if the load transient has an extremely high slew rate. Low
inductance capacitors constructed with reverse package
geometry are available. A capacitor dissipates heat as a
function of RMS current and frequency. Be sure that IPP is
11
2
2 D
2
( I MAX ⋅ ( D – D ) ) + ⎛ x ⋅ I MAX ⋅ ------ ⎞
⎝
12 ⎠
I IN_RMS = ----------------------------------------------------------------------------------------------------I MAX
(EQ. 14)
where:
- IMAX is the maximum continuous ILOAD of the converter
- x is a multiplier (0 to 1) corresponding to the inductor
peak-to-peak ripple amplitude expressed as a percentage
of IMAX (0% to 100%)
- D is the duty cycle that is adjusted to take into account the
efficiency of the converter which is written as:
V OUT
D = ------------------------V IN ⋅ EFF
(EQ. 15)
In addition to the bulk capacitance, some low ESL ceramic
capacitance is recommended to decouple between the drain
of the high-side MOSFET and the source of the low-side
MOSFET.
NORMALIZED INPUT RMS RIPPLE CURRENT
2
Selection of the Input Capacitor
(EQ. 10)
A typical step-down DC/DC converter will have an IPP of
20% to 40% of the maximum DC output load current. The
value of IPP is selected based upon several criteria such as
MOSFET switching loss, inductor core loss, and the resistive
loss of the inductor winding. The DC copper loss of the
inductor can be estimated by:
P COPPER = I LOAD
shared by a sufficient quantity of paralleled capacitors so that
they operate below the maximum rated RMS current at FSW.
Take into account that the rated value of a capacitor can fade
as much as 50% as the DC voltage across it increases.
0.6
0.55
0.5
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
x=1
x = 0.75
x = 0.50
x = 0.25
x=0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
DUTY CYCLE
FIGURE 6. NORMALIZED RMS INPUT CURRENT FOR x = 0.8
FN6348.0
August 22, 2006
ISL6268
MOSFET Selection and Considerations
Typically, a MOSFET cannot tolerate even brief excursions
beyond their maximum drain to source voltage rating. The
MOSFETs used in the power stage of the converter should
have a maximum VDS rating that exceeds the sum of the
upper voltage tolerance of the input power source and the
voltage spike that occurs when the MOSFET switches off.
There are several power MOSFETs readily available that are
optimized for DC/DC converter applications. The preferred
high-side MOSFET emphasizes low switch charge so that
the device spends the least amount of time dissipating
power in the linear region. Unlike the low-side MOSFET
which has the drain-source voltage clamped by its body
diode during turn off, the high-side MOSFET turns off with
VIN - VOUT - VL across it. The preferred low-side MOSFET
emphasizes low r DS(on) when fully saturated to minimize
conduction loss.
As an example, suppose the high-side MOSFET has a total
gate charge Qg of 25nC at VGS = 5V, and a ∆VBOOT of
200mV. The calculated bootstrap capacitance is 0.125µF.
For a comfortable margin, select a capacitor that is double
the calculated capacitance; in this example, 0.22µF will
suffice. Use an X7R or X5R ceramic capacitor.
Layout Considerations
As a general rule, power should be on the bottom layer of
the PCB and weak analog or logic signals are on the top
layer of the PCB. The ground-plane layer should be adjacent
to the top layer to provide shielding. The ground plane layer
should have an island located under the IC, the
compensation components, and the FSET components. The
island should be connected to the rest of the ground plane
layer at one point.
VIAS TO
GROUND
PLANE
For the low-side MOSFET, (LS), the power loss can be
assumed to be conductive only and is written as:
2
P CON_LS ≈ I LOAD ⋅ r DS ( on )_LS • ( 1 – D )
(EQ. 16)
For the high-side MOSFET, (HS), its conduction loss is
written as:
P CON_HS = I LOAD
2
•
r DS ( on )_HS • D
GND
VOUT
INDUCTOR
HIGH-SIDE
MOSFETS
PHASE
NODE
VIN
OUTPUT
CAPACITORS
SCHOTTKY
DIODE
LOW-SIDE
MOSFETS
INPUT
CAPACITORS
(EQ. 17)
FIGURE 7. TYPICAL POWER COMPONENT PLACEMENT
For the high-side MOSFET, its switching loss is written as:
V IN • I VALLEY • T ON • F
V IN • I PEAK • T OFF • F
SW
SW
- + ---------------------------------------------------------------P SW_HS = -------------------------------------------------------------------2
2
(EQ. 18)
where:
- IVALLEY is the difference of the DC component of the
inductor current minus half of the inductor ripple current
- IPEAK is the sum of the DC component of the inductor
current plus half of the inductor ripple current
- TON is the time required to drive the device into saturation
- TOFF is the time required to drive the device into cut-off
Selecting The Bootstrap Capacitor
The selection of the bootstrap capacitor is written as:
Qg
C BOOT = ----------------------∆V BOOT
(EQ. 19)
Signal Ground and Power Ground
The GND pin is the signal ground for analog and logic
signals of the IC. For a robust thermal and electrical
conduction path, connect the GND pin to the island of
ground plane under the top layer using several vias.
Connect the input capacitors, the output capacitors, and the
source of the lower MOSFETs to the power ground plane.
PGND (Pin 12)
This is the return path for the pull-down of the LG low-side
MOSFET gate driver. Ideally, PGND should be connected to
the source of the low-side MOSFET with a low-resistance,
low-inductance path.
VIN (Pin 3)
The VIN pin should be connected close to the drain of the
high-side MOSFET, using a low resistance and low
inductance path.
where:
VCC (Pin 4)
- Qg is the total gate charge required to turn on the
high-side MOSFET
- ∆VBOOT, is the maximum allowed voltage decay across
the boot capacitor each time the high-side MOSFET is
switched on
For best performance, place the decoupling capacitor very
close to the VCC and GND pins.
12
PVCC (Pin 14)
For best performance, place the decoupling capacitor very
close to the PVCC and PGND pins, preferably on the same
side of the PCB as the ISL6268 IC.
FN6348.0
August 22, 2006
ISL6268
EN (Pin 5), and PGOOD (Pin 2)
LG (Pin 13)
These are logic inputs that are referenced to the GND pin.
Treat as a typical logic signal.
The signal going through this trace is both high dv/dt and
high di/dt, with high peak charging and discharging current.
Route this trace in parallel with the trace from the PGND pin.
These two traces should be short, wide, and away from
other traces. There should be no other weak signal traces in
proximity with these traces on any layer.
COMP (Pin 6), FB (Pin 7), and VO (Pin 10)
For best results, use an isolated sense line from the output
load to the VO pin. The input impedance of the FB pin is
high, so place the voltage programming and loop
compensation components close to the VO, FB, and GND
pins keeping the high impedance trace short.
FSET (Pin 9)
This pin requires a quiet environment. The resistor RFSET
and capacitor CFSET should be placed directly adjacent to
this pin. Keep fast moving nodes away from this pin.
BOOT (Pin 15), UG (Pin 16), and PHASE (Pin 1)
The signals going through these traces are both high dv/dt
and high di/dt, with high peak charging and discharging
current. Route the UG and PHASE pins in parallel with short
and wide traces. There should be no other weak signal
traces in proximity with these traces on any layer.
Copper Size for the Phase Node
ISEN (Pin 11)
Route the connection to the ISEN pin away from the traces
and components connected to the FB pin, COMP pin, and
FSET pin.
13
The parasitic capacitance and parasitic inductance of the
phase node should be kept very low to minimize ringing. It is
best to limit the size of the PHASE node copper in strict
accordance with the current and thermal management of the
application. An MLCC should be connected directly across
the drain of the upper MOSFET and the source of the lower
MOSFET to suppress the turn-off voltage spike.
FN6348.0
August 22, 2006
ISL6268
Shrink Small Outline Plastic Packages (SSOP)
Quarter Size Outline Plastic Packages (QSOP)
M16.15A
N
INDEX
AREA
H
0.25(0.010) M
16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
(0.150” WIDE BODY)
B M
E
-B1
2
INCHES
GAUGE
PLANE
3
0.25
0.010
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
α
A2
A1
B
0.17(0.007) M
L
C
0.10(0.004)
C A M
B S
NOTES:
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.061
0.068
1.55
1.73
-
A1
0.004
0.0098
0.102
0.249
-
A2
0.055
0.061
1.40
1.55
-
B
0.008
0.012
0.20
0.31
9
C
0.0075
0.0098
0.191
0.249
-
D
0.189
0.196
4.80
4.98
3
E
0.150
0.157
3.81
3.99
4
e
0.025 BSC
0.635 BSC
-
H
0.230
0.244
5.84
6.20
-
h
0.010
0.016
0.25
0.41
5
L
0.016
0.035
0.41
0.89
6
8°
0°
N
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
MILLIMETERS
α
16
0°
16
7
8°
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
Rev. 2 6/04
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.10mm (0.004 inch) total in excess
of “B” dimension at maximum material condition.
10. Controlling dimension: INCHES. Converted millimeter
dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
14
FN6348.0
August 22, 2006
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