KGF16N05D

DATASHEET
N-Channel 5.5V Dual Power MOSFET
KGF16N05D
Features
The KGF16N05D is a dual 5.5V, 1.9mΩ, chip-scale, N-channel
Power MOSFET. The device uses technology that uniquely
integrates low cost CMOS and WLCSP fabrication processes.
The chip scale package offers small area, low vertical profile
and is fully compatible with standard SMT assembly
processes. The KGF16N05D device offers unprecedented low
on-resistance and total gate charge, outperforming
conventional trench MOSFETs and enabling high frequency,
low voltage switching. The device offers extremely high power
density, reducing the board size of DC/DC converters and other
power management systems.
• Industry leading figures of merit:
rDS(ON) × Qg and rDS(ON) × Qgd
• Low profile/small footprint chip scale WLCSP package
• High frequency switching
• Known Good FET (KGF) Quality Assurance Process
• Low thermal resistance
Applications
• Point-of-load DC/DC converters
• Portable electronics
• OR’ing diodes
PRODUCT SUMMARY (PER FET)
ID
TA = +25°C
8A
Maximum
V(BR)DSS
ID = 5mA
5.5V
Minimum
rDS(ON)
VGS = 4.5V
1.9mΩ
Typical
rDS(ON)
VGS = 4.5V
(in Parallel)
0.95mΩ
Typical
Qg
VGS = 4.5V
ID = 4A
5.5nC
Typical
0.9nC
Typical
Qgd
D1
D2
G1
G2
S
FIGURE 1. EQUIVALENT CIRCUIT
January 27, 2016
FN8810.0
1
FIGURE 2. WLCSP, DIE SIZE 2.475mmx1.170mm
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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KGF16N05D
Ordering Information
PART NUMBER
PART MARKING
KGF16N05D-400
AM
Pin Configuration
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2
15
G2
D
D
14
19
18
D
13
20
17
D
S
S
S
12
S
11
S
S
S
S
6
S
G1
D
7
S
5
D
4
8
D
3
9
D
2
10
PACKAGE
(RoHS Compliant)
-55°C to +150°C
20 Bump WLCSP
Pin Descriptions
KGF16N05D
(20 BUMP WLCSP)
BOTTOM VIEW
1
TEMP RANGE
(°C)
16
PIN #
PIN NAME
DESCRIPTION
1
G1
Gate of MOSFET 1
2, 3, 4, 5
D1
Drain of MOSFET 1
6, 7, 8, 9, 10, 11,
12, 13, 14, 15
S
16, 17, 18, 19
D2
Drain of MOSFET 2
20
G2
Gate of MOSFET 2
Source of both MOSFETs
FN8810.0
January 27, 2016
KGF16N05D
Absolute Maximum Ratings
Thermal Information
(Note 1)
Drain-to-Source Voltage (VDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5V
Gate-to-Source Voltage (VGS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5.5V
Drain Current (ID1 + ID2)
Continuous (ID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16A
Pulsed (IDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40A
Single Pulse Avalanche Current (IAS), (ID1 + ID2)
L ≤ 50µH, RG ≤ 25Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10A
Thermal Resistance (Typical) (Note 2)
JA (°C/W) JP (°C/W)
WLCSP Package . . . . . . . . . . . . . . . . . . . . . .
50
10
Maximum Power Dissipation (PD) (Note 2)
TA = +25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5W
TA = +70°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6W
Junction and Storage Temperature Range (TJ, Tstg). . . . .-55°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
1. TJ = +25°C unless otherwise noted.
2. When mounted on 1 inch square 2oz copper clad FR-4.
Electrical Characteristics
SYMBOL
V(BR)DSS
IDSS
Specifications are for single MOSFET unless otherwise specified. TJ = +25°C unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
(Note 3)
TYP
MAX
(Note 3)
5.5
UNIT
Drain-to-Source Breakdown Voltage
VGS = 0 V, ID = 5mA
V
Zero Gate Voltage Drain Current
VDS = 4V, VGS = 0V, TJ = +25°C
0.01
mA
VDS = 5V, VGS = 0V, TJ = +25°C
0.1
mA
VDS = 5V, VGS = 0V, TJ = +125°C
1.0
mA
75
nA
0.9
V
IGSS
Gate-to-Body Leakage
VGS = 5.5V, VDS = 0V
VGS(th)
Gate Threshold Voltage
VDS = VGS, ID = 250µA
rDS(ON)
Drain-to-Source On-State Resistance
(per MOSFET)
VGS = 3.5V, ID = 8A
2.1
mΩ
VGS = 4.5V, ID = 8A
1.9
mΩ
VGS = 3.5V, ID = 8A
1.05
mΩ
VGS = 4.5V, ID = 8A
0.95
mΩ
VDS = 5V, VGS = 0V, f = 1MHz
600
pF
rDS(ON)
Drain-to-Source On-State Resistance
(in Parallel)
0.6
0.7
Ciss
Input Capacitance
Coss
Output Capacitance
840
pF
Crss
Reverse Transfer Capacitance
215
pF
Ciss
Input Capacitance
660
pF
Coss
Output Capacitance
1130
pF
Crss
Reverse Transfer Capacitance
265
pF
VDS = 0V, VGS = 0V, f = 1MHz
Rg
Gate Resistance
VDS = 0V, f = 1MHz
1.0
Ω
Qg
Total Gate Charge
VGS = 3.5V, ID = 4A, VDS = 4V
4.3
nC
Qgs
Gate-to-Source Charge
0.6
nC
Qgd
Gate-to-Drain Charge
0.9
nC
Qg
Total Gate Charge
VGS = 4.5V, ID = 4A, VDS = 4V
5.5
nC
trr
Source-to-Drain Reverse Recovery Time
IS = 3A, di/dt = 33A/µs
69
ns
Diode Forward Voltage
IS = 5A, VGS = 0V
VSD
0.65
1.00
V
NOTE:
3. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
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KGF16N05D
Typical Performance Curves
40
VGS = 5V TO 1.5V
35
35
ID - DRAIN CURRENT (A)
ID - DRAIN CURRENT (A)
40
30
25
20
15
10
VGS = 1.25V
5
30
25
20
15
TJ = +125°C
10
5
0
0
0.0
0.5
1. 0
1.5
2.0
0.0
0.5
VDS - DRAIN-TO-SOURCE VOL TAGE (V)
1.5
2.0
FIGURE 4. TRANSFER CHARACTERISTICS
2.4
rDS(ON) - ON-STATE RESISTANCE
(NORMALIZED)
1.5
2.2
VGS = 3.5V
2.0
1.8
VGS = 4 .5V
1.6
1.4
0
5
10
15
20
25
30
35
1.4
VGS = 4.5V
ID = 8A
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
40
-60 -40 -20
I D - DRAIN CURRENT (A)
16
14
12
I D = 8A
8
6
4
2
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VG S - GATE-TO-SOURCE VOLTAGE (V)
FIGURE 7. DRAIN-TO-SOURCE ON-STATE RESISTANCE vs
GATE-TO-SOURCE VOLTAGE
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20
40
60
80
100 120 140 160
5.0
FIGURE 6. DRAIN-TO-SOURCE ON-STATE RESISTANCE vs JUNCTION
TEMPERATURE
VGS(th) - GATE THRESHOLD VOLTAGE
(NORMALIZED)
18
10
0
TJ - JUNCTION TEMPERATURE (oC)
FIGURE 5. DRAIN-TO-SOURCE ON-STATE RESISTANCE vs DRAIN
CURRENT
rDS(ON) - ON-STATE RESISTANCE (m)
1.0
VGS - GATE-TO-SOURCE (V)
FIGURE 3. OUTPUT CHARACTERISTICS
rDS(ON) - ON-STATE RESISTANCE (mΩ)
TJ = -55°C
TJ = +25°C
1.5
1.4
1.3
1.2
I D = 250µA
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
-60 -40 -20
0
20
40
60
80
100 120 140 160
TJ - JUNCTION TEMPERATURE (o C)
FIGURE 8. GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
FN8810.0
January 27, 2016
KGF16N05D
Typical Performance Curves (Continued)
V(BR)DSS - DRAIN-TO-SOURCE
VOLTAGE (NORMALIZED)
IS - SOURCE CURRENT (A)
1.20
1 0.0
TJ = +1 25o C
TJ = +25o C
1.0
1.15
1.10
I D = 5mA
1.05
1.00
0.95
0.90
0.85
0.80
-60 -40 -20
0.1
0.0
0.2
0.4
0.6
0.8
1.0
1.2
20
40
60
80 100 120 140 160
TJ - JUNCTION TEMP ERATURE (o C)
VSD - SOURCE-TO-DRAIN VO LTAGE (V)
FIGURE 10. DRAIN-TO-SOURCE BREAKDOWN VOLTAGE vs JUNCTION
TEMPERATURE
FIGURE 9. SOURCE-TO-DRAIN DIODE FORWARD VOLTAGE
4.5
140 0
4.0
VDS = 4V
ID = 4A
3.5
120 0
C - CAPACITANCE (pF)
VGS - GATE-TO-SOURCE VOLTAGE (V)
0
3.0
2.5
2.0
1.5
1.0
0.5
Coss
100 0
8 00
Ciss
6 00
4 00
Crss
2 00
0
0
0.0
0
1
2
3
4
QG - TOTAL GATE CHARGE (nC)
1
5
4
5
FIGURE 12. CAPACITANCE
1000
ID - DRAIN CURRENT (A)
3
VD S - DRAIN-TO-SOURCE VOLTAGE (V)
FIGURE 11. GATE CHARGE
rDS(ON) LIMITED
VGS = 4.5V
100
2
TA = +25oC,
SINGLE PULSE
10ms
10
100ms
1
DC
rDS(ON) LIMIT
0.1
PACKAGE LIMIT
THERMAL LIMIT
0.01
0.1
1.0
10.0
VDS - DRAIN-TO-SOURCE VOLTAGE (V)
FIGURE 13. MAXIMUM RATED FORWARD BIASED SAFE OPERATING AREA (IN PARALLEL)
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KGF16N05D
r(t) - TRANSIENT THERMAL RESISTANCE
(NORMALIZED)
Typical Performance Curves (Continued)
1.00
0.50
0.20
0.10
0.10
0.05
0.02
SINGLE PULSE
0.01
100E-6
1E-3
10E-3
100E-3
1E+0
10E+0
100E+0
1E+3
t - TIME (s)
FIGURE 14. TRANSIENT THERMAL RESPONSE, JUNCTION-TO-AMBIENT (IN PARALLEL)
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KGF16N05D
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
January 27, 2016
FN8810.0
CHANGE
Initial release
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
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KGF16N05D
Dimensional Outline and Pad Layout
Side View
0.4mm ±30um
SILICON
0.115mm ±15um
Pad-up View
0.5mm
D
D
D
D
G1
S
S
S
S
S
S
S
S
S
S
D
D
D
D
G2
0.1mm
0.335mm
1.170mm ±15um
0.2mm
0.27mm
2.475mm ±15um
Solder Bumps are Copper pillar : 65um Cu with 35 um SAC305 cap
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Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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