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August 2004
TERSIL
1-888-IN
Low Cost Dual Power Distribution
Controller
HIP1013
FN4516.3
Features
The HIP1013 is a low cost HOT SWAP dual supply power
distribution controller. Two external N-Channel MOSFETs are
driven to distribute power while providing load fault isolation. At
turn-on, the gate of each external N-Channel MOSFET is
charged with a 10A current source. Capacitors on each gate
(see the Typical Application Diagram), create a programmable
ramp (soft turn-on) to control inrush currents. A built in charge
pump supplies the gate drive for the 12V supply N-Channel
MOSFET switch.
Over current protection is facilitated by two external current
sense resistors. When the current through either resistor
exceeds the user programmed value the N-Channel MOSFETs
are latched off by the HIP1013. The controller is reset by a
rising edge on either PWRON pin.
• HOT SWAP Dual Power Distribution Control for +5V and
+12V or +5V and +3.3V
• Provides Fault Isolation
• Charge Pump Allows the Use of N-Channel MOSFETs
• Redundant Power On Controls
• Power Good and Over Current Latch Indicators
• Adjustable Turn-On Ramp
• Protection During Turn-On
• Pb-free Available
Applications
• Power Distribution Control
• Hot Plug™ Components
Typical Application Diagram
Choosing the voltage selection mode the HIP1013 controls
either +12V/5V or +3.3V/+5V supplies.
CPUMP
Although pin compatible with the HIP1012 device, the HIP1013
does not offer current regulation during an OC event.
RSENSE
Ordering Information
PART
NUMBER
TEMP.
RANGE (°C)
12V
PACKAGE
PKG.
DWG. #
HIP1013CB
-0 to 70
14 Ld SOIC
M14.15
HIP1013CBZA (Note)
-0 to 70
14 Ld SOIC
(Pb-free)
M14.15
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.
*Tape & Reel packaging available with “-T” suffix..
CGATE
VDD
RLOAD
HIP1013
3/12VS
3/12VISEN
3/12VG
VDD
POWER ON
INPUTS
M/PON1
CGATE
GND
CPUMP
NC
PWRON2
PGOOD
5VG
5VS
5V
RILIM
RILIM
5V
5ISEN
RSENSE
RLOAD
Pinout
HIP1013 (SOIC)
TOP VIEW
3/12VS
1
14 3/12VISEN
3/12VG
2
13 RILIM
VDD 3
12 GND
MODE/ 4
PWRON1
11 CPUMP
PWRON2 5
10 NC
5VG 6
9 PGOOD
5VS 7
8 5VISEN
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 1998, 1999, 2004. All Rights Reserved
Hot Plug™ is a trademark of Core International, Inc. All other trademarks mentioned are the property of their respective owners.
2
VDD
5VIN
CGATE
12VIN
CGATE
5VS
5VG
PWRON2
MODE/
PWRON1
VDD
12VG
12VS
10A
RISING
EDGE
RESET
18V
12V
10A
R QN
R
Q
S
OC
-
+
+
-
OC
RSENSE
HIP1013
12V
ENABLE
18V
RSENSE
PGOOD
QPUMP
POR
100A
12V
5ISEN
PGOOD
NC
CPUMP
GND
RILIM
12ISEN
CPUMP
TO VDD
TO LOAD
RILIM
TO LOAD
HIP1013
Functional Diagram
HIP1013
Pin Description
PIN NO.
SYMBOL
FUNCTION
1
12VS
12V Source
Connect to source of associated external N-Channel MOSFET switch to sense output
voltage.
2
12VG
12V Gate
Connect to the gate of associated N-Channel MOSFET switch. A capacitor from this
node to ground sets the turn-on ramp. At turn-on this capacitor will be charged to 17.4V
by a 10A current source when in 5V/12V mode of operation, otherwise capacitor will be
charged to 11.4V.
3
VDD
Chip Supply
Connect to 12V supply. This can be either connected directly to the +12V rail supplying
the load voltage or to a dedicated VDD +12V supply.
4
MODE/
PWRON1
Power ON/ Reset invokes
3.3V operation when
shorted to VDD , Pin 3.
5
PWRON2
Power ON/Reset
PWRON1 and PWRON2 are used to turn-on and reset the chip. Both outputs turn-on
when either pin is driven low. After an over current limit fault, the chip is reset by the rising
edge of a reset signal applied to either PWRON pin. Each input has 100A pull up
capability which is compatible with 3V and 5V open drain and standard logic. PWRON1
is also used to invoke 3.3V control operation in preference to +12V control. By tying pin
4 to pin 3 the charge pump is disabled and the UV threshold also shifts to 2.8V.
6
5VG
5V Gate
Connect to the gate of the external 5V N-Channel MOSFET. A capacitor from this node
to ground sets the turn-on ramp. At turn-on this capacitor will be charged to 11.4V by a
10A current source.
7
5VS
5V Source
Connect to the source side of 5V external N-Channel MOSFET switch to sense output
voltage.
8
5VISEN
5V Current Sense
Connect to the load side of the 5V sense resistor to measure the voltage drop across this
resistor between 5VS and 5VISEN pins.
9
PGOOD
Power Good Indicator
PGOOD is driven by an open drain N-Channel MOSFET. It is pulled low when either
output voltage is not within specification or and OC condition exists.
10
DESCRIPTION
No Connection.
Charge Pump Capacitor
Connect a 0.1F capacitor between this pin and VDD (Pin 3).
11
CPUMP
12
GND
Chip Ground
13
RILIM
Current Limit Set Resistor
A resistor connected between this pin and ground determines the current level at which
current limit is activated. This current is determined by the ratio of the RILIM resistor to
the sense resistor (RSENSE). The current at current limit onset is equal to
10A x (RILIM / RSENSE).
14
12VISEN
12V Current Sense
Connect to the load side of sense resistor to measure the voltage drop across this
resistor.
3
HIP1013
Absolute Maximum Ratings TA = 25°C
Thermal Information
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +17V
3/12VG, CPUMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 25V
3/12VISEN, 3/12VS . . . . . . . . . . . . . . . . . . . . . . . -5V to VDD + 0.3V
5VISEN, 5VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5V to 7.5V
PGOOD, RILIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7.5V
MODE/PWRON1, PWRON2, 5VG . . . . . . . . . . -0.3V to VDD + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV (Class 2)
Thermal Resistance (Typical, Note 1)
JA (°C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
120
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
Operating Conditions
VDD Supply Voltage Range . . . . . . . . . . . . . . . . . . . +10.5V to +16V
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. JA is measured with the component mounted on an evaluation PC board in free air.
2. All voltages are relative to GND, unless otherwise specified.
Electrical Specifications
VDD = 12V, CVG = 0.01F, RSENSE = 0.1, CBULK = 220F, ESR = 0.5, TA = TJ = 0°C to 70°C, Unless
Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
85
100
115
mV
Current Overload, RILIM = 10k, RSHORT = 6.0
-
2
-
s
RTSHORT
CVG = 0.01F
-
500
1000
ns
12V Gate Turn-On Time
tON12V
CVG = 0.01F
-
12
-
ms
5V Gate Turn-On Time
tON5V
CVG = 0.01F
-
5
-
ms
Gate Turn-On Current
ION
CVG = 0.01F
8
10
12
A
CONTROL SECTION
Current Limit Threshold Voltage
(Voltage Across Sense Resistor)
VIL
Over Current Limit Response Time
Response Time To Dead Short
OCLrt
RILIM = 10k
12V Under Voltage Threshold
12VVUV
10.5
10.8
11.0
V
5V Under Voltage Threshold
5VVUV
4.35
4.5
4.65
V
2.65
2.8
2.95
V
16.8
17.3
17.9
V
11.2
11.9
-
V
IVDD
4
8
10
mA
PORrvth
9.5
10.0
10.5
V
3.3V Under Voltage Threshold
3.3VVUV
Charge pumped 12VG Voltage
V12VG
3/5VG High Voltage
3/5VG
CPUMP = 0.1F
SUPPLY CURRENT AND IO SPECIFICATIONS
VDD Supply Current
VDD POR Rising Threshold
VDD POR Falling Threshold
PORfvth
9.3
9.8
10.3
V
1.8
2.4
3.2
V
PWR_Vth
1.1
1.5
2
V
PWRON Hysteresis
PWR_hys
0.1
0.2
0.3
V
PWRON Pull-Up Current
PWRN_I
60
80
100
A
PWRON Pull-up Voltage
PWRN_V
PWRON Rising Threshold
PWRON pins open
RILIM Pin Current Source Output
RILIM_Io
90
100
110
A
Charge Pump Output Current
Qpmp_Io
CPUMP = 0.1F, CPUMP = 16V
400
590
800
A
Charge Pump Output Voltage
Qpmp_Vo
No load
17.2
17.4
-
V
Charge Pump Output Voltage - Loaded
Qpmp_VIo
Load current = 100A
16.2
16.7
-
V
Charge Pump POR Rising Threshold
Qpmp+Vth
15.6
16
16.5
V
Charge Pump POR Falling Threshold
Qpmp-Vth
15.2
15.7
16.2
V
4
HIP1013
Typical Performance Curves
8.4
105
SUPPLY CURRENT(mA)
8.2
CURRENT (A)
8.0
7.8
7.6
104
103
7.4
-30
-20 -10
10
0
20
30
50
40
60
70
102
-40
80
-30
-20
-10
0
TEMPERATURE (°C)
FIGURE 1. SUPPLY CURRENT
5V UV THRESHOLD (V)
12V UV THRESHOLD (V)
50
40
60
10.96
-20
0
20
70
80
40
60
4.610
2.884
3.3V UV
4.600
2.882
-20
0
20
40
60
80
2.880
TEMPERATURE (°C)
FIGURE 3. 12V UV THRESHOLD
FIGURE 4. 3.3V/5V UV THRESHOLD
11.935
17.36
2.886
5V UV
4.605
4.595
-40
80
2.888
TEMPERATURE (°C)
17.6
17.32
11.920
11.915
17.30
5V VG
11.910
17.28
11.905
-20
0
20
40
60
TEMPERATURE (°C)
FIGURE 5. 12V, 5V GATE DRIVE
5
11.900
80
17.4
CHARGE PUMP VOLTAGE
NO LOAD
VOLTAGE (V)
11.925
12V VG
3.3V, 5V GATE DRIVE (V)
11.930
17.34
12V GATE DRIVE (V)
30
4.615
10.98
17.26
-40
20
FIGURE 2. RILIM SOURCE CURRENT
11.00
10.94
-40
10
TEMPERATURE (°C)
3.3V UV THRESHOLD (V)
7.2
-40
17.2
17.0
CHARGE PUMP VOLTAGE
100A LOAD
16.8
16.6
-40
-20
0
20
40
TEMPERATURE (°C)
FIGURE 6. CHARGE PUMP VOLTAGE
60
80
HIP1013
Typical Performance Curves
(Continued)
10.2
VDD LOW TO HIGH
12 OC VTth
102.0
POWER ON RESET (V)
VOLTAGE THRESHOLD (mV)
102.5
101.5
5 OC Vth
101.0
100.5
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
9.8
9.6
-40
VDD HIGH TO LOW
-30 -20 -10
0
10
20
30
40
50
60
70
TEMPERATURE (°C)
FIGURE 7. OC VOLTAGE THRESHOLD WITH = RILIM 10k
HIP1013 Description and Operation
The HIP1013 offers the designer a cost efficient 5V and 12V
true hot plug controller. This device drives two external
N-Channel MOSFET switches and uses a charge pump to
provide 17V to drive the gate of the 12V supply switch. The
HIP1013 features Over Current (OC) programing with a
single external resistor, RILIM and during turn-on, the gate
capacitor of each external N-Channel MOSFET is charged
with a 10A current source. These capacitors create a
programmable ramp (soft turn-on).
Upon initial power up, the HIP1013 can either isolate the
voltage supply from the load by holding the external
N-Channel MOSFET switches off or apply the supply rail
voltage directly to the load for true hot swap capability. In
either case the HIP1013 turns on in a soft start mode
protecting the supply rail from sudden current loading.
The load currents pass through two external current sense
resistors. When the voltage across either resistor exceeds
the user programmed Over Current (OC) voltage threshold
value, (see Table 1) the HIP1013 controller turns both
N-Channel MOSFETs off in 2s.
TABLE 1.
RILIM RESISTOR
NOMINAL OC VTH
15K
150mv
10K
100mV
7.5K
75mV
4.99K
50mV
NOTE: Nominal OC Vth = RILIM x 10 A
The HIP1013 is reset by a rising edge on either PWRON pin
and is turned on by either PWRON pin being driven low. The
HIP1013 can control either +12V/5V or +3.3V/+5V supplies.
Tying the PWRON1 pin to VDD , invokes the +3.3V/+5V
voltage mode. In this mode, the external charge pump
capacitor is not needed and CPUMP, pin 11 is also tied
6
10.0
FIGURE 8. POWER ON RESET VOLTAGE THRESHOLD
directly to VDD . Upon any OC or Under Voltage (UV)
condition the PGOOD fault indicating signal will pull low
when tied high through a resistor to the logic supply.
80
HIP1013
HIP1013 Application Considerations
There is no unique and specific HIP1013 application
evaluation board. Since the HIP1013 is pin compatible with
the HIP1012 device, you can substitute a HIP1013 for the
existing HIP1012 in either of the HIP1012EVAl1 or EVAL2
boards. Otherwise contact your Intersil Corporation sales
office and an already modified board will be provided.
Although pin compatible to the HIP1012, the HIP1013 is a
less featured dual power supply distribution controller and
does not include programmable current limiting regulation
and delay time to latch off.
Random resets can also occur if the HIP1013 (PINS 8 and
14) sense pins are pulled below ground when turning off a
highly inductive load. Place a large load capacitor (10-50F)
on the output to eliminate unintended resets.
Physical layout of RSENSE resistors is critical to avoid
the possibility of false over current occurrences. Ideally
trace routing between the RSENSE resistors and the HIP1013
VS and VISEN pins are direct and as short as possible with
zero current in the sense lines.
CORRECT
TO HIP1013
VS AND VISEN
INCORRECT
TO HIP1013
VS AND VISEN
CURRENT
SENSE RESISTOR
7
HIP1013
Small Outline Plastic Packages (SOIC)
M14.15 (JEDEC MS-012-AB ISSUE C)
N
INDEX
AREA
0.25(0.010) M
H
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
B M
E
INCHES
-B-
1
2
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
e
µ
A1
B
0.25(0.010) M
C A M
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.3367
0.3444
8.55
8.75
3
E
0.1497
0.1574
3.80
4.00
4
e
C
0.10(0.004)
B S
0.050 BSC
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
N
NOTES:
MILLIMETERS

14
0o
14
8o
0o
7
8o
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
8
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