DATASHEET

HIP1015, HIP1016
®
Data Sheet
March 2003
FN4778.5
Power Distribution Controllers
Features
The HIP1015 and HIP1016 are hot swap power controllers.
The HIP1015 is targeted for a +12V bus whereas the
HIP1016 is targeted for +5V applications. Each has an
undervoltage (UV) monitoring and reporting with a threshold
level ~17% lower than the nominal +12V and +5V.
• HOT SWAP Single Power Distribution Control (HIP1015
for 12V, HIP1016 for 5V and Low Side Switch)
The HIP1015 has an integrated charge pump allowing
control of up to a +12V bus using an external N-channel
MOSFET. The HIP1016 can also be used to control much
higher positive or negative voltages in a low side controller
configuration. Both the HIP1015 and HIP1016 feature
programmable Overcurrent (OC) detection, current limiting
regulation with time delay to latch off and soft start.
• Programmable Current Limit Time to Latch-Off
Ordering Information
• Protection During Turn On
PART NUMBER
TEMP.
RANGE (oC)
PKG.
NO.
PACKAGE
• Undervoltage Monitoring and Notification
• Overcurrent Fault Isolation
• Programmable Current Regulation Level
• Rail to Rail Common Mode Input Voltage Range
(HIP1015)
• Internal Charge Pump Allows the use of N-channel
MOSFET (HIP1015)
• Undervoltage and Overcurrent Latch Indicators
• Adjustable Turn-On Ramp
• Two Levels of Overcurrent Detection Provide Fast
Response to Varying Fault Conditions
• Less Than 1µs Response Time to Dead Short
HIP1015CB
0 to 85
8 Lead SOIC
M8.15
HIP1015CB-T
0 to 85
8 Lead SOIC
Tape and Reel
M8.15
HIP1016CB
0 to 85
8 Lead SOIC
M8.15
• Hot Plug Components and Circuitry
HIP1016CB-T
0 to 85
8 Lead SOIC
Tape and Reel
M8.15
• High Side Low Voltage (< +15V) Switching
Applications
• Power Distribution Control
• Low Side High Voltage (> +15V, Negative V) Switch
Pinout
HIP1015, HIP1016 (SOIC)
TOP VIEW
Application One - High Side Controller
LOAD
+
1
8
2
7
ISET
1
8
PWRON
ISEN
2
7
PGOOD
GATE
3
6
CTIM
VSS
4
5
VDD
Application Two - Low Side Controller
+VBUS
-
LOAD
PWRON
1
2
PGOOD
3
HIP1015
HIP1016
4
3
6
OC
4
HIP1016
5
PWRON
8
7
6
5
12V REG
+12V
1
OC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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HIP1015,HIP1016
Simplified Block Diagram
VDD
+
POR
+
QN
8V
ISET
R
R
-
Q
PWRON
S
-
+
UV
+
-
VREF
ENABLE
12V
ISEN
PGOOD
10µA
CLIM
OC
+
-
GATE
FALLING
EDGE
DELAY
10µA
7.5k
-
-
+
+
1.86V
WOCLIM
18V
ENABLE
VSS
CTIM
+
-
20µA
RISING
EDGE
PULSE
18V
VDD
Pin Descriptions
PIN #
SYMBOL
FUNCTION
1
ISET
Current Set
Connect to the low side of the current sense resistor through the current limiting set resistor.
This pin functions as the current limit programming pin.
2
ISEN
Current Sense
Connect to the more positive end of sense resistor to measure the voltage drop across this
resistor
3
GATE
External FET Gate Drive
Pin
Connect to the gate of the external N-Channel MOSFET. A capacitor from this node to ground
sets the turn-on ramp. At turn-on this capacitor will be charged to VDD +5V (HIP1015) and to
VDD (HIP1016) by a 10µA current source.
4
VSS
Chip Return
5
VDD
Chip Supply
12V chip supply. This can be either connected directly to the +12V rail supplying the switched
load voltage or to a dedicated VSS +12V supply.
6
CTIM
Current Limit Timing
Capacitor
Connect a capacitor from this pin to ground. This capacitor determines the time delay
between an overcurrent event and chip output shutdown (current limit time-out). The duration
of current limit time-out (in seconds) = 93kΩ x CTIM (Farads).
7
PGOOD
Power Good Indicator
Indicates that the voltage on ISEN pin is within specification. PGOOD is driven by an open
drain N-Channel MOSFET and is pulled low when the output is not within specification.
8
PWRON
Power ON
PWRON is used to control and reset the chip. The chip is enabled when PWRON pin is driven
high or is open. After a current limit time out, the chip is reset by a low level signal applied to
this pin. This input has 20µA pull up capability
2
DESCRIPTION
HIP1015,HIP1016
Absolute Maximum Ratings TA = 25oC
Thermal Information
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +16V
GATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD+8V
ISEN, PGOOD, PWRON, CTIM, ISET. . . . . . . . -0.3V to VDD + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5kV
Thermal Resistance (Typical, Note 1)
Operating Conditions
θJA (oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
98
Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
VDD Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . +12v+/-15%
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. (See Tech Brief, #TB379.1 for
details.)
2. All voltages are relative to GND, unless otherwise specified.
VDD = 12V, TA = TJ = 0oC to 85oC, Unless Otherwise Specified
Electrical Specifications
PARAMETER
SYMBOL
ISET Current Source
TEST CONDITIONS
MIN
TYP
18.5
20
21.5
µA
VISET - VISEN
-6
0
6
mV
CTIM Voltage
1.3
1.8
2.3
V
-
100
-
ns
IISET
Current Limit Amp Offset Voltage
Current Limit Time-Out Threshold Voltage
GATE Response Time To Severe
Overcurrent
GATE Response Time to Overcurrent
GATE Turn-On Current
CTIM_Vth
pd_woc_amp
VGATE to 10.8V
pd_oc_amp
VGATE to 10.8V
IGATE
VGATE to = 6V
8.4
10
Overcurrent
45
75
Severe Overcurrent
0.5
0.8
1.5
A
9.2
9.6
10
V
GATE Pull down Current
OC_GATE_I_4V
GATE Pull down Current
WOC_GATE_I_4V
HIP1015 Undervoltage Threshold
12VUV_VTH
HIP1015 Undervoltage Disabled
12VUV_VTH_dis
HIP1015 GATE High Voltage
MAX UNITS
12VG
600
ns
11.6
mA
VDD+1.9V VDD+2.5V
GATE Voltage
µA
V
VDD+4.5V
VDD+5V
-
V
4.5
V
HIP1016 Undervoltage Threshold
5VUV_VTH
4.0
4.35
HIP1016 Undervoltage Disabled
5VUV_VTH_dis
VDD-3V
VDD-2.5V
VDD-1.5V
VDD
-
V
-
3
5
mA
HIP1016 GATE High Voltage
5VG
VDD Supply Current
IVDD
GATE Voltage
V
VDD POR Rising Threshold
VDD_POR_L2H
VDD Low to High
7.8
8.4
9
V
VDD POR Falling Threshold
VDD_POR_H2L
VDD High to Low
7.5
8.1
8.7
V
VDD POR Threshold Hysteresis
VDD_POR_HYS
VDD_POR_L2H - VDD_POR_H2L
0.1
0.3
0.6
V
PWRON Pin Open
2.7
3.2
-
V
PWRON Pull-up Voltage
PWRN_V
PWRON Rising Threshold
PWR_Vth
1.4
1.7
2.0
V
PWRON Hysteresis
PWR_hys
130
170
250
mV
PWRON Pull-Up Current
PWRN_I
9
17
25
µA
16
20
23
µA
16
20
23
mA
CTIM Charging Current
CTIM_ichg0
CTIM Fault pull-up Current
VCTIM = 0V
HIP1015 ISEN Current
ISEN_5V_I
41
72
88
µA
HIP1016 ISEN Current
ISEN_5V_I
100
145
170
µA
3
HIP1015,HIP1016
HIP1015, HIP1016 Description and Operation
The HIP1015 and HIP1016 are single power supply
distribution controllers for generic hot swap applications. The
HIP1015 is targeted for +12V switching applications
whereas the HIP1016 is targeted for +5V applications as
each has an undervoltage (UV) threshold level ~17% lower
than the nominal +12V and +5V, respectively.
The HIP1015 and HIP1016 features include a highly
accurate programmable Overcurrent (OC) detecting
comparator, programmable current limiting regulation with
programmable time delay to latch off and programmable soft
start turn-on ramp all set with a minimum of external passive
components. The HIP1015 and HIP1016 also include severe
overcurrent protection that immediately shuts down the
MOSFET switch should the load current cause the OC
voltage threshold to exceed the programmed OC level by
150mV. Additionally the HIP1015 and HIP1016 have an UV
indicator and an OC latch indicator.
Upon initial power up, the HIP1015 or HIP1016 can either
isolate the voltage supply from the load by holding the external
N-Channel MOSFET switch off or apply the supply rail voltage
directly to the load for true hot swap capability. In either case
the HIP1015 and HIP1016 turns on in a soft start mode
protecting the supply rail from sudden in-rush current. The
PWRON pin must be pulled low for the device to isolate the
power supply from the load by holding the external N-channel
MOSFET off, otherwise with the PWRON pin held high or
floating the HIP1015 and HIP1016 will be in true hot swap
mode.
At turn-on, the gate capacitor of the external N-Channel
MOSFET is charged with a 10µA current source resulting in
a programmable ramp (soft start turn-on). The internal
HIP1015 charge pump supplies the gate drive for the 12V
supply switch driving that gate to VDD +5V. The HIP1016
gate drive is limited to the chip bias voltage.
Load current passes through the external current sense
resistor. When the voltage across the sense resistor
exceeds the user programmed Overcurrent voltage
threshold value, (See Table 1 for RISET programming
resistor value and resulting nominal overcurrent threshold
voltage, VOC) the controller enters current regulation. At this
time, the time-out capacitor, on CTIM pin starts charging with
a 20mA current source and the controller enters the current
limit time to latch-off period. The length of the current limit
time to latch-off period is set by the single external capacitor
(See Table 2 for CTIM capacitor value and resulting nominal
current limited time out to latch-off period.) placed from the
CTIM pin (pin 6) to ground. The programmed current level is
held until either the OC event passes or the time out period
expires. If the former is the case then the N-Channel
MOSFET is fully enhanced and the CTIM capacitor is
discharged. Once CTIM charges to 1.87V, signaling that the
time out period has expired an internal latch is set whereby
4
the FET gate is quickly pulled to 0V turning off the NChannel MOSFET switch, isolating the faulty load.
TABLE 1.
RISET RESISTOR
NOMINAL OC VTH
10kΩ
200mV
4.99kΩ
100mV
2.5kΩ
50mV
750Ω
15mV
NOTE: Nominal Vth = RISET x 20µA.
TABLE 2.
CTIM CAPACITOR
NOMINAL CURRENT LIMITED PERIOD
0.022µF
2ms
0.047µF
4.4ms
0.1µF
9.3ms
NOTE: Nominal time-out period in seconds = CTIM x 93kΩ.
The HIP1015 and HIP1016 respond to a severe overcurrent
load (defined as a voltage across the sense resistor >150mV
over the OC Vth set point) by immediately, driving the NChannel MOSFET gate to 0V in less than 1µs. The gate
voltage is then slowly ramped up turning on the N-Channel
MOSFET to the programmed current limit level, this is the
start of the time out period.
Upon an UV condition the PGOOD signal will pull low when
tied high through a resistor to the logic supply. This pin is an
UV fault indicator. For an OC latch off indication, monitor
CTIM, pin 6. This pin will rise rapidly from 1.9V to 12V once
the time out period expires.
The HIP1015 and HIP1016 are reset after an OC latch-off
condition by a low level on the PWRON pin and is turned on
by the PWRON pin being driven high.
Application Considerations
During the Time-Out Delay Period with the HIP1015 and
HIP1016 in current limit mode, the VGS of the external NChannel MOSFETs is reduced driving the N-Channel
MOSFET switch into a high rDS(ON) state. Thus avoid
extended time out periods as the external N-Channel
MOSFETs may be damaged or destroyed due to excessive
internal power dissipation. Refer to the MOSFET
manufacturers data sheet for SOA information.
With the high levels of inrush current e.g., highly capacitive
loads and motor start up currents, choosing the current
limiting level is crucial to provide both protection and still
allow for this inrush current without latching off. Consider this
in addition to the time out delay when choosing MOSFETs
for your design.
HIP1015,HIP1016
Physical layout of RSENSE resistor is critical to avoid the
possibility of false overcurrent occurrences. Ideally trace
routing between the RSENSE resistors and the HIP1015 and
HIP1016 is direct and as short as possible with zero current
in the sense lines. (See Figure 1.)
Biasing the HIP1016
Table 3 gives typical component values for biasing the
HIP1016 in a 48V application. The formulas and calculations
deriving these values are also shown below.
TABLE 3. TYPICAL VALUES FOR A -48V HOT SWAP
APPLICATION
CORRECT
INCORRECT
SYMBOL
TO ISEN AND
RISET
PARAMETER
RCL
1.58kΩ, 1W
DD1
12V Zener Diode, 50mA Reverse Current
When using the HIP1016 to control -48V, a Zener diode may
be used to provide the +12V bias to the chip. If a Zener is
used then a current limit resistor should also be used.
Several items must be taken into account when choosing
values for the current limit resistor (RCL) and Zener Diode
(DD1):
CURRENT
SENSE RESISTOR
• The variation of the VBUS (in this case, -48V)
FIGURE 1. SENSE RESISTOR PCB LAYOUT
• The chip supply current needs for all functional conditions
Using the HIP1016 as a -48V Low Side Hot
Swap Power Controller
To supply the required VDD, it is necessary to maintain the
chip supply 12V above the -48V bus. This may be
accomplished with a +12V Regulator between the voltage
rail and pin 5 (VDD). By using a Regulator, the designer may
ignore the bus voltage variations. However, a low-cost
alternative is to use a Zener diode (See Figure 2 for typical
5A load control ) this option is detailed below.
Note that in this configuration the PGOOD feature (pin 7) is
not operational.
0.005
1%
HUF7554S3S
LOAD
0.001µF
1.47kΩ
1%
2kΩ
1
2
3
4
RCL
1.58kΩ
1W
0.01µF
HIP1016
8
7
6
5
NC
DD1
12V
VBUS
0.047µF
-48V
FIGURE 2.
5
PWRON
• The power rating of RCL.
• The current rating of DD1
Formulas
1. Sizing RCL:
RCL = (VBUS,MIN - 12)/ICHIP
2. Power Rating of RCL:
PRCL = IC(VBUS,MAX - 12)
3. DD1 Current Rating:
IDD1 = (VBUS,MAX - 12)/RCL
Example:
A typical -48V supply may vary from -36 to -72V. Therefore,
VBUS,MAX = -72V
VBUS,MIN = -36V
ICHIP = 15mA (max)
Sizing RCL:
RCL = (VBUS,MIN - 12)/IC
RCL = (36 - 12)/0.015
RCL = 1.6kΩ [Typical Value = 1.58kΩ]
Power Rating of RCL:
PRCL = IC(VBUS,MAX - 12)
PRCL = (0.015)(72 - 12)
PRCL = 0.9W [Typical Value = 1W]
DD1 Current Rating:
IDD1 = (VBUS,MAX - 12)/RCL
IDD1 = (72 - 12)/1.58kΩ
IDD1 = 38mA [Typical Value = 12V rating, 50mA reverse
current]
HIP1015,HIP1016
5.0
20.2
4.5
20.0
ISET CURRENT (µA)
SUPPLY CURRENT (mA)
Typical Performance Curves
4.0
3.5
3.0
19.8
19.6
19.4
19.2
2.5
19.0
0
2.0
10
0
20
40
30
50
60
70
80
90
100
10
20
30
TEMPERATURE (oC)
FIGURE 3. VDD BIAS CURRENT
60
70
80
90
100
90
100
90
100
1.89
CTIM OC VOLTAGE THRESHOLD (V)
20.32
CTIM - 0V
20.16
20.0
19.82
19.66
1.88
1.87
1.86
1.85
1.84
1.83
19.5
0
10
20
30
40
50
60
70
80
90
0
100
10
20
30
TEMPERATURE (oC)
FIGURE 5. CTIM CURRENT SOURCE
9.67
9.66
4.25
HIP1016
9.65
20
30
40
50
60
70
80
TEMPERATURE (oC)
FIGURE 7. UV THRESHOLD
6
60
70
80
10.2
90
4.0
100
GATE CHARGE CURRENT (µA)
HIP1015
10
50
FIGURE 6. CTIM OC VOLTAGE THRESHOLD
4.5
0
40
TEMPERATURE (oC)
HIP1016, 5V UV THRESHOLD (V)
CTIM = 0V, CURRENT SOURCE (mA)
50
FIGURE 4. ISET SOURCE CURRENT
20.5
HIP1015, 12V UV THRESHOLD (V)
40
TEMPERATURE (oC)
10.1
10.0
9.9
9.8
9.7
9.6
0
10
20
30
40
50
60
70
80
TEMPERATURE (oC)
FIGURE 8. GATE CHARGE CURRENT
HIP1015,HIP1016
(Continued)
12.00
17.183
11.99
17.166
11.98
17.150
11.97
17.133
11.96
17.116
11.95
17.100
0
10
20
30
40
50
60
70
80
8.5
11.94
90 100
POWER ON RESET (V)
17.200
HIP1016, GATE DRIVE (V)
HIP1015, GATE DRIVE (V)
Typical Performance Curves
VDD LO TO HI
8.4
8.3
8.2
VDD HI TO LO
8.1
8.0
0
10
20
30
40
50
60
70
80
90
100
TEMPERATURE (oC)
TEMPERATURE (oC)
FIGURE 9. GATE DRIVE VOLTAGE, VDD = 12V
FIGURE 10. POWER ON RESET VOLTAGE THRESHOLD
VGATE 2V/DIV
VOUT 1V/DIV
IOUT 2A/DIV
IOUT 2A/DIV
VGATE 5V/DIV
VOUT 5V/DIV
PWRON 5V/DIV
PWRON 5V/DIV
0V
0V
1.0ms/DIV
2ms/DIV
FIGURE 11.
HIP1015 HIGH SIDE +12V TURN-ON
VDRAIN 10V/DIV
IOUT 1A/DIV
FIGURE 12.
HIP1016 HIGH SIDE +5V TURN-ON
VDRAIN 10V/DIV
IOUT 1A/DIV
0V
+50V
VGATE 5V/DIV
VGATE 5V/DIV
PWRON 5V/DIV
EN 5V/DIV
0V
0V
5ms/DIV
FIGURE 13.
+50V LOW SIDE SWITCHING CGATE = 100pF
7
-50V
0V
5ms/DIV
FIGURE 14.
-50V LOW SIDE SWITCHING CGATE = 1000pF
HIP1015,HIP1016
Typical Performance Curves
(Continued)
+350V
+350V
IOUT 1A/DIV
VDRAIN 50V/DIV
IOUT 1A/DIV
VDRAIN 50V/DIV
VGATE 5V/DIV
VGATE 5V/DIV
PWRON 5V/DIV
PWRON 5V/DIV
0V
0V
2ms/DIV
FIGURE 15.
+350V LOW SIDE SWITCHING CGATE = 100pF
8
2ms/DIV
FIGURE 16.
+350V LOW SIDE SWITCHING CGATE = 1000pF
HIP1015,HIP1016
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
N
INDEX
AREA
0.25(0.010) M
H
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
B M
E
INCHES
-B-
1
2
SYMBOL
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
µα
e
A1
B
0.25(0.010) M
C
C A M
B S
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
MILLIMETERS
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.1890
0.1968
4.80
5.00
3
E
0.1497
0.1574
3.80
4.00
4
0.050 BSC
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
8o
0o
N
NOTES:
MAX
A1
e
0.10(0.004)
MIN
α
8
0o
8
7
8o
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
9
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