SiHF15N60E Datasheet

SiHF15N60E
www.vishay.com
Vishay Siliconix
E Series Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V) at TJ max.
•
•
•
•
•
•
650
RDS(on) max. () at 25 °C
VGS = 10 V
Qg max. (nC)
0.28
78
Qgs (nC)
9
Qgd (nC)
17
Configuration
Single
D
TO-220 FULLPAK
APPLICATIONS
•
•
•
•
Server and telecom power supplies
Switch mode power supplies (SMPS)
Power factor correction power supplies (PFC)
Lighting
- High-intensity discharge (HID)
- Fluorescent ballast lighting
• Industrial
- Welding
- Induction heating
- Motor drives
- Battery chargers
- Renewable energy
- Solar (PV inverters)
G
G D S
Low figure-of-merit (FOM) Ron x Qg
Low input capacitance (Ciss)
Reduced switching and conduction losses
Ultra low gate charge (Qg)
Avalanche energy rated (UIS)
Available
Material categorization: for definitions of
compliance please see www.vishay.com/doc?99912
S
N-Channel MOSFET
ORDERING INFORMATION
Package
Lead (Pb)-free
Lead (Pb)-free and Halogen-free
TO-220 FULLPAK
SiHF15N60E-E3
SiHF15N60E-GE3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
Drain-Source Voltage
VDS
600
Gate-Source Voltage
VGS
± 30
Continuous Drain Current (TJ = 150 °C) e
VGS at 10 V
TC = 25 °C
TC = 100 °C
Pulsed Drain Current a
ID
IDM
Linear Derating Factor
UNIT
V
15
9.6
A
39
0.27
W/°C
Single Pulse Avalanche Energy b
EAS
102
mJ
Maximum Power Dissipation
PD
34
W
TJ, Tstg
-55 to +150
°C
Operating Junction and Storage Temperature Range
Drain-Source Voltage Slope
Reverse Diode dV/dt
VDS = 0 V to 80 % VDS
d
Soldering Recommendations (Peak temperature) c
for 10 s
dV/dt
70
7.7
300
V/ns
°C
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature.
b. VDD = 50 V, starting TJ = 25 °C, L = 11.6 mH, Rg = 25 , IAS = 4.2 A.
c. 1.6 mm from case.
d. ISD  ID, dI/dt = 100 A/μs, starting TJ = 25 °C.
e. Limited by maximum junction temperature.
S16-0799-Rev. H, 02-May-16
Document Number: 91480
1
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHF15N60E
www.vishay.com
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum Junction-to-Ambient
RthJA
-
65
Maximum Junction-to-Case (Drain)
RthJC
-
3.7
UNIT
°C/W
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage (N)
VDS
VGS = 0 V, ID = 250 μA
600
-
-
V
VDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.71
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
2
-
4
V
VGS = ± 20 V
-
-
± 100
nA
VGS = ± 30 V
-
-
±1
μA
VDS = 600 V, VGS = 0 V
-
-
1
VDS = 480 V, VGS = 0 V, TJ = 125 °C
-
-
10
Gate-Source Leakage
IGSS
Zero Gate Voltage Drain Current
IDSS
μA
-
0.23
0.28

gfs
VDS = 30 V, ID = 8 A
-
4.6
-
S
Input Capacitance
Ciss
1350
-
Coss
-
70
-
Reverse Transfer Capacitance
Crss
VGS = 0 V,
VDS = 100 V,
f = 1 MHz
-
Output Capacitance
-
5
-
Effective Output Capacitance, Energy
Related a
Co(er)
-
53
-
Effective Output Capacitance, Time
Related b
Co(tr)
-
177
-
-
39
78
-
11
-
Drain-Source On-State Resistance
Forward Transconductance
RDS(on)
VGS = 10 V
ID = 8 A
Dynamic
pF
VDS = 0 V to 480 V, VGS = 0 V
Total Gate Charge
Qg
Gate-Source Charge
Qgs
VGS = 10 V
ID = 8 A, VDS = 480 V
Gate-Drain Charge
Qgd
-
17
-
Turn-On Delay Time
td(on)
-
16
32
Rise Time
Turn-Off Delay Time
tr
td(off)
Fall Time
tf
Gate Input Resistance
Rg
VDD = 480 V, ID = 8 A,
VGS = 10 V, Rg = 9.1 
-
26
52
-
41
82
-
22
44
f = 1 MHz, open drain
0.3
0.86
1.7
-
-
15
-
-
60
nC
ns

Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Current
ISM
Diode Forward Voltage
VSD
Reverse Recovery Time
trr
Reverse Recovery Charge
Qrr
Reverse Recovery Current
IRRM
MOSFET symbol
showing the 
integral reverse
p - n junction diode
D
A
G
TJ = 25 °C, IS = 8 A, VGS = 0 V
TJ = 25 °C, IF = IS = 8 A,
dI/dt = 100 A/μs, VR = 25 V
S
-
1.0
1.2
V
-
302
604
ns
-
4.0
8
μC
-
24
-
A
Notes
a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDSS.
b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDSS.
S16-0799-Rev. H, 02-May-16
Document Number: 91480
2
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHF15N60E
www.vishay.com
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
3
TOP
15 V
14 V
13 V
12 V
11 V
10 V
9V
8V
7V
6V
BOTTOM 5 V
40
30
ID = 8 A
TJ = 25 °C
RDS(on), Drain-to-Source
On Resistance (Normalized)
ID, Drain-to-Source Current (A)
50
20
10
10
15
20
1
VGS = 10 V
0.5
30
20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
Fig. 1 - Typical Output Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
10 000
15 V
14 V
13 V
12 V
11 V
10 V
9V
8V
7V
BOTTOM 6 V
20
1.5
VDS, Drain-to-Source Voltage (V)
TOP
25
25
TJ = 150 °C
Ciss
1000
Capacitance (pF)
ID, Drain-to-Source Current (A)
30
5
2
0
- 60 - 40 - 20 0
0
0
2.5
15
10
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds Shorted
Crss = Cgd
Coss = Cds + Cgd
Coss
100
Crss
10
5
5V
1
0
0
5
10
15
20
25
30
0
VDS, Drain-to-Source Voltage (V)
100
200
300
400
500
600
VDS, Drain-to-Source Voltage (V)
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 2 - Typical Output Characteristics
10
9
TJ = 25 °C
40
8
2000
6
TJ = 150 °C
20
Coss
5
Eoss
4
200
Eoss (μJ)
7
30
Coss (pF)
ID, Drain-to-Source Current (A)
50
3
10
2
1
0
0
20
0
5
10
15
20
25
VGS, Gate-to-Source Voltage (V)
Fig. 3 - Typical Transfer Characteristics
S16-0799-Rev. H, 02-May-16
0
100
200
300
VDS
400
500
600
Fig. 6 - Coss and Eoss vs. VDS
Document Number: 91480
3
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHF15N60E
www.vishay.com
Vishay Siliconix
20
VDS = 480 V
VDS = 300 V
VDS = 120 V
20
ID, Drain Current (A)
VGS, Gate-to-Source Voltage (V)
24
16
12
8
15
10
5
4
0
0
0
20
40
60
25
80
Qg, Total Gate Charge (nC)
50
75
100
125
150
TJ, Case Temperature (°C)
Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 10 - Maximum Drain Current vs. Case Temperature
750
100
VDS, Drain-to-Source
Breakdown Voltage (V)
ISD, Reverse Drain Current (A)
725
TJ = 150 °C
TJ = 25 °C
10
1
0.1
0.4
0.6
0.8
1
1.2
1.4
1.6
VSD, Source-Drain Voltage (V)
Operation in this Area
Limited by RDS(on)
650
625
600
575
525
- 60 - 40 - 20 0
20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
Fig. 8 - Typical Source-Drain Diode Forward Voltage
100
675
550
VGS = 0 V
0.2
700
Fig. 11 - Temperature vs. Drain-to-Source Voltage
IDM Limited
ID, Drain Current (A)
10
100 μs
Limited by RDS(on)*
1
1 ms
10 ms
0.1
TC = 25 °C
TJ = 150 °C
Single Pulse
BVDSS Limited
0.01
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Fig. 9 - Maximum Safe Operating Area
S16-0799-Rev. H, 02-May-16
Document Number: 91480
4
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHF15N60E
www.vishay.com
Vishay Siliconix
1
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
0.1
0.1
0.02
0.05
Single Pulse
0.01
0.0001
0.001
0.01
0.1
1
10
Pulse Time (s)
Fig. 12 - Normalized Thermal Transient Impedance, Junction-to-Case
RD
VDS
VDS
tp
VGS
VDD
D.U.T.
RG
+
- VDD
VDS
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
IAS
Fig. 13 - Switching Time Test Circuit
Fig. 16 - Unclamped Inductive Waveforms
VDS
QG
10 V
90 %
QGS
10 %
VGS
QGD
VG
td(on)
td(off) tf
tr
Charge
Fig. 17 - Basic Gate Charge Waveform
Fig. 14 - Switching Time Waveforms
Current regulator
Same type as D.U.T.
L
Vary tp to obtain
required IAS
VDS
50 kΩ
D.U.T
RG
+
-
IAS
12 V
0.2 µF
0.3 µF
V DD
+
D.U.T.
-
VDS
10 V
tp
0.01 Ω
VGS
3 mA
Fig. 15 - Unclamped Inductive Test Circuit
IG
ID
Current sampling resistors
Fig. 18 - Gate Charge Test Circuit
S16-0799-Rev. H, 02-May-16
Document Number: 91480
5
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHF15N60E
www.vishay.com
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
+
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 19 - For N-Channel










Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91480.
S16-0799-Rev. H, 02-May-16
Document Number: 91480
6
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
Vishay Siliconix
TO-220 FULLPAK (HIGH VOLTAGE)
A
E
A1
ØP
n
d1
d3
D
u
L1
V
L
b3
A2
b2
c
b
e
MILLIMETERS
DIM.
A
A1
A2
b
b2
b3
c
D
d1
d3
E
e
L
L1
n
ØP
u
v
ECN: X09-0126-Rev. B, 26-Oct-09
DWG: 5972
MIN.
4.570
2.570
2.510
0.622
1.229
1.229
0.440
8.650
15.88
12.300
10.360
INCHES
MAX.
4.830
2.830
2.850
0.890
1.400
1.400
0.629
9.800
16.120
12.920
10.630
MIN.
0.180
0.101
0.099
0.024
0.048
0.048
0.017
0.341
0.622
0.484
0.408
13.730
3.500
6.150
3.450
2.500
0.500
0.520
0.122
0.238
0.120
0.094
0.016
2.54 BSC
13.200
3.100
6.050
3.050
2.400
0.400
MAX.
0.190
0.111
0.112
0.035
0.055
0.055
0.025
0.386
0.635
0.509
0.419
0.100 BSC
0.541
0.138
0.242
0.136
0.098
0.020
Notes
1. To be used only for process drawing.
2. These dimensions apply to all TO-220, FULLPAK leadframe versions 3 leads.
3. All critical dimensions should C meet Cpk > 1.33.
4. All dimensions include burrs and plating thickness.
5. No chipping or package damage.
Document Number: 91359
Revision: 26-Oct-09
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1
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Revision: 02-Oct-12
1
Document Number: 91000