DATASHEET

ISL6115, ISL6116, ISL6117,
ISL6120
This family of fully featured hot swap power controllers
targets applications in the +2.5V to +12V range. The
ISL6115 is for +12V control, the ISL6116 for +5V, the
ISL6117 for +3.3V and the ISL6120 for +2.5V control
applications. Each has a hard wired undervoltage (UV)
monitoring and reporting threshold level approximately
80% of the aforementioned voltage.
The ISL6115 has an integrated charge pump allowing
control of up to +16V rails using an external N-Channel
MOSFET whereas the other devices utilize the +12V
bias voltage to fully enhance the N-Channel pass FET.
All ICs feature programmable overcurrent (OC)
detection, current regulation (CR) with time delay to
latch-off and soft-start.
The current regulation level is set by 2 external
resistors; RISET sets the CR Vth and the other is a low
ohmic sense element across, which the CR Vth is
developed. The CR duration is set by an external
capacitor on the CTIM pin, which is charged with a
20µA current once the CR Vth level is reached. If the
voltage on the CTIM capacitor reaches 1.9V the IC then
quickly pulls down the GATE output latching off the
pass FET.
This family although designed for high side switch
control the ISL6116, ISL6117, ISL6120 can also be
used in a low side configuration for control of much
higher voltage potentials.
Application Circuits- High Side
Controller
Features
• HOT SWAP Single Power Distribution Control
(ISL6115 for +12V, ISL6116 for +5V, ISL6117 for
+3.3V and ISL6120 for +2.5V)
• Overcurrent Fault Isolation
• Programmable Current Regulation Level
• Programmable Current Regulation Time to
Latch-Off
• Rail-to-Rail Common Mode Input Voltage Range
(ISL6115)
• Internal Charge Pump Allows the Use of N-Channel
MOSFET for +12V Control (ISL6115)
• Undervoltage and Overcurrent Latch Indicators
• Adjustable Turn-On Ramp
• Protection During Turn-On
• Two Levels of Overcurrent Detection Provide Fast
Response to Varying Fault Conditions
• 1µs Response Time to Dead Short
• Pb-Free Available (RoHS Compliant)
Applications
• Power Distribution Control
• Hot Plug Components and Circuit
Application Two - Low Side
Controller
+VBUS
LOAD
+
1
8
PGOOD
ISL6116
ISL6117
ISL6120
6
OC
5
PWRON
8
1
7
December 3, 2015
FN9100.8
+12V
6
5
+V SUPPLY TO BE CONTROLLED
1
4
PWRON
7
2
ISL6115
ISL6116
ISL6117
ISL6120
3
3
LOAD
4
2
-
12V REG
OC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2004-2008, 2010, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL6115, ISL6116, ISL6117, ISL6120
Power Distribution Controllers
ISL6115, ISL6116, ISL6117, ISL6120
Simplified Block Diagram
VDD
+
ISET
+
+
-
-
UV
+
-
POR
QN R
R
Q
S
8V
VREF
ENABLE
12V
ISEN
ISL61xx
UV DISABLE
OC
GATE
FALLING
EDGE
DELAY
10µA
ENABLE
VSS
PGOOD
20µA
CLIM
+
-
7.5k
CTIM
+
-
+
+
1.86V
WOCLIM
18V
PWRON
-
20µA
RISING
EDGE
PULSE
18V
VDD
Ordering Information
PART
NUMBER
PART
MARKING
TEMP.
RANGE (°C)
PACKAGE
PKG.
DWG. #
ISL6115CBZA (Notes 1, 2)
6115 CBZ
0 to +85
8 Ld SOIC (Pb-free)
M8.15
ISL6116CBZA (Notes 1, 2)
No longer available or
supported
6116 CBZ
0 to +85
8 Ld SOIC (Pb-free)
M8.15
ISL6117CBZA (Notes 1, 2)
6117 CBZ
0 to +85
8 Ld SOIC (Pb-free)
M8.15
ISL6120CBZA (Notes 1, 2)
No longer available or
supported
6120 CBZ
0 to +85
8 Ld SOIC (Pb-free)
M8.15
ISL6115EVAL1Z
Evaluation Platform
NOTES:
1. Please refer to TB347 for details on reel specifications. Add “-T” suffix for tape and reel.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6115. For more information on MSL please see
techbrief TB363.
2
FN9100.8
December 3, 2015
ISL6115, ISL6116, ISL6117, ISL6120
Pin Configuration
ISL6115, ISL6116, ISL6117, ISL6120
(8 LD SOIC)
TOP VIEW
ISET
1
8 PWRON
ISEN
2
7 PGOOD
GATE
3
6 CTIM
VSS
4
5 VDD
Pin Descriptions
PIN # SYMBOL
FUNCTION
DESCRIPTION
1
ISET
Current Set
Connect to the low side of the current sense resistor through the current limiting set
resistor. This pin functions as the current limit programming pin.
2
ISEN
Current Sense
Connect to the more positive end of sense resistor to measure the voltage drop across this
resistor.
3
GATE
External FET Gate
Drive Pin
Connect to the gate of the external N-Channel MOSFET. A capacitor from this node to
ground sets the turn-on ramp. At turn-on this capacitor will be charged to VDD +5V
(ISL6115) and to VDD (ISL6116, ISL6117, ISL6120) by a 10µA current source.
4
VSS
Chip Return
5
VDD
Chip Supply
12V chip supply. This can be either connected directly to the +12V rail supplying the
switched load voltage or to a dedicated VSS +12V supply.
6
CTIM
Current Limit Timing
Capacitor
Connect a capacitor from this pin to ground. This capacitor determines the time delay
between an overcurrent event and chip output shutdown (current limit time-out). The
duration of current limit time-out is equal to 93k x CTIM.
7
PGOOD
Power Good Indicator Indicates that the voltage on the ISEN pin is satisfactory. PGOOD is driven by an open
drain N-Channel MOSFET and is pulled low when the output voltage (VISEN) is less
than the UV level for the particular IC.
8
PWRON
Power-ON
PWRON is used to control and reset the chip. The chip is enabled when PWRON pin is
driven high to a maximum of 5V or is left open. Do not drive this input >5V. After a
current limit time-out, the chip is reset by a low level signal applied to this pin. This
input has 20µA pull-up capability.
3
FN9100.8
December 3, 2015
ISL6115, ISL6116, ISL6117, ISL6120
Absolute Maximum Ratings TA = +25°C
Thermal Information
VDD . . . . . . . . . . . . . . . . . .
GATE . . . . . . . . . . . . . . . . .
ISEN, PGOOD, PWRON, CTIM,
ESD Rating
Human Body Model . . . . . .
Thermal Resistance (Typical, Note 4)
. . . . . . . . . . . -0.3V to +16V
. . . . . . . . . -0.3V to VDD + 8V
ISET . . . -0.3V to VDD + 0.3V
. . . . . . . . . . . . . . . . . . . 5kV
Operating Conditions
JA (°C/W)
8 Ld SOIC Package . . . . . . . . . . . . . . . . . . .
98
Maximum Junction Temperature (Plastic Package) . . +150°C
Maximum Storage Temperature Range . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
VDD Supply Voltage Range (ISL6115) . . . . . . . . +12V ±15%
VDD Supply Voltage Range (ISL6116, 17, 20) . . +12V ±25%
Temperature Range (TA) . . . . . . . . . . . . . . . . 0°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379 for details.
5. All voltages are relative to GND, unless otherwise specified.
Electrical Specifications
VDD = 12V, TA = TJ = 0°C to +85°C, Unless Otherwise Specified. Temperature limits
established by characterization and are not production tested. Boldface limits apply over the
operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
MIN
(Note 7)
TYP
18.5
20
21.5
µA
TJ = +15°C to +55°C
19
20
21
µA
TEST CONDITIONS
MAX
(Note 7) UNITS
CURRENT CONTROL
ISET Current Source
IISET_ft
ISET Current Source
IISET_pt
Current Limit Amp Offset Voltage
Vio_ft
VISET - VISEN
-6
0
6
mV
Current Limit Amp Offset Voltage
Vio_pt
VISET - VISEN, TJ = +15°C to
+55°C
-2
0
2
mV
GATE DRIVE
GATE Response Time to Severe OC
GATE Response Time to Overcurrent
GATE Turn-On Current
GATE Pull-Down Current
pd_woc_amp
VGATE to 10.8V
-
100
-
ns
pd_oc_amp
VGATE to 10.8V
-
600
-
ns
IGATE
VGATE to = 6V
8.4
10
11.6
µA
Overcurrent
45
75
-
mA
0.5
0.8
-
A
9.2
9.6
10
V
-
V
OC_GATE_I_4V
GATE Pull-Down Current (Note 6)
ISL6115 Undervoltage Threshold
ISL6115 GATE High Voltage
WOC_GATE_I_4V Severe Overcurrent
12VUV_VTH
12VG
GATE Voltage
VDD + 4.5V VDD + 5V
ISL6116 Undervoltage Threshold
5VUV_VTH
4.0
4.35
4.5
V
ISL6117 Undervoltage Threshold
3VUV_VTH
2.4
2.6
2.8
V
ISL6120 Undervoltage Threshold
2VUV_VTH
1.8
1.85
1.9
V
ISL6116, ISL6117, ISL6120 GATE
High Voltage
VG
VDD - 1.5V
VDD
-
V
-
3
5
mA
GATE Voltage
BIAS
VDD Supply Current
IVDD
VDD POR Rising Threshold
VDD_POR_L2H
VDD Low to High
7.8
8.4
9
V
VDD POR Falling Threshold
VDD_POR_H2L
VDD High to Low
7.5
8.1
8.7
V
VDD POR Threshold Hysteresis
VDD_POR_HYS
VDD_POR_L2H - VDD_POR_H2L
0.1
0.3
0.6
V
-
5
-
V
Maximum PWRON Pull-Up Voltage
4
PWRN_PUV
Maximum External Pull-up
Voltage
FN9100.8
December 3, 2015
ISL6115, ISL6116, ISL6117, ISL6120
Electrical Specifications
VDD = 12V, TA = TJ = 0°C to +85°C, Unless Otherwise Specified. Temperature limits
established by characterization and are not production tested. Boldface limits apply over the
operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
PWRON Pin Open
MIN
(Note 7)
TYP
MAX
(Note 7) UNITS
2.7
3.2
-
V
PWRON Pull-Up Voltage
PWRN_V
PWRON Rising Threshold
PWR_Vth
1.4
1.7
2.0
V
PWRON Hysteresis
PWR_hys
130
170
250
mV
PWRON Pull-Up Current
PWRN_I
9
17
25
µA
16
20
23
µA
-
20
-
mA
CURRENT REGULATION DURATION/POWER GOOD
CTIM Charging Current
CTIM_ichg0
VCTIM = 0V
CTIM Fault Pull-Up Current (Note 6)
Current Limit Time-Out Threshold
Voltage
Power Good Pull Down Current
CTIM_Vth
CTIM Voltage
1.3
1.8
2.3
V
PG_Ipd
VOUT = 0.5V
-
8
-
mA
NOTES:
6. Limits established by characterization and are not production tested.
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified.
Description and Operation
The members of this IC family are single power supply
distribution controllers for generic hot swap
applications across the +2.5V to +12V supply range.
The ISL6115 is targeted for +12V switching
applications whereas the ISL6116 is targeted for +5V,
the ISL6117 for +3.3V and the ISL6120 for +2.5V
applications. Each IC has a hardwired undervoltage
(UV) threshold level approximately 17% lower than the
stated voltages.
These ICs feature a highly accurate programmable
current regulation (CR) level with programmable time
delay to latch-off, and programmable soft-start
turnHon ramp all set with a minimum of external
passive components. The ICs also include severe OC
protection that immediately shuts down the MOSFET
switch should a rapid load current transient such as
with a dead short cause the CR Vth to exceed the
programmed level by 150mV. Additionally, the ICs
have a UV indicator and an OC latch indicator. The
functionality of the PGOOD feature is enabled once
the IC is biased, monitoring and reporting any UV
condition on the ISEN pin.
Upon initial power-up, the IC can either isolate the
voltage supply from the load by holding the external
N-Channel MOSFET switch off or apply the supply rail
voltage directly to the load for true hot swap capability.
The PWRON pin must be pulled low for the device to
isolate the power supply from the load by holding the
external N-Channel MOSFET off. With the PWRON pin
held high or floating the IC will be in true hot swap
mode. In both cases the IC turns on in a soft-start
mode protecting the supply rail from sudden in-rush
current.
5
At turn-on, the external gate capacitor of the NChannel MOSFET is charged with a 10µA current
source resulting in a programmable ramp (soft-start
turn-on). The internal ISL6115 charge pump supplies
the gate drive for the 12V supply switch driving that
gate to ~VDD +5V, for the other three ICs the gate
drive voltage is limited to the chip bias voltage, VDD.
Load current passes through the external current
sense resistor. When the voltage across the sense
resistor exceeds the user programmed CR voltage
threshold value, (see Table 1 for RISET programming
resistor value and resulting nominal current regulation
threshold voltage, VCR) the controller enters its
current regulation mode. At this time, the time-out
capacitor, on CTIM pin is charged with a 20µA current
source and the controller enters the current limit time
to latch-off period. The length of the current limit time
to latch-off duration is set by the value of a single
external capacitor (see Table 2) for CTIM capacitor
value and resulting nominal current limited time-out
to latch-off duration placed from the CTIM pin (pin 6)
to ground. The programmed current level is held until
either the OC event passes or the time-out period
expires. If the former is the case then the N-Channel
MOSFET is fully enhanced and the CTIM capacitor is
discharged. Once CTIM charges to 1.87V signaling
that the time-out period has expired, an internal latch
is set whereby the FET gate is quickly pulled to 0V
turning off the N-Channel MOSFET switch, isolating
the faulty load.
FN9100.8
December 3, 2015
ISL6115, ISL6116, ISL6117, ISL6120
TABLE 1. RISET PROGRAMMING RESISTOR VALUE
RISET RESISTOR
NOMINAL CR VTH
10k
200mV
4.99k
100mV
2.5k
50mV
750
15mV
NOTE: Nominal Vth = RISET x 20µA.
TABLE 2. CTIM CAPACITOR VALUE
CTIM CAPACITOR
NOMINAL CURRENT LIMITED
PERIOD
0.022µF
2ms
0.047µF
4.4ms
0.1µF
9.3ms
NOTE: Nominal time-out period = CTIM x 93k.
This IC responds to a severe overcurrent load (defined
as a voltage across the sense resistor >150mV over
the OC Vth set point) by immediately driving the
N-Channel MOSFET gate to 0V in about 10µs. The gate
voltage is then slowly ramped up turning on the
N-Channel MOSFET to the programmed current
regulation level; this is the start of the time-out period.
Upon a UV condition, the PGOOD signal will pull low
when tied high through a resistor to the logic or VDD
supply. This pin is a UV fault indicator. For an OC
latch-off indication, monitor CTIM, pin 6. This pin will
rise rapidly from 1.9V to VDD once the time-out period
expires.
external N-Channel MOSFET is reduced driving the
MOSFET switch into a (linear region) high rDS(ON)
state. Strike a balance between the CR limit and the
timing requirements to avoid periods when the
external N-Channel MOSFETs may be damaged or
destroyed due to excessive internal power dissipation.
Refer to the MOSFET SOA information in the
manufacturer’s data sheet.
When driving particularly large capacitive loads a
longer soft-start time to prevent current regulation
upon charging and a short CR time may offer the best
application solution relative to reliability and FET MTF.
Physical layout of RSENSE resistor is critical to
avoid the possibility of false overcurrent occurrences.
Ideally, trace routing between the RSENSE resistors
and the IC is as direct and as short as possible with
zero current in the sense lines (see Figure 1)..
CORRECT
INCORRECT
TO ISEN AND
RISET
CURRENT
SENSE RESISTOR
See Figures 12 through 16 for waveforms relevant to
text.
The IC is reset after an OC latch-off condition by a low
level on the PWRON pin and is turned on by the
PWRON pin being driven high.
Application Considerations
Design applications where the CR Vth is set extremely
low (25mV or less), there is a two-fold risk to
consider.
• There is the susceptibility to noise influencing the
absolute CR Vth value. This can be addressed with a
100pF capacitor across the RSENSE resistor.
• Due to common mode limitations of the
overcurrent comparator, the voltage on the ISET
pin must be 20mV above the IC ground either
initially (from ISET*RSET) or before CTIM reaches
time-out (from gate charge-up). If this does not
happen, the IC may incorrectly report overcurrent
fault at start-up when there is no fault. Circuits
with high load capacitance and initially low load
current are susceptible to this type of unexpected
behavior.
FIGURE 1. SENSE RESISTOR PCB LAYOUT
Using the ISL6116 as a -48V
Low Side Hot Swap Power
Controller
To supply the required VDD, it is necessary to maintain
the chip supply 10V to 16V above the -48V bus. This
may be accomplished with a suitable regulator
between the voltage rail and pin 5 (VDD). By using a
regulator, the designer may ignore the bus voltage
variations. However, a low-cost alternative is to use a
Zener diode (see Figure 2 for typical 5A load control);
this option is detailed in the following.
Note that in this configuration the PGOOD feature
(pin 7) is not operational as the ISEN pin voltage is
always < UV threshold.
See Figures 17 through 20 for waveforms relevant to
-48V and other high voltage applications.
Do not signal nor pull-up the PWRON input to > 5V.
Exceeding 6V on this pin will cause the internal charge
pump to malfunction.
During the soft-start and the time-out delay duration
with the IC in its current limit mode, the VGS of the
6
FN9100.8
December 3, 2015
ISL6115, ISL6116, ISL6117, ISL6120
0.005
1%
LOAD
0.001µF
1.47k
1%
2k
1
2
3
4
RCL
Formulas
Sizing RCL is expressed in Equation 1:
V BUS  MIN  – 12
R CL = ------------------------------------------I CHIP
(EQ. 1)
Power Rating of RCL is expressed in Equation 2:
(EQ. 2)
P RCL = I C  V BUS  MAX  – 12 
1.58k
1W
0.01µF
ISL6116
DD1 current rating is expressed in Equation 3:
8
7
6
5
NC
0.047µF
12V
DD1
PWRON
VBUS
-48V
FIGURE 2. TYPICAL 5A LOAD CONTROL
Biasing the ISL6116
Table 3 gives typical component values for biasing the
ISL6116 in a ±48V application. The formulas and
calculations deriving these values are also shown in the
following equations.
TABLE 3. TYPICAL VALUES FOR A -48V HOT SWAP
APPLICATION
SYMBOL
PARAMETER
 V BUS  MAX  – 12 
I DD1 = -------------------------------------------------R CL
(EQ. 3)
Example:
A typical -48V supply may vary from -36 to -72V.
Therefore:
VBUS,MAX = -72V
VBUS,MIN = -36V
ICHIP = 15mA (Max)
Sizing RCL is expressed in Equation 4:
 V BUS  MIN  – 12 
R CL = -----------------------------------------------IC
36 – 12
R CL = ------------------0.015
(EQ. 4)
R CL = 16k  TypicalValue = 1.58k 
RCL
1.58k, 1W
Power rating of RCL is expressed in Equation 5:
DD1
12V Zener Diode, 50mA Reverse Current
P RCL = I C  V BUS  MAX  – 12 
When using the ISL6116 to control -48V, a Zener diode
may be used to provide the +12V bias to the chip. If a
Zener is used then a current limit resistor should also
be used. Several items must be taken into account
when choosing values for the current limit resistor
(RCL) and Zener Diode (DD1):
• The variation of the VBUS (in this case, -48V
nominal)
• The chip supply current needs for all functional
conditions
P RCL =  0.015   72 – 12 
(EQ. 5)
P RCL = 0.9W  TypicalValue = 1W 
DD1 current rating is expressed in Equation 6:
 V BUS  MAX  – 12 
I DD1 = -------------------------------------------------R CL
 72 – 12 
I DD1 = -----------------------1.58k
(EQ. 6)
I DD1 = 38mA  TypicalValue = 12Vrating, 50mA reverse current 
• The power rating of RCL.
• The current rating of DD1
7
FN9100.8
December 3, 2015
ISL6115, ISL6116, ISL6117, ISL6120
5.0
20.2
4.5
20.0
ISET CURRENT (µA)
4.0
3.5
3.0
19.8
19.6
19.4
19.2
2.5
19.0
0
2.0
0
10
20
30
40
50
60
70
90
80
100
10
20
30
70
80
90
100
90
100
1.89
CTIM OC VOLTAGE THRESHOLD (V)
CTIM = 0V, CURRENT SOURCE (µA)
60
FIGURE 4. ISET SOURCE CURRENT
20.50
20.32
CTIM - 0V
20.16
20.00
19.82
19.66
1.88
1.87
1.86
1.85
1.84
1.83
19.50
0
10
20
30 40
50 60 70
TEMPERATURE (°C)
80
90
0
100
4.37
9.75
4.36
9.74
40
50
60
70
80
90
4.35
100
TEMPERATURE (°C)
FIGURE 7. ISL6115, ISL6116 UV THRESHOLD
8
ISL6117, 3.3V UV THRESHOLD (V)
ISL6115
30
30
40
50
60
70
80
2.70
ISL6116, 5V UV THRESHOLD (V)
ISL6116
20
20
FIGURE 6. CTIM OC VOLTAGE THRESHOLD
9.76
10
10
TEMPERATURE (°C)
FIGURE 5. CTIM CURRENT SOURCE
ISL6115, 12V UV THRESHOLD (V)
50
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 3. VDD BIAS CURRENT
0
40
1.860
ISL6117
2.65
1.855
ISL6120
2.60
0
10
20
30
40
50
60
70
80
90
1.850
100
ISL6120, 2.5V UV THRESHOLD (V)
SUPPLY CURRENT (mA)
Typical Performance Curves
TEMPERATURE (°C)
FIGURE 8. ISL6117, ISL6120 UV THRESHOLD
FN9100.8
December 3, 2015
ISL6115, ISL6116, ISL6117, ISL6120
10.2
17.200
12.00
10.1
17.183
11.99
17.166
11.98
17.150
11.97
17.133
11.96
17.116
11.95
10.0
9.9
9.8
9.7
9.6
0
17.100
10
20
30
40
50
60
70
80
90
100
0
10
TEMPERATURE (°C)
20
30
40
50
60
70
80
90
ISL6116,17,20 GATE DRIVE (V)
(Continued)
ISL6115, GATE DRIVE (V)
GATE CHARGE CURRENT (µA)
Typical Performance Curves
11.94
100
TEMPERATURE (°C)
FIGURE 10. GATE DRIVE VOLTAGE, VDD = 12V
FIGURE 9. GATE CHARGE CURRENT
8.5
VDD LO TO HI
POWER ON RESET (V)
8.4
8.3
GATE
VOUT
8.2
PGOOD
VDD HI TO LO
8.1
IOUT
PWRON
8.0
0
10
20
30
40
50
60
70
80
90
100
5V/DIV 0.5A/DIV 1ms/DIV
TEMPERATURE (°C)
FIGURE 11. POWER-ON RESET VOLTAGE THRESHOLD
FIGURE 12. ISL6115 +12V TURN-ON
GATE
PGOOD
GATE
PWRON
IOUT
VOUT
VOUT
IOUT
CTIM
PGOOD
2V/DIV 0.5A/DIV 1ms/DIV
FIGURE 13. ISL6116 +5V TURN-ON
9
5V/DIV 0.5A/DIV 1ms/DIV
FIGURE 14. ISL6115 ‘LOW’ OVERCURRENT RESPONSE
FN9100.8
December 3, 2015
ISL6115, ISL6116, ISL6117, ISL6120
Typical Performance Curves
(Continued)
IOUT
VOUT
IOUT
PGOOD
GATE
GATE
CTIM
CTIM
VOUT
PGOOD
5V/DIV 0.5A/DIV 1ms/DIV
2V/DIV 0.5A/DIV 1ms/DIV
FIGURE 15. ISL6115 ‘HIGH’ OVERCURRENT RESPONSE
VDRAIN 10V/DIV
FIGURE 16. ISL6116 ‘HIGH’ OVERCURRENT RESPONSE
VDRAIN 10V/DIV
IOUT 1A/DIV
IOUT 1A/DIV
0V
+50V
VGATE 5V/DIV
VGATE 5V/DIV
PWRON 5V/DIV
EN 5V/DIV
0V
0V
-50V
0V
5ms/DIV
5ms/DIV
FIGURE 17. +50V LOW SIDE SWITCHING
CGATE = 100pF
+350V
FIGURE 18. -50V LOW SIDE SWITCHING
CGATE = 1000pF
+350V
IOUT 1A/DIV
VDRAIN 50V/DIV
IOUT 1A/DIV
VDRAIN 50V/DIV
VGATE 5V/DIV
VGATE 5V/DIV
PWRON 5V/DIV
PWRON 5V/DIV
0V
0V
2ms/DIV
FIGURE 19. +350V LOW SIDE SWITCHING
CGATE = 100pF
10
2ms/DIV
FIGURE 20. +350V LOW SIDE SWITCHING
CGATE = 1000pF
FN9100.8
December 3, 2015
ISL6115, ISL6116, ISL6117, ISL6120
ISL6115EVAL1Z Board
Bias and load connection points are provided in
addition to test points, TP1 to TP8 for each IC pin. The
terminals, J1 and J4 are for the bus voltage and return,
respectively, with the more negative potential being
connected to J4. With the load between terminals J2
and J3 the board is now configured for evaluation. The
device is enabled through LOGIN, TP9 with a TTL
signal. ISL6116EVAL1 includes a level shifting circuit
with an opto-coupling device for the PWRON input so
that standard TTL logic can be translated to the -V
reference for chip control.
The ISL6115EVAL1Z is default provided as a +12V high
side switch controller with the CR level set at ~1.5A.
See Figure 21 for ISL6115EVAL1Z schematic and Table
4 for BOM. Bias and load connection points are
provided along with test points for each IC pin.
With J1 installed the ISL6115 will be biased from the
+12V supply (VIN) being switched. Connect the load to
VLOAD+. PWRON pin pulls high internally enabling the
ISL6115 if not driven low via PWRON test point or J2.
When controlling a positive voltage, PWRON can be
accessed at TP8.
With R3 = 750 the CR Vth is set to 15mV and with
the 10m sense resistor (R1) the ISL6115EVAL1Z has
a nominal CR level of 1.5A. The 0.01µF delay time to
latch-off capacitor results in a nominal 1ms before
latch-off of output after an OC event.
The ISL6116EVAL1 is provided with a high voltage
linear regulator for convenience to provide chip bias
from ±24V to ±350V. This can be removed and
replaced with the zener and resistor bias scheme as
discussed earlier. High voltage regulators and power
discrete devices are no longer available from Intersil
but can be purchased from other semiconductor
manufacturers.
Also included with the ISL6115EVAL1Z board are one
each of the ISL6116, ISL6117 and ISL6120 for
evaluation of those ICs in a high side application.
Remove J1 and provide a separate +12V IC bias supply
via VBIAS test point.
Reconfiguring the ISL6116EVAL1 board for a higher CR
level can be done by changing the RSENSE and RISET
resistor values as the provided FET is 75A rated. If
evaluation at >60V, an alternate FET must be chosen
with an adequate BVDSS.
Reconfiguring the ISL6115EVAL1Z board for a higher
CR level can be done by changing the RSENSE and/or
RISET resistor values as the provided FET is rated for a
much higher current.
ISL6116EVAL1 Board
The ISL6116EVAL1 is default configured as a negative
voltage low side switch controller with a ~2.4A CR
level. See Figure 22 for ISL6116EVAL1 schematic and
Table 4 for BOM and component description. This basic
configuration is capable of controlling both larger
positive or negative potential voltages with minimal
changes.
HI J2
LOAD
J3 LO
R1
Q2
J1
3
PGOOD
7
R11
VBIAS
8
VIN
+12V
VBIAS
PWRON
TP8
LOGIN
TP9
R10
R8
R6
C1
J1
7
R
G
1
6
R4
C2
C3
5
5
C3
R2
ISL6116
U1
CTIM
6
U2
4
U1
PWRON
8
ISL6115
1
2
2
R1
4
J2
1
3
VOUT
R3
R2
R7
+VBUS
AGND
VLOAD+
J4
-VBUS
C1
D2
DD1
3.3V
R5
R9
OFF
0V to 5V
OT1
FIGURE 21. ISL6115EVAL1Z HIGH SIDE SWITCH
APPLICATION
11
ON
FIGURE 22. ISL6116EVAL1 NEGATIVE VOLTAGE LOW
SIDE CONTROLLER
FN9100.8
December 3, 2015
ISL6115, ISL6116, ISL6117, ISL6120
TABLE 4. BILL OF MATERIALS, ISL6115EVAL1Z, ISL6116EVAL1
COMPONENT
DESIGNATOR
COMPONENT NAME
COMPONENT DESCRIPTION
ISL6115EVAL1Z
U1
N-FET
11.5m, 30V, 11.5A Logic Level N-Channel Power MOSFET or equivalent
R1
Load Current Sense Resistor
WSL-2512 10m 1W Metal Strip Resistor
R2
Gate Stability Resistor
20 0603 Chip Resistor
R3
Overcurrent Voltage Threshold Set
Resistor
750 0603 Chip Resistor (Vth = 15mV)
R4
PGOOD Pull up Resistor
10k 0603 Chip Resistor
C1
Gate Timing Capacitor
0.001µF 0402 Chip Capacitor (<2ms)
C2
IC Decoupling Capacitor
0.1µF 0402 Chip Capacitor
C3
Time Delay Set Capacitor
0.01µF 0402 Chip Capacitor (1ms)
J1
Bias Voltage Selection Jumper
Install if switched rail voltage is = +12V. Remove and provide separate
+12V bias voltage to U2 via VBIAS if ISL6116, ISL6117 or ISL6120 is
being evaluated.
J2
PWRON Disable
Install J2 to disable U2. Connects PWRON to GND.
N-FET
10m, 80V, 75A N-Channel Power MOSFET or equivalent
ISL6116EVAL1
Q2
R1
Load Current Sense Resistor
WSL-2512 10m 1W Metal Strip Resistor
R2
Overcurrent Voltage Threshold Set
Resistor
1.21k 805 Chip Resistor (Vth = 24mV)
R7
Gate to Drain Resistor
2k 805 Chip Resistor
C1
Gate Timing Capacitor
0.001µF 805 Chip Capacitor (<2ms)
C3
IC Decoupling Capacitor
0.1µF 805 Chip Capacitor
R5
LED Series Resistors
2.32k 805 Chip Resistor
D2
Fault Indicating LEDs
Low Current Red SMD LED
DD1
Fault Voltage Dropping Diode
3.3V Zener Diode, SOT-23 SMD 350mW
OT1
PWRON Level Shifting Opto-Coupler
PS2801-1 NEC
R8
Level Shifting Bias Resistor
2.32k 805 Chip Resistor
R9
Level Shifting Bias Resistor
1.18k 805 Chip Resistor
R10
Level Shifting Bias Resistor
200 805 Chip Resistor
RG1
HIP5600IS
High Voltage Linear Regulator
R6
Linear Regulator RF1
1.78k 805 Chip Resistor
R11
Linear Regulator RF2
15k 805 Chip Resistor
12
FN9100.8
December 3, 2015
ISL6115, ISL6116, ISL6117, ISL6120
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest revision.
DATE
REVISION
CHANGE
December 3, 2015
FN9100.8
Added Rev History and About Intersil sections.
Updated Ordering Information on page 2.
Updated POD M8.15 to most current version. Revision changes are as follows:
Updated to new POD format by removing table and moving dimensions onto drawing and
adding land pattern
Changed in Typical Recommended Land Pattern the following:
2.41(0.095) to 2.20(0.087)
0.76 (0.030) to 0.60(0.023)
0.200 to 5.20(0.205)
Changed Note 1 "1982" to "1994"
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The
company's products address some of the largest markets within the industrial and infrastructure, mobile
computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the
respective product information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
13
FN9100.8
December 3, 2015
ISL6115, ISL6116, ISL6117, ISL6120
Package Outline Drawing
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 1/12
DETAIL "A"
1.27 (0.050)
0.40 (0.016)
INDEX
6.20 (0.244)
5.80 (0.228)
AREA
0.50 (0.20)
x 45°
0.25 (0.01)
4.00 (0.157)
3.80 (0.150)
1
2
8°
0°
3
0.25 (0.010)
0.19 (0.008)
SIDE VIEW “B”
TOP VIEW
2.20 (0.087)
SEATING PLANE
5.00 (0.197)
4.80 (0.189)
1.75 (0.069)
1.35 (0.053)
1
8
2
7
0.60 (0.023)
1.27 (0.050)
3
6
4
5
-C-
1.27 (0.050)
0.51(0.020)
0.33(0.013)
SIDE VIEW “A
0.25(0.010)
0.10(0.004)
5.20(0.205)
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1994.
2. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
3. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.
14
FN9100.8
December 3, 2015
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