DATASHEET

ISL6173
®
Data Sheet
January 3, 2006
FN9186.3
Dual Low Voltage Hot Swap Controller
Features
This IC targets dual voltage hot swap applications across the
+2.5V to +3.3V (nominal) bias supply voltage range with a
second lower voltage rail down to less than 1V. It features a
charge pump for driving external N-Channel MOSFETs,
regulated current protection and duration, output undervoltage
monitoring and reporting, optional latch-off or retry response,
and adjustable soft-start.
• Fast Current Regulation amplifier quickly responds to
overcurrent fault conditions
The current regulation level (CR) for each rail is set by two
external resistors and each CR duration is set by an external
capacitor on the TIM pin. After the CR duration has expired
the IC then quickly pulls down the associated GATE(s)
output turning off its external FET(s). The ISL6173 offers a
latched output or indefinite auto retry mode of operation.
• Overcurrent Circuit Breaker and Fault Isolation functions
Ordering Information
PART
MARKING
ISL6173DRZA
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL6173DRZA-T ISL6173DRZ 0 to +85 28 Ld 5x5 QFN L28.5x5
Tape & Reel
Evaluation Platform
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Pinout
• Adjustable Current Regulation Threshold as low as 20mV
• Selectable Latch-off or Auto Retry Response to Fault
conditions
• Adjustable voltage ramp-up for In-rush Protection During
Turn-On
UV1
EN1
OCREF
EN2
UV2
VS2
27
26
25
24
23
22
VO2
SS1
3
19
SS2
GT1
4
18
GT2
FLT1
5
17
FLT2
PG1
6
16
PG2
CT1
7
15
CT2
9
10
11
12
13
14
CPVDD
20
CPQ+
2
BIAS
VO1
CPQ-
SNS2
PGND
21
GND
1
RTR/LTCH
SNS1
8
• Charge Pump Allows the use of N-Channel MOSFETs
• QFN Package:
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Power Supply Sequencing, Distribution and Control
• Hot Swap/Electronic Breaker Circuits
Rsns1
V1(out)
Rset1
VS1
28
• Dual Supply Hot Swap Power Distribution Control to <1V
V1(in)
ISL6173 (28 LD QFN) TOP VIEW
1
• Two Levels of Overcurrent Detection Provide Fast
Response to Varying Fault Conditions
• Rail Independent Control, Monitoring and Reporting I/O
TEMP.
RANGE
(°C)
ISL6173DRZ 0 to +85 28 Ld 5x5 QFN L28.5x5
ISL6173EVAL3
• Programmable Current Regulation Level and Duration
EN1 EN2 VS1
RTR/LTCH
BIAS
CPQ+
SNS1 GT1 VO1
UV1
PG1
FLT1
SS1
CPQOCREF
ISL6173
CPVDD
SS2
FLT2
PG2
PGND
GND
UV2
CT1 CT2 VS2
SNS2 GT2 VO2
V2(in)
Rset2
PART NUMBER
(Note)
• Less than 1µs response Time to Dead Short
V2(OUT)
Rsns2
FIGURE 1. TYPICAL APPLICATION
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL6173
Block Diagram
Io
Vin
LOAD
Vo
Rsns
Q
Current
Limit
Amplifier
VO1
GT1
SNS1
Rset
VS1
Iset
10V
24µA
Soft Start
Amplifier
-
CPVDD
-
+
10µA
42µA
SS1
+
3K
Css
+
WOC
Comparator
1.178V
OCREF
Rref
OC Timer
&
Logic
+
Iref
Iref
4
Current
Mirror
FLT1
OC
Comparator
10µA
+
10K
Ct
Timeout
Comparator
1.178V
-
633mV
BIAS
RTR/LTCH
PG1
CT1
BIAS
EN1
CPVDD
-
Rs1
10K
UV1
UV
+
Comparator
BIAS
Rs2
CPQ+
X2
Charge
Pump
Cp
X2
Charge
Pump
10V(out)
CPQCPVDD
Cv
633mV
POR and
Bandgap
GND
PGND
1.178V
ISL6173
FIGURE 2. ISL6173 - INTERNAL BLOCK-DIAGRAM OF THE IC - CHANNEL ONE ONLY
2
FN9186.3
January 3, 2006
ISL6173
Pinout
VS1
UV1
EN1
OCREF
EN2
UV2
VS2
28 LEAD QFN
TOP VIEW
28
27
26
25
24
23
22
20
VO2
SS1
3
19
SS2
GT1
4
18
GT2
FLT1
5
17
FLT2
PG1
6
16
PG2
CT1
7
15
CT2
9
10
11
12
13
14
CPVDD
8
CPQ+
2
BIAS
VO1
CPQ-
SNS2
PGND
21
GND
1
RTR/LTCH
SNS1
Pin Descriptions
PIN
NAME
1
SNS1
2
FUNCTION
DESCRIPTION
Current Sense Input
This pin is connected to the current sense resistor and control MOSFET Drain node. It provides
current sense signal to the internal comparator and amplifier in conjunction with VS1 pin.
VO1
Output Voltage 1
This pin is connected to the control MOSFET switch source, which connects to a load. Internally, this
voltage is used for SS control.
3
SS1
Soft-Start Duration Set
Input
A capacitor from this pin to ground sets the output soft-start ramp slope. This capacitor is charged by
the internal 10µA current source setting the soft-start ramp. The output voltage ramp tracks the SS
ramp by controlled enhancement of FET gate. Once ramp-up is completed, the capacitor continues
to charge to the CPVDD voltage rail. If common capacitor is used (by tying SS1, SS2 together and
the capacitor to GND from the connection) then both the outputs track each other as they ramp up.
4
GT1
Gate Drive Output
Direct connection to the gate of the external N-Channel MOSFET. At turn-on the Gate will charge to
4 X Vbias or 10V(max) from the 24µA source.
5
FLT1
Fault Output
This is an open drain output. It asserts (pulls low) once the current regulation duration (determined
by the CTx timeout cap) has expired. This output is valid for Vbias>1V.
6
PG1
Power Good Output
This is an active low, open drain output. When asserted (logic zero), it indicates that the voltage on
UV1 pin is more than 643mV (633mV + 10mV hysteresis). This output is valid at VBIAS >1V.
7
CT1
Timer Capacitor
A capacitor from this pin to ground controls the current regulation duration from the onset of current
regulation to channel shutdown (current limit time-out). Once the voltage on CTx cap reaches
VCT_Vth the GATE output is pulled down and the FLT is asserted.
The duration of current limit time-out = (CTIM*1.178)/10µA
When the OC comparator trips AND the RTR/LTCH pin is pulled low, the IC’s faulty channel remains
shut down for 64 cycles (each cycle length is equal to the current limit time-out duration).
8
RTR/
LTCH
Retry Or Latch Input
This input dictates the IC behavior (for either channel) under OC condition. If it is pulled high (or left
floating), the IC will shut down upon OC time-out. If it is pulled low, the IC will go into retry mode after
an interval determined by the capacitor on CTx pin. The faulting channel will remain shut down for
64 cycles and will try to come out of it on the 65th cycle. Each cycle length is determined by the
formula shown in CT pin description.
9
GND
Chip Gnd
This pin is also internally shorted to the metal tab at the bottom of the IC.
10
PGND
Charge pump ground. Both GND and PGND must be tied together externally.
3
FN9186.3
January 3, 2006
ISL6173
Pin Descriptions (Continued)
PIN
NAME
FUNCTION
DESCRIPTION
11
CPQ-
Charge Pump Capacitor Flying cap lowside.
Low Side
12
BIAS
Chip Bias Voltage
13
CPQ+
Charge Pump Capacitor Flying cap highside. Use of 0.1µF for 2.5V bias and 0.022µF for 3.3V bias is recommended.
High Side
14
CPVDD
15
Provides IC Bias. Should be 2V to 4V for IC to function normally. This pin can be powered from a
supply voltage that is not being controlled. It is preferable to use 3.3V even if the channels being
controlled are 2.5V or lower because more gate drive voltage will be available to the MOSFETs.
Charge Pump Output
This is the voltage used for some internal pullups and bias. Use of 0.47µF (minimum) is
recommended.
CT2
Timer Capacitor
Same function as pin 7
16
PG2
Power Good Output
Same function as pin 6
17
FLT2
Fault Output
Same as pin 5
18
GT2
Gate Drive Output
Same as pin 4
19
SS2
Soft-Start Duration Set
Input
Same as pin 3
20
VO2
Output Voltage 2
Same as pin 2
21
SNS2
Current Sense Input
Same as pin 1
22
VS2
Current Sense
Reference
Voltage input for one of the two voltages. Provides a 20µA current source for the ISET series resistor
which sets the voltage to which the sense resistor IR drop is compared.
23
UV2
Undervoltage Monitor
Input
This pin is one of the two inputs to the undervoltage comparator. The other input is the 633mV
reference. It is meant to sense the output voltage through a resistor divider. If the output voltage
drops so that the voltage on the UV pin goes below 633mV, PG2 is deasserted.
24
EN2
Enable
This is an active low input. When asserted (pulled low), the SS and gate drive are released and the
output voltage gets enabled. When deasserted (pulled high or left floating), the reverse happens.
25
OCREF
Ref. Current Adj.
Allows adjustment of the reference current through RSET and the internal current regulation set
resistor, thus setting the thresholds for CR, OC and WOC.
26
EN1
Enable Input
Same as pin 24
27
UV1
Undervoltage Monitor
Input
Same as pin 23
28
VS1
Current Sense
Reference
Same as pin 22
4
FN9186.3
January 3, 2006
ISL6173
Absolute Maximum Ratings
Thermal Information
VBIAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5V
GTx, CPQ+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +12V
ENx, RTR/LTCH, SNSx, PGx, FLTx, VSx, CTx, UVx,
SSx, CPQ-, CPVDD. . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.5VDC
Output Current . . . . . . . . . . . . . . . . . . . . . . . Short Circuit Protected
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . .1750V
Machine Model (Per EIAJ ED-4701 Method C-111) . . . . . . . .125V
Charged Device Model (Per EOS/ESD DS5.3, 4/14/93) . . .1750V
Thermal Resistance (Typical, Notes 1, 4)
θJA (°C/W)
θJC (°C/W)
5x5 QFN Package . . . . . . . . . . . . . . . .
42
12.5
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
For recommended soldering conditions, see Tech Brief TB389.
(QFN - Leads Only)
Operating Conditions
VBIAS/VIN1 Supply Voltage Range. . . . . . . . . . . . +2.25V to +3.63V
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. All voltages are relative to GND, unless otherwise specified.
3. 1V (min) on the BIAS pin required for FLT to be valid.
4. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
VDD = 2.5V to +3.3V, VS = 1V ,TA = TJ = 0°C - 85°C, Unless Otherwise Specified.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CURRENT REGULATION CONTROL
ISET Current
ISET_ft
ROCREF = 14.7kΩ
18.7
20
21.3
µA
Partial Temp Range ISET Current
ISET_pt
ROCREF = 14.7kΩ
TJ = 25oC to 60oC
19
20
21
µA
Current Limit Amp Offset Voltage
Vio_ft
VVS - VSNS with IOUT = 0A
-2
2
mV
Partial Temp. Current Limit Amp Offset
Voltage
Vio_pt
VVS - VSNS with IOUT = 0A
TJ = 25°C to 60°C
-1
1
mV
Current Regulation Threshold Voltage
VCRVTH_1
RISET = 1.25K, ISET = 20µA
23
27
mV
VCRVTH_1R
RISET = 1.25K, ISET = 20µA
-8
+8
%
VCRVTH_2
RISET = 2.50K, ISET = 20µA
48
52
mV
VCRVTH_2R
RISET = 2.50K, ISET = 20µA
-4
+4
%
VCRVTH_3
RISET = 0.499K, ISET = 20µA
8
12
mV
VCRVTH_3R
RISET = 0.499K, ISET = 20µA
-20
+20
%
1.202
V
Current Regulation Accuracy
Current Regulation Threshold Voltage
Current Regulation Accuracy
Current Regulation Threshold Voltage
Current Regulation Accuracy
CT Threshold Voltage
VCT_Vth
CT Charging Current
ICT
1.128
25
50
10
1.178
10
µA
3
ns
100
ns
5
µs
GATE DRIVE
GATE Response Time from WOC (Open)
pd_woc_open
GATE open
100mV of overdrive on the WOC
comparator
GATE Response Time from WOC
(Loaded)
pd_woc_load
GATE = 1nF
GATE Response Time in Current
Regulation mode (Loaded)
pd_cr_load
GATE Turn-On Current
IGATE
5
GATE = 1nF
120% Load Current
GATE = 2V, VVS = 2V, VSNS = 2.1V
21
24
27
µA
FN9186.3
January 3, 2006
ISL6173
Electrical Specifications
VDD = 2.5V to +3.3V, VS = 1V ,TA = TJ = 0°C - 85°C, Unless Otherwise Specified. (Continued)
PARAMETER
SYMBOL
GATE Voltage
VGATE
TEST CONDITIONS
Bias = 2.5V (see graph on page 7)
MIN
TYP
7.5
2.1 < Bias < 2.5
(see graph on page 7)
8
VBIAS = 3.3V
9
MAX
UNIT
9.0
V
V
BIAS
Supply Current
IBIAS
17
mA
POR Rising Threshold
VIN_POR_L2H
2.12
V
POR Falling Threshold
VIN_POR_H2L
2.10
V
POR Threshold Hysteresis
VIN_POR_HYS
5
Undervoltage Comparator Falling
Threshold
VUV_VTHF
620
635
650
mV
Undervoltage Comparator Hysteresis
VUV_HYST
7
16
25
mV
mV
I/O
EN Rising Threshold
PWR_Vth_R
VBIAS = 2.5V
1.55
1.95
2.19
V
EN Falling Threshold
PWR_Vth_F
VBIAS = 2.5V
0.97
1.10
1.30
V
EN Hysteresis
PWR_HYST
VBIAS = 2.5V
600
850
1100
mV
PG Pull-Down Voltage
VOL_PG
IPG = 8mA
0.047
0.4
V
FLT Pull-Down Voltage (Note 3)
VOL_FLT
IFLT = 8mA
0.047
0.4
V
Soft-Start Charging Current
IQ_SS
VSS = 1V
10
µA
CHARGE PUMP
CPVDD
V_CPVDD
VBIAS = 3.3V
CPVDD
V_CPVDD
VBIAS = 3.3V
T = 25°C
External User Load = 6mA
6
4.9
5.2
5.0
5.5
V
V
FN9186.3
January 3, 2006
ISL6173
Typical Performance Curves (at 25°C unless otherwise specified)
2.045
12
2.04
10
POR RISING (V)
2.035
I_BIAS (mA)
8
6
4
2.03
2.025
2.02
2.015
2.01
2
0
2.005
CPQ = 22nF, CPVDD = 0.47µF
1.0
1.4
1.7
2.0
2.3
2.9
3.2
2
3.7
-10
0
FIGURE 3. I_BIAS vs V_BIAS
9
9
8
8
7
7
6
6
VGATE (V)
10
VGATE (V)
40
60
85
FIGURE 4. POR RISING THRESHOLD vs TEMPERATURE
10
5
4
3
5
4
3
2
2
CPQ = 22nF, CPVDD = 0.47µF
1
0
25
TEMPERATURE (°C)
V_BIAS(V)
CPQ = 0.1µF, CPVDD = 0.47µF
1
0
2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.5 3.7 3.8 3.9 4
2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.5 3.7 3.8 3.9 4
V_BIAS (v)
V_BIAS (V)
FIGURE 5. VGATE vs V_BIAS
FIGURE 6. VGATE vs V_BIAS
24.6
0.19
0.18
24.4
0.17
0.16
PG_VOL
IG (µA)
24.2
24
23.8
0.15
0.14
0.13
0.12
23.6
0.11
23.4
-10
0
25
40
TEMPERATURE (°C)
60
FIGURE 7. GATE DRIVE vs TEMPERATURE
7
85
0.1
IPG = 8mA
-10
0
25
40
60
85
TEMPERATURE (°C)
FIGURE 8. PG_VOL vs TEMPERATURE
FN9186.3
January 3, 2006
ISL6173
Typical Performance Curves (at 25°C unless otherwise specified)
(Continued)
3
RESPONSE TIME (µs)
1000
100
10
2.5
2
1.5
1
0.5
1
0
0.1
0.47
1
2
4
8.7
14
0
100
22
150
CG (nF)
200
250
300
OC (% OF LIMIT)
FIGURE 9. WOC RESPONSE vs LOAD CAPACITANCE
FIGURE 10. RESPONSE TIME vs IO*RSNS
2.008
2.006
POR FALLING (V)
TRESPONSE (ns)
10000
2.004
2.002
2
1.998
1.996
-10
0
25
40
60
85
TEMPERATURE (°C)
FIGURE 11. POR FALLING vs TEMPERATURE
8
FN9186.3
January 3, 2006
ISL6173
Detailed Description of Operation
Each of these modes is described in detail as follows:
ISL6173 targets dual voltage hot-swap applications with a
bias of 2.1V to 3.6VDC and the voltages being controlled
down to 0.7VDC. The IC’s main function is to limit and
regulate the inrush current into the loads. This is achieved by
enhancing an external MOSFET in a controlled manner. In
order to fully enhance the MOSFET, the IC must provide
adequate gate to source voltage, which is typically 5V or
greater. Hence, the final steady-state voltage on Gate (GT)
pin must be 5V above the load voltage. Two internal chargepumps allow this to happen.
1. Current Limit or Current Regulation (CR) Mode: - When
the load current reaches the current regulation threshold, the
current amplifier loop closes and the circuit behaves like a
current source. The Current Limit Amplifier is a folded
cascode type with source follower output capable of pulling
down the gate very fast in response to fast overload
transients. The current regulation threshold is set by setting a
reference current, ISET, through RSET by selecting an
appropriate resistor between OCREF and GND, which sets
IREF. The relationship between IREF and ISET is IREF =
4*ISET, where IREF = Vocref/Rocref = 1.178/Rocref. IREF
would typically be set at 80µA.
VIN
VO
Selecting appropriate values for RSET and RSNS such that
when IO = ICR,
GT1
VO1
Q
VIN
Vin
0
24µA
Iset
CPVDD
10µA
+
0
CURRENT REGULATION
MODE:
Iset*Rset = Io*Rsns
SS1
+
Q
Rsns
SNS1
-
+
Rset
-
Vo
-
+
VS1
SOFTSTART
AMPLIFIER
CPVDD
GT1
10V
42µA
(EQ. 1)
Io*RSNS = ISET*RSET
CURRENT 10V
LIMIT
AMPLIFIER
ISL6173
FIGURE 12. SOFT-START OPERATION
24µA
-
Controlled Soft-Start
+
3K
The output voltages are monitored through the Vo pins and
slew up at a rate determined by the capacitors on the Softstart (SS) pin, as illustrated in Figure 12. 24µA of gate
charge current is available. The soft-start amplifier controls
the output voltage by robbing some of the gate charge
current thus slowing down the MOSFET enhancement.
When the load voltage reaches its set level, as sensed by its
respective UV pin through an external resistor divider, the
Power Good (PG) output goes active.
Current Monitoring and Protection
The IC monitors the load current (Io) by sensing the voltagedrop across the low value current sense resistor (RSNS),
which is connected in series with the MOSFET as shown in
the diagram on page 2, through Sense (SNS) and voltage
set (VS) pins. The latter is through a resistor, RSET, as
shown. Two levels of overcurrent detection are available to
protect against all possible fault scenarios. These levels are:
1. Current Limit or Current Regulation (CR)
2. Way Overcurrent (WOC)
9
Iref
4
FIGURE 13. CURRENT REGULATION OPERATION
The operating mode is shown in Figure 13. When the circuit
enters this mode, the OC comparator detects it and sets off
the timer. CT begins to charge from an internal 10µA current
source. The amount of time it takes for this cap to charge to
1.178V sets up the current regulation duration. Upon
expiration of this time-out period, the MOSFET gate is pulled
down quickly by the current limit amplifier, unless the load
current level had already dropped back to a level below the
current regulation threshold level prior to that. In that case, the
current regulation mode is no longer active, the MOSFET is
allowed to fully enhance and the IC discharges the CT Cap. If
RTR/LTCH pin is left open or pulled to BIAS, the output
remains latched off after the expiration of the time-out period
determined by CT. If RTR/LTCH pin is pulled to GND, the IC
FN9186.3
January 3, 2006
ISL6173
automatically retries to turn on the MOSFET after a wait
period, during which CT is charged and discharged 64 times
and the retry attempt takes place on the 65th time. This wait
period allows the MOSFET junction to cool down.
2. Way Overcurrent (WOC) Mode - This mode is designed
to handle very fast, very low impedance shorts on the load
side, which can result in very high di/dt. Typically, the current
limit set for this mode is 300% of the current regulation limit.
This mode uses a very fast comparator, which directly looks
at the voltage drop across RSNS and pulls the gate very
quickly to GND (as shown in Figure 14) and immediately
releases it. If the WOC is still present, the IC enters current
regulation mode and the rest of the current regulation
behavior follows as described earlier in undercurrent
regulation mode.
Io
+
Iset Rset
-
Vo
-
+
Q
GATE
PULLDOWN
CURRENT
ISL6173
WOC
COMPARATOR
3K
Retry vs Latched Fault Operational Modes:
RTR/LTCH pin dictates the IC behavior after the gate (GT)
pin pulls down following OC timeout expiration. If the
RTR/LTCH pin is left floating, the gate pin will remain latched
off. It can only be released by de-asserting and reasserting
the enable (EN) input. If RTR/LTCH pin is pulled to GND,
then the Retry mode will be activated. In this mode the IC will
automatically attempt to turn-on the MOSFET after a delay,
determined by the capacitor on CT pin. In the Retry mode,
the internal logic charges and discharges the CT cap 64
times during “wait” period. On the 65th time, the FLT output
clears during retry attempt. If the overcurrent condition
persists after the soft-start, the CT pin will again start
charging and the process repeats.
Bias and Charge Pump Voltages:
SNS1
VS1
Rsns
GT1
Vin
on this pin reaches 1.178V, the CR duration expires. Fault
(FLT) pin goes active (pulls low), signaling the load of a fault
condition and the gate (GT) pin gets pulled low.
+
25Ω
The BIAS pin feeds the chip bias voltage directly to the first
of the two internal charge pumps, which are cascaded. The
output of the first charge pump, in addition to feeding the
second charge pump, is accessible on the CPVDD pin. The
voltage on the CPVDD pin is approximately 5V. It also
provides power to the POR and band-gap circuitry as shown
in the block diagram. A capacitor connected externally
across CPQ+ and CPQ- pins of the IC is the “flying” cap for
the charge-pump.
The second charge-pump is used exclusively to drive the
gates of the MOSFETs through the 24µA current sources,
one for each channel. The output of this charge pump is
approximately 10V as shown in the block diagram.
Tracking
FIGURE 14. WOC OPERATION
Additionally, as shown in the block diagram, there is also an
“OC comparator”, which also looks at the Rsense voltage
drop. When this drop exceeds the Current Limit set point, it
triggers the timeout circuit, which starts ticking and CTx is
allowed to charge. If the current limit condition remains in
effect until after the time-out period expires (CTx voltage
exceeding 1.178V), the gate of the MOSFET is pulled down,
the SSx capacitor is discharged, FLT is asserted and a new
SS sequence is allowed to begin after ENx recycle or by
keeping the RTR/LTCH pin pulled low.
The voltage on OCREF pin is the same as the internal bandgap reference voltage, which is 1.178V (nominal). A resistor
to GND from this pin sets the reference current (and hence
the reference voltage) for the current limit amplifier and
OC/WOC comparators. The current regulation (CR) duration
is set by the capacitor on CT pin to GND. Once the voltage
10
CH1: VO1, CH2: VO2, T = 2ms/DIV, CSS = 0.066µF
FIGURE 15. TRACKING MODE WAVEFORMS
FN9186.3
January 3, 2006
ISL6173
The two channels can be forced to track each other by
simply tying their SS pins together and using a common SS
capacitor. In addition, their EN pins also must be tied
together. Typical Start-up waveforms in this mode are shown
in Figure 15. If one channel goes down for any reason, the
other one will too. One important thing to note here is that
only the overcurrent latch-off mode will work. Auto-retry
feature WILL NOT work. Retry must be controlled manually
through EN.
Typical Hot-plug Power Up Sequence
1. When power is applied to the IC on the BIAS pin, the first
charge pump immediately powers up.
2. If the BIAS voltage is 2.1V or higher, the IC comes out of
POR. Both SS and CT caps remain discharged and the
gate (GT) voltage remains low.
same rate as the SS cap voltage. This is tightly controlled
by the soft-start amplifier shown in the block diagram.
5. SS cap begins to charge but the corresponding CTx cap
is held discharged.
6. Fault (FLT) remains deasserted (stays high) and the
output voltage continues to rise.
7. If the load current on the output exceeds the set current
limit for greater than the OC timeout period, FLT gets
asserted and the channel shutdown occurs.
8. If the voltage on UV pin exceeds 633mV threshold as a
result of rising Vo, the Power Good (PG) output goes
active.
9. At the end of the SS interval, the SS cap voltage reaches
CPVDD and remains charged as long as EN remains
asserted or there is no other fault condition present that
would attempt to pull down the gate.
3. ENx pin, when pulled low (below it’s specified threshold),
enables the respective channel.
State Diagram
4. SSx cap begins to charge up through the internal 10µA
current source, the gate (GT) voltage begins to rise and
the corresponding output voltage begins to rise at the
This is shown in Figure 16. It provides a quick overview of
the IC operation and can also be used as a troubleshooting
road map.
11
FN9186.3
January 3, 2006
ISL6173
IC Operation State Diagram
No
Pow er
Apply Pow er
Bias>1V
PG
&
FLT
Outputs
Valid
Bias>2V
FLT
Cleared
EN De-asserted
EN Asserted
Gate
Pulldow n
Soft Start
(Tss)
Io>>ICR
(WOC)
Io>ICR
Count 64
Pulses
&
Reset
Current
Limit
Mode
Output
Voltage
Available
Io>ICR
RTR/LTCH = L
Run
OC Timer
(Toc)
Vuv<633mV Vuv>645mV
Reset &
Latch
Off
State
Io>=Icr
AND
t>Toc
FLT
Asserted
RTR/LTCH = H
PG
Asserted
FIGURE 16.
12
FN9186.3
January 3, 2006
ISL6173
Applications Information
Current Set Resistor (RSET)
Selection of External Components
The typical application circuit of Figure 2 has been used for
this section, which provides guidelines to select the external
component values.
MOSFET (Q1)
This resistor directly sets the threshold for the current
regulation amplifier and indirectly sets the same for the OC
and WOC comparators in conjunction with RSNS. Once
RSNS has been selected, use Equation 1 (on page 9) to
calculate RSET. Use 20µA for ISET in a typical application.
Reference Current Set Resistor (RREF)
This component should be selected on the basis of its
rDS(ON) specification at the expected Vgs (gate to source
voltage) and the effective input gate capacitance (Ciss). One
needs to ensure that the combined voltage drop across the
Rsense and rDS(ON) at the desired maximum current
(including transients) will still keep the output voltage above
the minimum required level. Power dissipation in the device
under short circuit condition should also be an important
consideration especially in auto-retry mode (RTR/LTCH pin
pulled low). Using ISL6173 in latched off mode results in
lower power dissipation in the MOSFET.
This resistor sets up the current in the internal current
source, IREF/4, shown in Figure 2 for the comparators. The
voltage at the OCREF pin is the same as the internal
bandgap reference. The current (IREF) flowing through this
resistor is simply:
Ciss of the MOSFET influences the overcurrent response
time. It is recommended that a MOSFET with Ciss of less
than 10nF be chosen. Ciss will also have an impact on the
SS cap value selection as seen later.
Selection of Rs1 and Rs2
Current Sense Resistor (RSNS)
The voltage drop across this resistor, which represents the
load current (Io), is compared against the set threshold of
the current regulation amplifier. The value of this resistor is
determined by how much combined voltage drop is tolerable
between the source and the load. It is recommended that at
least 20mV drop be allowed across this resistor at max load
current. This resistor is expected to carry maximum full load
current indefinitely. Hence, the power rating of this resistor
must be greater than IO(MAX)2*RSNS.
This resistor is typically a low value resistor and hence the
voltage signal appearing across it is also small. In order to
maintain high current sense accuracy, current sense trace
routing is critical. It is recommended that either a four wire
resistor or the following routing method be used:
LOAD CURRENT CARRYING
TRACES
CURRENT
SENSE
TRACES
RSNS
FIGURE 17. RECOMMENDED CURRENT SENSE RESISTOR
PCB LAYOUT
13
IREF = 1.178/RREF
This current, IREF, should be set at 80µA to force 20µA in the
internal current source as shown in Figure 2, because of the
4:1 current mirror. This equates to the resistor value of
14.7K.
These resistors set the UV detect point. The UV comparator
detects the undervoltage condition when it sees the voltage
at UV pin drop below 0.633V. The resistor divider values
should be selected accordingly.
Charge Pump Capacitor Selection (CP and CV)
CP is the “flying cap” and CV is the smoothing cap of the
charge pump, which operates at 450kHz set internally. The
output resistance of the charge pump, which affects the
regulation, is dependent on the CP value and its ESR,
charge-pump switch resistance, and the frequency and ESR
of the smoothing cap, CV.
It is recommended that CP be kept within 0.022µF
(minimum) to 0.1µF (maximum) range. Only ceramic
capacitors are recommended. Use 0.1µF cap if CPVDD
output is expected to power an external circuit, in which case
the current draw from CPVDD must be kept below 10mA.
CV should at least be 0.47µF (ceramic only). Higher values
may be used if low ripple performance is desired.
Time-out Capacitor Selection (CT)
This capacitor controls the current regulation time-out
period. As shown in Figure 2, when the voltage across this
capacitor exceeds 1.178V, the time-out comparator detects it
and pulls down the gate voltage thus shutting down the
channel. An internal 10µA current source charges this
capacitor. Hence, the value of this capacitor is determined by
the following equation:
CT = (10µA * TOUT)/1.178
Where,
TOUT = Desired time-out period.
FN9186.3
January 3, 2006
ISL6173
Soft-Start Capacitor Selection (CSS)
The rate of change of voltage (dv/dt) on this capacitor, which
is determined by the internal 10µA current source, is the
same as that on the output load capacitance. Hence, the
value of this capacitor directly controls the inrush current
amplitude during hot swap operation.
CSS = CO*(10µA/IINRUSH)
Where,
CO = Load Capacitance
IINRUSH = Desired Inrush Current
IINRUSH is the sum of the dc steady-state load current and
the load capacitance charging current. If the dc steady-state
load remains disabled until after the soft-start period expires
(PGx could be used as a load enable signal, for example),
then only the capacitor charging current should be used as
IINRUSH. The Css value should always be more than (1/2.4)
of that of Ciss of the MOSFET to ensure proper soft-start
operation. This is because the Ciss is charged from 24µA
current source whereas the Css gets charged from a 10µA
current source (please refer to Figure 12). In order to make
sure both Vss and Vo track during the soft-start, this
condition is necessary.
ISL6173 Evaluation Platform
The ISL6173EVAL1 is the primary evaluation board for this
IC. The board is a standalone evaluation platform and it only
needs input bias and test voltages. The schematic for this
board is shown in Figures 20 and 21. The component
placement diagram is shown in Figure 22.
The evaluation board has been designed with a typical
application and accessibility to all the features in mind to
enable a user to understand and verify these features of the
IC. The circuit is designed for 2A for each input rail but it can
easily be scaled up or down by adjusting some component
values. LED indicators are provided to indicate Fault and
Power Good status. Switches are there to perform Enable
function for each channel, to select auto-retry or latchoff
mode and to check WOC and CR modes.
There are two input voltages, one for each channel plus
there is “+5V” input. The latter is to test the pull-up capability
of FLT and PG outputs to +5V and also to power the LEDs
and the dynamic load circuitry. ISL6173 does not require 5V.
The outputs are brought out to banana sockets to allow
external loading if desired.
J1 and J3 are wire jumpers. A user can replace them with
wire loops to attach a scope current probe. However, doing
so may reduce the di/dt enough to prevent WOC comparator
from tripping. The internal current regulation amplifier is fast
enough to respond to very fast di/dt. Hence, it is advisable to
use the on board dynamic load circuitry, as will be described,
if a user wants to check the WOC performance.
The dynamic load circuitry, shown in Figure 21, is included
on the board on both channels to ensure minimum
inductance in the current flow path. Two sets of load are
available per output:
1) CR Load: This load is set at 1Ω (approximately 3.3A for
3.3V output), which is higher than the 2.2A of CR limit but
less than WOC limit (6.6A) set on the board.
2) WOC Load: This load is set at 340mΩ, which is roughly
10A for 3.3V supply. This is higher than 6.6A WOC limit set
on the board.
A function/pulse generator is required to activate the
dynamic load circuitry. The function/pulse generator should
have adjustable pulse-width (3ms), single pulse (manual
trigger) and 5V pulse amplitude capability. Agilent model
No: 33220A or equivalent is a good choice. The function
generator needs to be connected through a co-ax cable to
J11 or J12 for channel 1 or channel 2 respectively. WOC or
CR load can be activated by turning SW4 or SW5 (channel
1) and SW6 or SW7 (channel 2) ON followed by applying the
pulse generator to turn on an appropriate load.
The load circuit consists of a MOSFET driver (EL7202),
MOSFET (IRF7821) and surface mount load resistors. The
MOSFET drivers, U2 and U3, respond to a pulse from the
generator to turn on the MOSFET for the duration of the
pulse, which should be set less than the timeout period
described in “Time-out Capacitor Selection”. On this board
the timeout capacitor value is 0.15µF, which corresponds to
a timeout period of 17.67ms.
One way to tell if the WOC mode is active would be by
looking at the Gate waveform of the control MOSFET (M1 or
M2). The WOC comparator when tripped, pulls down the
Gate hard. The following waveform shows WOC operation:
Pins SS1 and SS2 of the IC are available on header J2 as
test points so that they can be tied together to achieve
tracking between Vo1 and Vo2. Both the Enable (EN)
switches (SW1 and SW2) must be turned ON to check this
function.
Each channel is preloaded with capacitive load. Extra load
can be externally applied as required.
14
FN9186.3
January 3, 2006
ISL6173
FIGURE 18. WOC OPERATION
Channel 1 is Vgate, Channel 2 is the pulse generator output
and Channel 3 is Vout. Note how Vgate gets immediately
pulled down to zero volts up on load application.
In CR mode, however, Vgate always remains above zero
volts because WOC comparator never trips. This can be
seen on the following scope shot:
FIGURE 19. CURRENT REGULATION OPERATION
It is also important to note that in WOC mode, although
Vgate gets pulled down to zero initially, the gate is quickly
released and slowly rises until the CR amplifier takes control.
15
FN9186.3
January 3, 2006
ISL6173
Bill of Materials for ISL6173 Eval 1 Board
ITEM
QTY
REFERENCE
PART
PKG
MFG P/N
1
2
C1, C18
220µF
Leaded
UPM1E221MPH6 or eq
Nichicon
2
2
C2, C17
47µF
Leaded
UPM1E470MEH or eq
Nichicon
3
2
C3, C4
0.1µF
0805
Any
4
2
C5, C6
1000pF
0805
Any
5
2
C9, C10
0.033µF
0805
Any
6
2
C11, C12
0.15µF
0805
Any
7
1
C13
0.47µF
0805
Any
8
1
C14
2.2µF
1206
Any
9
2
C19, C20
0.01µF
0805
Any
10
1
C21
10µF
7343
Any
11
1
C22
0.022µF
0805
Any
12
2
D1, D6
MBR130P
SMA
MBR130P
ON Semi
13
2
D3, D4
LED GRN
1206
PG1101W
Stanley
14
2
D2, D5
LED RED
1206
BR1101W
Stanley
15
1
J2
2 Pin Header
Any
16
2
J1, J3
Jumper
Any
17
2
J11, J12
BNC Jack
18
6
M1, M2, M3, M4, M5, M6
IRF7821
SO8
19
10
RS1, RS2, R10, R12, R30, R31
1K
0805
Any
IRF7821
MANUFACTURER
International
Rectifier
R55, R56, R57, R58
20
6
R1, R27, R49, R50, R51, R52
0.01
2512
Any
21
4
R2, R3, R25, R26
390
0805
Any
22
1
R8
3.57K
0805
Any
23
1
R9
2.55K
0805
Any
24
1
R11
14.7K
0805
Any
25
3
R14, R15, R20
0
0805
Any
26
4
R16, R17, R18, R19
10K
0805
Any
27
2
R29, R32
1.1K
0805
Any
28
4
R33, R34, R35, R36
10
0805
Any
29
6
R37, R38, R42, R43, R44, R45
1
2512
Any
30
10
R39, R40, R41, R46, R47, R48
5
2512
Any
R61, R62, R63, R64
31
2
R53, R54
100
1206
Any
32
2
R59, R60
49.9
0805
Any
34
1
U1
ISL6173
QFN28 5x5
35
2
U2, U3
EL7202/SO
SO8
38
7
SW5, SW6, SW7, SW8, SW9,
SW10, SW11
Toggle Switch
16
ISL6172
Intersil
Intersil
GT11MCKE
C&K
FN9186.3
January 3, 2006
1
20
SNS2 GT2 VO2
C12
0.15µF
R15
C6
0
1000pF
TP16
NO STUFF
R19
10K
R18
10K
R3
390
D2
FLT1
LED55B/TO
D3
LED55B/TO
TP7
1
GND_OUT
J9
1
TP13
TP17 TP18
1
1
R11
14.7K
1
1
TP3
R31
1K
TP8
R32
1.1K
R16
10K
D4
PG2
LED55B/TO
D5
FLT2
LED55B/TO
J2
CON2
R25
390
R26
390
5V
1
R12 R9
1K 2.55K
TP14
1
2
CT2 VS2
R17
10K
D1
MBR130P
5V
1
4
1
1
C10
0.033µF
1
7
1K
OCREF 25
29
GND1
PG2 16
CON2
J3
TP15
J10
C17
47µF
VO2
1
1
R27
0.01
4
1
2
1
R30
FLT2 17
C9
19
SS2
0.033µF
UV2 23
GND
CT1
1
1
TP10
Vi_2
ISL6173
PGND
C11
0.15µF
R8
3.57K
2.5V
M2
IRF7821
5
6
7
8
R54
100
1
2
3
9
C18
220µF
28
1
1
10
27
R2
390
C21
10µF
TP4
PG1 6
FLT1 5
3
SS1
U1
11 CPQ-
2
18
C13
0.47µF
TP9
Vi_2
J7
UV1
13 CPQ+
1
CLOSE = Retry
SNS1 GT1 VO1
14 CPVDD
OPEN = Latch
GND_IN
J6
VS1
21
1
C14
2.2µF
8 RTR/LTCH
12 BIAS
R14
0
R53
100
ISL6173
OPEN = Disable
CLOSE = Enable
C22
0.022µF
EN1 EN2
22
1
SW3
TP12
C19
0.01µF
C2
47µF
5V
R10
1K
15
TP11
1
SW1 SW2
RS1
1K
R20
0
24
5V
J5
C3
0.1µF
26
C4
0.1µF
R29
1.1K C5
1000pF
C20
0.01µF NO STUFF
TP5
TP6
RS2
1K
VO1
1
4
1
2
TP1
J1
CON2
VO1
1
R1
0.01
1
17
C1
220µF
5V
J8
TP2
Vi_1
3.3V
Vi_1
5
6
7
8
M1
IRF7821
J4
1
2
3
Schematic, ISL6173 Eval1
FN9186.3
January 3, 2006
FIGURE 20.
D6
MBR130P
VO2
Schematic, ISL6173 Eval1 (Continued)
VO1
TP27
TP28
1
1
R38
1
R37
1
R64
5
R42
1
R63
5
R40
5
R39
5
R41
5 TP29
TP30
TP31
1
M3
IRF7821
1
18
2
SW4
R59
49.9
3
J11
4
R33
4
5
6
7
8
1
2
3
10
R55
1K
1
1
SW5
M4
IRF7821
R34
TP26
4
1
1
2
3
10
R49
01
U2
1
2
3
4
5
6
7
8
TP25
1
R56
1K
R50
01
5V
8
7
6
5
ISL6173
NC1
NC8
IN2 OUTA
GND
V+
IN2_ OUTB
EL7202/SO
VO2
TP19
TP24
1
R44
1
SW6
1
1
M5
IRF7821
2
1
TP34
1
TP35
1
TP36
1
TP33
3
J12
R35
R60
49.9
R62
5
SW7
R45
1 TP20
R61
5
R47
5
R46
5
R48
5
TP23
1
TP32
4
R43
1
1
4
10
R57
1K
5
6
7
8
M6
IRF7821
1
2
3
R36
4
10
TP21
R58
1K
1
1
2
3
TP22
1
R52
01
R51
01
U3
1
2
3
4
FN9186.3
January 3, 2006
NC1
NC8
IN2 OUTA
GND
V+
IN2_ OUTB
EL7202/SO
FIGURE 21.
1
5
6
7
8
5V
8
7
6
5
ISL6173 Eval 1 - Component Layout
19
ISL6173
FN9186.3
January 3, 2006
FIGURE 22.
ISL6173
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
2X
L28.5x5
28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VHHD-1 ISSUE I)
0.15 C A
MILLIMETERS
D
A
9
D/2
D1
D1/2
2X
N
6
INDEX
AREA
0.15 C B
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
0.80
0.90
1.00
-
A1
-
0.02
0.05
-
A2
-
0.65
1.00
9
0.30
5,8
A3
1
2
3
E1/2
E/2
E1
b
E
9
0.15 C B
2X
0.15 C A
5.00 BSC
-
4.75 BSC
9
E2
A2
A
A1
A3
SIDE VIEW
(DATUM B)
4.75 BSC
2.95
3.10
9
3.25
7,8
0.08 C
-
-
-
L
0.50
0.60
0.75
8
9
NX k
D2
2 N
-
0.20
8
7
0.50 BSC
-
N
28
2
Nd
7
3
Ne
7
3
P
-
-
0.60
9
θ
-
-
12
9
Rev. 1 11/04
4X P
1
(DATUM A)
NOTES:
2
3
6
INDEX
AREA
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
(Ne-1)Xe
REF.
E2
2. N is the number of terminals.
7
3. Nd and Ne refer to the number of terminals on each D and E.
E2/2
NX L
N e
8
8
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
9
CORNER
OPTION 4X
(Nd-1)Xe
REF.
BOTTOM VIEW
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
A1
NX b
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
5
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
SECTION "C-C"
C
L
7,8
k
0.10 M C A B
D2
3.25
e
5
NX b
4X P
3.10
5.00 BSC
/ / 0.10 C
C
SEATING PLANE
2.95
E1
0
4X
9
D
E
B
TOP VIEW
0.25
D1
D2
2X
0.20 REF
0.18
C
L
L1
10
L
L1
e
10
L
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
e
C C
TERMINAL TIP
FOR ODD TERMINAL/SIDE
FOR EVEN TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
20
FN9186.3
January 3, 2006
Similar pages