DATASHEET

DATASHEET
ZVS Full Bridge PWM Controller
ISL6551
Features
The ISL6551 is a zero voltage switching (ZVS) full-bridge PWM
controller designed for isolated power systems. This part
implements a unique control algorithm for fixed-frequency ZVS
current mode control, yielding high efficiency with low EMI. The
two lower drivers are PWM controlled on the trailing edge and
employ resonant delay while the two upper drivers are driven
at a fixed 50% duty cycle.
• High speed PWM (up to 1MHz) for ZVS full bridge control
This IC integrates many features in 28 Ld SOIC package to
yield a complete and sophisticated power supply solution.
Control features include programmable soft-start for
controlled start-up, programmable resonant delay for zero
voltage switching, programmable leading edge blanking to
prevent false triggering of the PWM comparator due to the
leading edge spike of the current ramp, adjustable ramp for
slope compensation, drive signals for implementing
synchronous rectification in high output current, ultra high
efficiency applications and current share support for
paralleling up to 10 units, which helps achieve higher reliability
and availability as well as better thermal management.
Protective features include adjustable cycle-by-cycle peak
current limiting for overcurrent protection, fast short-circuit
protection (in hiccup mode), a latching shutdown input to turn
off the IC completely on output overvoltage conditions or other
extreme and undesirable faults, a non-latching enable input to
accept an enable command when monitoring the input voltage
and thermal condition of a converter and VDD undervoltage
lockout with hysteresis. Additionally, the ISL6551 includes
high current high-side and low-side totem-pole drivers to avoid
additional external drivers for moderate gate capacitance (up
to 1.6nF at 1MHz) applications, an uncommitted high
bandwidth (10MHz) error amplifier for feedback loop
compensation, a precision bandgap reference with ±1.5%
(ISL6551AB) or ±1% (ISL6551IB) tolerance across
recommended operating conditions and a ±5% “in regulation”
monitor.
In addition to the ISL6551, other external elements such as
transformers, pulse transformers, capacitors, inductors and
Schottky or synchronous rectifiers are required for a complete
power supply solution. A detailed 200W telecom power supply
reference design using the ISL6551 with companion Intersil
ICs, Supervisor and Monitor ISL6550, and Half-bridge Driver
HIP2100, is presented in application note AN1002.
• Current mode control compatible
• High current high-side and low-side totem-pole drivers
• Adjustable resonant delay for ZVS
• 10MHz error amplifier bandwidth
• Programmable soft-start
• Precision bandgap reference
• Latching shutdown input
• Non-latching enable input
• Adjustable leading edge blanking
• Adjustable dead time control
• Adjustable ramp for slope compensation
• Fast short-circuit protection (hiccup mode)
• Adjustable cycle-by-cycle peak current limiting
• Drive signals to implement synchronous rectification
• VDD undervoltage lockout
• Current share support
• ±5% “in regulation” indication
• Pb-free (RoHS compliant)
Applications
• Full-bridge and push-pull converters
• Power supplies for off-line and Telecom/Datacom
• Power supplies for high end microprocessors and servers
Related Literature
• AN1002, 200W, 470kHz, Telecom Power Supply Using
ISL6551 Full-Bridge Controller and ISL6550 Supervisor and
Monitor.
In addition, the ISL6551 can also be designed in push-pull
converters using all of the features except the two upper
drivers and adjustable resonant delay features.
October 28, 2015
FN9066.7
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2003-2006, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL6551
Table of Contents
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Drive Signals Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Timing Diagram Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Shutdown Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Shutdown Timing Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Block/Pin Functional Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Additional Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
System Blocks Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Current Sense. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Primary FETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Feedback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Rectifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Main Transformers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Supervisor Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Output Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Primary FET Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Full Bridge Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Simplified Typical Application Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Small Outline Plastic Packages (SOIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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FN9066.7
October 28, 2015
ISL6551
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
ISL6551IBZ
ISL6551IBZ
0 to +85
28 Ld SOIC
M28.3
ISL6551ABZ
(No longer available, recommended
replacement: ISL6551IBZ, ISL6551IBZ-T)
ISL6551ABZ
-40 to +105
28 Ld SOIC
M28.3
NOTES:
1. Add “-T” suffix for tape and reel.
2. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for ISL6551. For more information on MSL, please see tech brief TB363.
Pin Configuration
ISL6551
28 LD (SOIC)
TOP VIEW
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3
VSS
1
28
VDD
CT
2
27
VDDP1
RD
3
26
VDDP2
R_RESDLY
4
25
PGND
R_RA
5
24
UPPER1
ISENSE
6
23
UPPER2
PKILIM
7
22
LOWER1
BGREF
8
21
LOWER2
R_LEB
9
20
SYNC1
CS_COMP 10
19
SYNC2
CSS 11
18
ON/OFF
EANI 12
17
DCOK
EAI 13
16
LATSD
EAO 14
15
SHARE
FN9066.7
October 28, 2015
ISL6551
Functional Pin Description
PIN #
PIN NAME
DESCRIPTION
1
VSS
Reference ground. All control circuits are referenced to this pin.
2
CT
Set the oscillator frequency, up to 1MHz.
3
RD
Adjust the clock dead time from 50ns to 1000ns.
4
R_RESDLY
Program the resonant delay from 50ns to 500ns.
5
R_RA
Adjust the ramp for slope compensation (from 50mV to 250mV).
6
ISENSE
The pin receives the current information via a current sense transformer or a power resistor.
7
PKILIM
Set the overcurrent limit with the bandgap reference as the trip threshold.
8
BGREF
Precision bandgap reference, 1.263V ±2% overall recommended operating conditions.
9
R_LEB
Program the leading edge blanking from 50ns to 300ns.
10
CS_COMP
Set a low current sharing loop bandwidth with a capacitor.
11
CSS
Program the rise time and the clamping voltage with a capacitor and a resistor, respectively.
12
EANI
Noninverting input of Error Amp. It is clamped by the voltage at the CSS pin (Vclamp).
13
EAI
Inverting input of error amp. It receives the feedback voltage.
14
EAO
Output of error amp. It is clamped by the voltage at the CSS pin (Vclamp).
15
SHARE
This pin is the SHARE BUS connecting with other unit(s) for current share operation.
16
LATSD
The IC is latched off with a voltage greater than 3V at this pin and is reset by recycling VDD.
17
DCOK
Power-good indication with a ±5% window.
18
ON/OFF
This is an Enable pin that controls the states of all drive signals and the soft-start.
19, 20
SYNC2, SYNC1
These are the gate control signals for the output synchronous rectifiers.
21, 22
LOWER2, LOWER1
Both lower drivers are PWM controlled on the trailing edge.
UPPER2, UPPER1
Both upper drivers are driven at a fixed 50% duty cycle.
PGND
Power ground. High current return paths for both the upper and the lower drivers.
23, 24
25
26, 27
28
VDDP2, VDDP1
Power is delivered to both the upper and the lower drivers through these pins.
VDD
Power is delivered to all control circuits including SYNC1 and SYNC2 via this pin.
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FN9066.7
October 28, 2015
ISL6551
BANDGAP
REFERENCE
BGREF
11 CSS
16 LATSD
28 VDD
18 ON/OFF
Functional Block Diagram
SHUTDOWN
SHUTDOWN
LATCH
LATCH
UVLO
SOFT
SOFTSTART
START
8
PKILIM 7
SHUTDOWN
SHUTDOWN
27 VDDP1
UPPER1
DRIVER
24 UPPER1
R_LEB 9
R_RESDLY 4
RESODLY
UPPER2
DRIVER
LEB
ISENSE 6
RAMP
ADJUST
R_RA 5
CT 2
RD 3
23 UPPER2
26 VDDP2
CLOCK
GENERATOR
EAO 14
EAI 13
EANI 12
PWM
LOGIC
ERROR AMP
Figure 7
22 LOWER1
LOWER2
DRIVER
21 LOWER2
CURRENT
SHARE
DC OK
25 PGND
20 SYNC1
19 SYNC2
15 SHARE
VSS
10 CS_COMP
1
17 DCOK
CIRCUITS REFERENCED TO VSS
LOWER1
DRIVER
CIRCUITS REFERENCED TO PGND
EXTERNAL SINGLE POINT CONNECTION REQUIRED
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM
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FN9066.7
October 28, 2015
ISL6551
Absolute Maximum Ratings
Thermal Information
Supply Voltage VDD, VDDP1, VDDP2 . . . . . . . . . . . . . . . . . . . . . . -0.3 to 16V
Enable Inputs (ON/OFF, LATSD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD
Power Good Sink Current (IDCOK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . . . . . . . 3kV
Machine Model (Per EIAJ ED-4701 Method C-111) . . . . . . . . . . . . . 250V
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
SOIC Package (Note 4) . . . . . . . . . . . . . . . .
55
N/A
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Ambient Temperature Range
ISL6551IB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +85°C
ISL6551AB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C
Supply Voltage Range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . .10.8V to 13.2V
Supply Voltage Range, VDDP1 and VDDP2. . . . . . . . . . . . . . . . . . . . <13.2V
Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . . +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTE:
4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
(ISL6551AB), Unless Otherwise Stated.
PARAMETER
These specifications apply for VDD = VDDP = 12V and TA = 0°C to +85°C (ISL6551IB) or -40°C to +105°C
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
10.8
12.0
13.2
V
13
18
mA
20
mA
SUPPLY (VDD, VDDP1, VDDP2)
Supply Voltage
VDD
Bias Current from VDD (ISL6551IB)
IDD
VDD = 12V (not including drivers current at VDDP)
5
Bias Current from VDD (ISL6551AB)
IDD
VDD = 12V (not including drivers current at VDDP)
3
Total Current from VDD and VDDP
ICC
VDD = VDDP = 12V, F = 1MHz, 1.6nF Load
60
mA
UNDER VOLTAGE LOCKOUT (UVLO)
Start Threshold (ISL6551IB)
VDDON
9.2
Start Threshold (ISL6551AB)
VDDON
9.16
Stop Threshold (ISL6551IB)
VDDOFF
8.03
Stop Threshold (ISL6551AB)
VDDOFF
7.98
9.6
8.6
1
9.9
V
9.94
V
8.87
V
8.92
V
Hysteresis (ISL6551IB)
VDDHYS
0.3
1.9
V
Hysteresis (ISL6551AB)
VDDHYS
0.27
1.93
V
CLOCK GENERATOR (CT, RD)
Frequency Range
Dead Time Pulse Width (Note 5)
F
VDD = 12V (Figure 5)
100
1000
kHz
DT
VDD = 12V (Figure 6)
50
1000
ns
BANDGAP REFERENCE (BGREF)
Bandgap Reference Voltage
(ISL6551IB)
VREF
VDD = 12V, 399kΩ pull-up, 0.1µF, after trimming
1.250
1.263
1.280
V
Bandgap Reference Voltage
(ISL6551AB)
VREF
VDD = 12V, 399kΩ pull-up, 0.1µF, after trimming
1.244
1.263
1.287
V
Bandgap Reference Output Current
IREF
VDD = 12V, see Block/Pin Functional Descriptions for
details
100
µA
PWM DELAYS (Note 5)
LOW1, 2 delay “Rising”
LOWR
With respect to RESDLY rising
5
ns
LOW1, 2 delay “Falling”
LOWF
Compare Delay at Verror = Vramp
44
ns
SYNC1, 2 delay “Falling”
SYNCF
With respect to RESDLY falling and with 20pF load
18
ns
SYNC1,2 delay “Rising”
SYNCR
With respect to CLK rising and with 20pF load
20
ns
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FN9066.7
October 28, 2015
ISL6551
Electrical Specifications These specifications apply for VDD = VDDP = 12V and TA = 0°C to +85°C (ISL6551IB) or -40°C to +105°C
(ISL6551AB), Unless Otherwise Stated. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ERROR AMPLIFIER (EANI, EAI, EAO) (Note 5)
Unity Gain Bandwidth
DC Gain
UGBW
10
MHz
DCG
79
dB
Maximum Offset Error Voltage
Vos
Input Common Mode Range
Vcm
Common Mode Rejection Ratio
CMMR
Power Supply Rejection Ratio
PSSR
Maximum Output Source Current
VDD = 12V
1mA load
ISRC
Maximum Lower Saturation Voltage
Vsatlow
0.4
3.1
mV
9
V
82
dB
95
dB
2
mA
Sinking 0.27mA
125
mV
1000
kHz
RAMP ADJUST (R_RA) (Note 5)
Ramp Frequency
F
Linear Voltage Ramp, Minimum
100
50
mV
Linear Voltage Ramp, Maximum
LVR
250
mV
Overall Variation
25
%
PEAK CURRENT LIMIT (PKILIM)
Peak Current Shutdown Threshold
IpkThr
Peak Current Shutdown Delay (Note 5)
IpkDel
BGREF = 0.1µF, 399kΩ pull-up
1.25
1.263
1.31
75
V
ns
SOFT-START (CSS)
Charge Current
Iss
Discharge Current
Vcss = 0.6V
8
12
µA
Idis
1.6
5.2
mA
Cycle-by-cycle Current Limit
(ISL6551IB)
Vclamp
2
8
V
Cycle-by-cycle Current Limit
(ISL6551AB)
Vclamp
1.9
8.1
V
DRIVERS (UPPER1, UPPER2, LOWER1, LOWER2)
Maximum Capacitive Load (each)
CL
VDD = VDDP = 12V, F = 1MHz,
Thermal Dependence
1600
pF
Turn-on Rise Time (ISL6551IB)
tr
1.0nF Capacitive load
8.9
16
ns
Turn-on Rise Time (ISL6551AB)
tr
1.0nF Capacitive load
9.2
17
ns
Turn-off Fall Time (ISL6551IB)
tf
1.0nF Capacitive load
6.4
Turn-off Fall Time (ISL6551AB)
tf
1.0nF Capacitive load
Shutdown Delay (Note 5)
tSD
1.0nF Capacitive load
14.5
ns
Rising Edge Delay (Note 5)
tRD
1.0nF Capacitive load
16.4
ns
1.0nF Capacitive load
13.7
Falling Edge Delay (Note 5)
tFD
Vsat_sourcing
Vsat_high
Sourcing 20mA
Vsat_sinking (ISL6551IB)
Vsat_low
Vsat_sinking (ISL6551AB)
Vsat_low
Sinking 200mA
10
ns
12
ns
ns
1.00
V
Sourcing 200mA
1.35
V
Sinking 20mA
0.035
V
Sinking 200mA
0.31
V
Sinking 20mA
0.04
V
0.5
V
SYNCHRONOUS SIGNALS (SYNC1, SYNC2)
Maximum capacitive load (each)
VDD = 12, F = 1MHz
20
(Figure 10)
50
pF
PROGRAMMABLE DELAYS (RESDLY, LEB) (Note 5)
Resonant Delay Adjust Range
Resonant Delay
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tRESDLY
7
500
ns
R_RESDLY = 10k
55
ns
R_RESDLY = 120k
488
ns
FN9066.7
October 28, 2015
ISL6551
Electrical Specifications These specifications apply for VDD = VDDP = 12V and TA = 0°C to +85°C (ISL6551IB) or -40°C to +105°C
(ISL6551AB), Unless Otherwise Stated. (Continued)
PARAMETER
SYMBOL
Leading Edge Blanking Adjust Range
Leading Edge Blanking
TEST CONDITIONS
(Figure 11)
tLEB
MIN
TYP
50
MAX
UNIT
300
ns
R_LEB = 20k
64
ns
R_LEB = 140k
302
ns
R_LEB = 12V
0
ns
LATCHING SHUTDOWN (LATSD)
Fault Threshold
VIN
Fault_NOT Threshold
VINN
Time to Set latch (Note 5)
TSET
3
V
1.9
415
V
ns
ON/OFF (ON/OFF)
Turn-off Threshold
OFF
Turn-on Threshold
ON
0.8
2
V
V
CURRENT SHARE (SHARE, CS_COMP) (Note 5)
Voltage Offset Between Error Amp
Voltage of Master and Slave
Vcs_offset
SHARE = 30k
30
mV
Maximum Source Current To External
Reference
Ics_source
SHARE = 30k
190
µA
SHARE = 30K, Rsource = 1k,
OUTPUT REFERENCE = 1 to 5V,
(See Figure 13)
190
mV
CS_COMP = 0.1µF
500
Hz
Maximum Correctable Deviation In
Reference Voltage Between Master
and Slave
Share/Adjust Loop Bandwidth
CS BW
DCOK (DCOK)
Sink Current
IDCOK
Saturation Voltage
VSATDCOK
Input Reference
IDCOK = 5mA
Vref_in
1
5
mA
0.4
V
5
V
5
%
(Figure 14)
3
%
(Figure 14)
-5
%
Threshold (relative to Vref_in)
OV
(Figure 14)
Recovery (relative to Vref_in)
OV
Threshold (relative to Vref_in)
UV
Recovery (relative to Vref_in)
UV
(Figure 14)
Transient Rejection (Note 5)
TRej
100mV transient on Vout (system implicit rejection
and feedback network dependence (Figure 15)
-3
%
250
µs
NOTE:
5. Established by design. Not 100% tested in production.
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8
FN9066.7
October 28, 2015
ISL6551
Drive Signals Timing Diagrams
CLOCK
UPPER1
UPPER2
SYNC1
SYNC2
LOWER1
EAO
ILOWER1
LOWER2
EAO
ILOWER2
EAO
RAMP ADJUST
OUTPUT TO
PWM
LOGIC
T2
T1
T3
T4
T5
NOTES:
t1 = Leading edge blanking
t2 = t4 = Resonant delay
t3 = t5 = dead time
In the above figure, the values for t1 through t5 are exaggerated for demonstration purposes.
FIGURE 2. DRIVE SIGNALS TIMING DIAGRAMS
Timing Diagram Descriptions
The two upper drivers (UPPER1 and UPPER2) are driven at a
fixed 50% duty cycle and the two lower drivers (LOWER1 and
LOWER2) are PWM controlled on the trailing edge, while the
leading edge employs resonant delay (t2 and t4). In current
mode control, the sensed switch (FET) current (ILOWER1 and
ILOWER2) is processed in the Ramp Adjust and Leading Edge
Blanking (LEB) circuits and then compared to a control signal
(EAO). Spikes, due to parasitic elements in the bridge circuit,
would falsely trigger the comparator generating the PWM
signal. To prevent false triggering, the leading edge of the
sensed current signal is blanked out by t1, which can be
programmed at the R_LEB pin with a resistor. Internal switches
gate the analog input to the PWM comparator, implementing
the blanking function that eliminates response degrading delays
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9
which would be caused if filtering of the current feedback was
incorporated. The dead time (t3 and t5) is the delay to turn on
the upper FET (UPPER1/UPPER2) after its corresponding lower
FET (LOWER1/LOWER2) is turned off when the bridge is
operating at maximum duty cycle in normal conditions, or is
responding to load transients or input line dipping conditions.
Therefore, the upper and lower FETs that are located at the
same side of the bridge can never be turned on together, which
eliminates shoot-through currents. SYNC1 and SYNC2 are the
gate control signals for the output synchronous rectifiers. They are
biased by VDD and are capable of driving capacitive loads up to
20pF at 1MHz clock frequency (500kHz switching frequency).
External drivers with high current capabilities are required to drive
the synchronous rectifiers, cascading with both synchronous
signals (SYNC1 and SYNC2).
FN9066.7
October 28, 2015
ISL6551
Shutdown Timing Diagrams
LATCH CANNOT BE RESET BY ON/OFF
C
LATSD
D
ON/OFF
A
E
VDDON
VDD
LATCH RESET BY
REMOVING VDD
PKILIM > BGREF
B
ILIM_OUT
F
VDDOFF
PKILIM < BGREF
SOFT
START
DRIVER
ENABLE
SOFT-START
SHUTDOWN
FAULT
FAULT
OFF
OVER
CURRENT
LATCHED
OFF/ON
LATCH
RESET
UNDER VOLTAGE
LOCKOUT
FIGURE 3. SHUTDOWN TIMING DIAGRAMS
Shutdown Timing Descriptions
A (ON/OFF) - When the ON/OFF is pulled low, the soft-start
capacitor is discharged and all the drivers are disabled. When the
ON/OFF is released without a fault condition, a soft-start is
initiated.
B (OVERCURRENT) - If the output of the converter is over loaded,
i.e., the PKILIM is above the bandgap reference voltage (BGREF),
the soft-start capacitor is discharged very quickly and all the
drivers are turned off. Thereafter, the soft-start capacitor is
charged slowly and discharged quickly if the output is overloaded
again. The soft-start will remain in hiccup mode as long as the
overload conditions persist. Once the overload is removed, the
soft-start capacitor is charged up and the converter is then back
to normal operation.
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10
C (LATCHING SHUTDOWN) - The IC is latched off completely as the
LATSD pin is pulled high and the soft-start capacitor is reset.
D (ON/OFF) - The latch cannot be reset by the ON/OFF.
E (LATCH RESET) - The latch is reset by removing the VDD. The
soft-start capacitor starts to be charged after VDD increases
above the turn-on threshold VDDON.
F (VDD UVLO) - The IC is turned off when the VDD is below the
turn-off threshold VDDOFF. Hysteresis VDDHYS is incorporated in
the undervoltage lockout (UVLO) circuit.
FN9066.7
October 28, 2015
ISL6551
Block/Pin Functional
Descriptions
• Undervoltage Lockout (UVLO)
- UVLO establishes an orderly start-up and verifies that VDD
is above the turn-on threshold voltage (VDDON). All the
drivers are held low during the lockout. UVLO incorporates
hysteresis VDDHYS to prevent multiple startup/shutdowns
while powering up.
- UVLO limits are not applicable to VDDP1 and VDDP2.
Detailed descriptions of each individual block in the functional
block diagram on page 5 are included in this section.
Application information and design considerations for each pin
and/or each block are also included.
• Bandgap Reference (BGREF)
- The reference voltage VREF is generated by a precision
bandgap circuit.
- This pin must be pulled up to VDD with a resistance of
approximately 399kΩ for proper operation. For additional
reference loads (no more than 1mA), this pull-up resistor
should be scaled accordingly.
- This pin must also be decoupled with an 0.1µF low ESR
ceramic capacitor.
• IC Bias Power (VDD, VDDP1, VDDP2)
- The IC is powered from a 12V ±10% supply.
- VDD supplies power to both the digital and analog circuits
and should be bypassed directly to the VSS pin with an
0.1µF low ESR ceramic capacitor.
- VDDP1 and VDDP2 are the bias supplies for the upper
drivers and the lower drivers, respectively. They should be
decoupled with ceramic capacitors to the PGND pin.
- Heavy copper should be attached to these pins for a
better heat spreading.
• Clock Generator (CT, RD)
- This free-running oscillator is set by two external
components as shown in Figure 4. A capacitor at CT is
charged and discharged with two equal constant current
sources and fed into a window comparator to set the clock
frequency. A resistor at RD sets the clock dead time. RD
and CT should be tied to the VSS pin on their other ends
as close as possible. The corresponding CT for a particular
frequency can be selected from Figure 5.
- The switching frequency (fsw) of the power train is half of
the clock frequency (Fclock), as shown in Equation 1.
• IC GNDs (VSS, PGND)
- VSS is the reference ground, the return of VDD, of all
control circuits and must be kept away from nodes with
switching noises. It should be connected to the PGND in
only one location as close to the IC as practical. For a
secondary side control system, it should be connected to
the net after the output capacitors, i.e., the output return
pinout(s). For a primary side control system, it should be
connected to the net before the input capacitors, i.e., the
input return pinout(s).
- PGND is the power return, the high-current return path of
both VDDP1 and VDDP2. It should be connected to the
SOURCE pins of two lower power switches or the RETURNs
- of external drivers as close as possible with heavy copper
traces.
- Copper planes should be attached to both pins.
RD
Fclock
f sw = ------------------2
(EQ. 1)
SET CLOCK
DEAD TIME (DT)
RD
VDDI_CT
VMAX
+
OUT
CT
CT
CLK
S
I_CT
VMIN
- OUT
+
R
Q
Q
Q
Q
CLK
DT
DT
FIGURE 4. SIMPLIFIED CLOCK GENERATOR CIRCUIT
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FN9066.7
October 28, 2015
ISL6551
3,000
2
DEAD TIME (µs)
0°C
60°C
2,500
120°C
F (kHz)
2,000
1,500
1.6
1.2
0.8
0.4
1,000
0
0
500
0
20
40
60
80
100
120
140
160
RD (kΩ)
10
100
CT (pF)
1,000
RECOMMENDED RANGE
FIGURE 5. CT vs FREQUENCY
- Note that the capacitance of a scope probe (~12pF for
single ended) would induce a smaller frequency at the CT
pin. It can be easily seen at a higher frequency. An
accurate operating frequency can be measured at the
outputs of the bridge/synchronous drivers.
- The dead time is the delay to turn on the upper FET
(UPPER1/UPPER2) after its corresponding lower FET
(LOWER1/LOWER2) is turned off when the bridge is
operating at maximum duty cycle in normal conditions, or
is responding to load transients or input line dipping
conditions. This helps to prevent shoot through between
the upper FET and the lower FET that are located at the
same side of the bridge. The dead time can be estimated
using Equation 2:
M  RD
DT = -------------------k
(ns)
FIGURE 6. RD vs DEAD TIME (VDD = 12V)
10,000
(EQ. 2)
WHERE M = 11.4(VDD = 12V), 11.1(VDD = 14V) and
12(VDD = 10V) and RD is in kΩ. This relationship is shown
in Figure 6.
• Error Amplifier (EAI, EANI, EAO)
- This amplifier compares the feedback signal received at
the EAI pin to a reference signal set at the EANI pin and
provides an error signal (EAO) to the PWM Logic. The
feedback loop compensation can be programmed via
these pins.
- Both EANI and EAO are clamped by the voltage (Vclamp)
set at the CSS pin, as shown in Figure 7. Note that the
diodes in the functional block diagram represent the
clamp function of the CSS in a simplified way.
• Soft-start (CSS)
- The voltage on an external capacitor charged by an
internal current source ISS is fed into a control pin on the
error amplifier. This causes the Error Amplifier to: 1) limit
the EAO to the soft-start voltage level; and 2) over ride the
reference signal at the EANI with the soft-start voltage,
when the EANI voltage is higher than the soft-start
voltage. Thus, both the output voltage and current of the
power supply can be controlled by the soft-start.
- The clamping voltage determines the cycle-by-cycle peak
current limiting of the power supply. It should be set above
the EANI and EAO voltages and can be programmed by an
external resistor as shown in Figure 7 using Equation 3.
Vclamp = Rcss  Iss
400mV
VDD
CSS
+
-
(EQ. 3)
(V)
Figure 12
SSL
(TO
BLANKING
CIRCUIT)
EAI
(–)
Iss
EANI
(+)
RCSS
SHUTDOWN
ERROR AMP
EAO
FIGURE 7. SIMPLIFIED CLAMP/SOFT-START
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FN9066.7
October 28, 2015
ISL6551
- Per Equation 3, the clamping voltage is a function of the
charge current Iss. For a more predictable clamping
voltage, the CSS pin can be connected to a referencebased clamp circuit as shown in Figure 8. To make the
Vclamp less dependent on the soft-start current (Iss), the
currents flowing through R1 and R2 should be scaled
much greater than Iss. The relationship of this circuit can
be found in Equation 4.
divider from the ISENSE pin. The resistor divider relationship
is defined in Equation 7.
- In general, the trip point is a little smaller than the BGREF
due to the noise and/or ripple at the BGREF.
ISENSE
RUP
PKILIM
RDOWN
VREF
R1
FIGURE 9. PEAK CURRENT LIMIT SET CIRCUIT
CSS
R DOWN
BGREF
---------------------------------------- = ----------------------------------------R DOWN + R UP
ISENSE  max 
FIGURE 8. REFERENCE-BASED CLAMP CIRCUIT
R2
R1  R2
Vclamp  Iss  --------------------- + Vref  --------------------R1 + R2
R1 + R2
(EQ. 4)
- The soft-start rise time (Tss) can be calculated with
Equation 5. The rise time (Trise) of the output voltage is
approximated with Equation 6.
Vclamp  Css
t ss = --------------------------------------Iss
(s)
EANI  Css
t rise = -------------------------------Iss
(s)
(EQ. 5)
(EQ. 6)
• Drivers (Upper1, Upper2, Lower1, Lower2)
- The two upper drivers are driven at a fixed 50% duty cycle
and the two lower drivers are PWM controlled on the
trailing edge while the leading edge employs resonant delay.
They are biased by VDDP1 and VDDP2, respectively.
- Each driver is capable of driving capacitive loads up to CL at
1MHz clock frequency and higher loads at lower frequencies
on a layout with high effective thermal conductivity.
- The UVLO holds all the drivers low until the VDD has reached
the turn-on threshold VDDON.
- The upper drivers require assistance of external level-shifting
circuits such as Intersil’s HIP2100 or pulse transformers to
drive the upper power switches of a bridge converter.
• Peak Current Limit (PKILIM)
- When the voltage at PKILIM exceeds the BGREF voltage, the
gate pulses are terminated and held low until the next clock
cycle. The peak current limit circuit has a high-speed loop
with propagation delay IpkDel. Peak current shutdown
initiates a soft-start sequence.
- The peak current shutdown threshold is usually set slightly
higher than the normal cycle-by-cycle PWM peak current
limit (Vclamp) and therefore will normally only be activated
in a short-circuit condition. The limit can be set with a resistor
(EQ. 7)
• Latching Shutdown (LATSD)
- A high TTL level on LATSD latches the IC off. The IC goes into
a low power mode and is reset only after the power at the
VDD pin is removed completely. The ON/OFF cannot reset
the latch.
- This pin can be used to latch the power supply off on output
overvoltage or other undesired conditions.
• ON/OFF (ON/OFF)
- A high standard TTL input (safe also for VDD level) signals the
controller to turn on. A low TTL input turns off the controller
and terminates all drive signals including the SYNC outputs.
The soft-start is reset.
- This pin is a non-latching input and can accept an enable
command when monitoring the input voltage and the
thermal condition of a converter.
• Resonant Delay (R_RESDLY)
- A resistor tied between R_RESDLY and VSS determines the
delay that is required to turn on a lower FET after its
corresponding upper FET is turned off. This is the resonant
delay, which can be estimated with Equation 8.
(EQ. 8)
tRESDLY = 4.01 x R_RESDLY/k + 13 (ns)
- Figure 10 illustrates the relationship of the value of the
resistor (R_RESDLY) and the resonant delay (tRESDLY). The
percentages in the figure are the tolerances at the two end
points of the curve.
500
+18%
450
-24%
400
tRESDLY (ns)
R2
350
300
250
200
150
+37%
100
+4%
50
0
20
40
60
80
100
120
R_RESDLY (kΩ)
FIGURE 10. R_RESDLY vs RESDLY
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FN9066.7
October 28, 2015
ISL6551
• Leading Edge Blanking (R_LEB)
- In current mode control, the sensed switch (FET) current is
processed in the Ramp Adjust and LEB circuits and then
compared to a control signal (EAO voltage). Spikes, due to
parasitic elements in the bridge circuit, would falsely trigger
the comparator generating the PWM signal. To prevent false
triggering, the leading edge of the sensed current signal is
blanked out by a period that can be programmed with the
R_LEB resistor. Internal switches gate the analog input to the
PWM comparator, implementing the blanking function that
eliminates response degrading delays, which would be
caused if filtering of the current feedback was incorporated.
The current ramp is blanked out during the resonant delay
period because no switching occurs in the lower FETs. The
leading edge blanking function will not be activated until the
soft-start (CSS) reaches over 400mV, as illustrated in
Figures 7 and 12. The leading edge blanking (LEB) function
can be disabled by tying the R_LEB pin to VDD, i.e., LEB = 1.
Never leave the pin floating.
- The blanking time can be estimated with Equation 9, whose
relationship can be seen in Figure 11. The percentages in
the figure are the tolerances at the two endpoints of the
curve.
tLEB = 2 x R_LEB / kΩ + 15 (ns)
(EQ. 9)
300
+20%
-18%
250
tLEB (ns)
200
150
+51%
100
-11%
50
0
20
40
60
80
100
120
140
R_LEB (KΩ)
FIGURE 11. R_LEB vs tLEB
0.1µ
VDD
ADJ_RAMP
ADJ_RAMP
399k
200mV
RAMP_OUT
(TO PWM
COMPARATOR)
BGREF
R_RA
ISENSE
0
RAMP_OUT
200mV
R_RA
BLANK
ADD RAMP
+
ISENSE
200mV
R_LEB
SET
BLANKING
TIME
R_LEB
RESDLY
LEB
SSL
See Figure 7
-
RESDLY
LEB
SSL
RAMP_OUT
0
X
X
BLANK
X
0
0
BLANK
1
1
X
NO BLANK
1
X
1
NO BLANK
FIGURE 12. SIMPLIFIED RAMP ADJUST AND LEADING EDGE BLANKING CIRCUITS
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14
FN9066.7
October 28, 2015
ISL6551
synchronous rectifiers. When using these drive schemes,
the user should understand the issues that might occur in
his/her applications, especially the impacts on current
share operation and light load operation. Refer to
application note AN1002 for more details.
- External high current drivers controlled by the
synchronous signals are required to drive the synchronous
rectifiers. A pulse transformer is required to pass the drive
signals to the secondary side if the IC is used in a primary
control system.
• Ramp Adjust (R_RA, ISENSE)
- The ramp adjust block adds an offset component
(200mV) and a slope adjust component to the ISENSE
signal before processing it at the PWM Logic block, as
shown in Figure 12. This ensures that the ramp voltage is
always higher than the OAGS (ground sensing opamp)
minimum voltage to achieve a “zero” state.
- It is critical that the input signal to ISENSE decays to zero
prior to or during the clock dead time. The level-shifting
and capacitive summing circuits in the RAMP ADJUST
block are reset during the dead time. Any input signal
transitions that occur after the rising edge of CLK and
prior to the rising edge of RESDLY can cause severe errors
in the signal reaching the PWM comparator.
- Typical ramp values are hundreds of mV over the period
on a 3V full scale current. Too much ramp makes the
controller look like a voltage mode PWM and too little
ramp leads to noise issues (jitter). The amount of ramp
(Vramp), as shown in Figure 12, is programmed with the
R_RA resistor and can be calculated with Equation 10.
Vramp = BGREF x dt /(R_RA x 500E-12) (V)
• Share Support (SHARE, CS_COMP)
- The unit with the highest reference is the master. Other
units, as slaves, adjust their references via a source
resistor to match the master reference sharing the load
current. The source resistor is typically 1kΩ connecting
the EANI pin and the OUTPUT REFERENCE (external
reference or BGREF), as shown in Figure 13. The share
bus represents a 30kΩ resistive load per unit, up to 10
units.
- The output (ADJ) of “Operational Transconductance
Amplifier (OTA)” can only pull high and it is floating while
in master mode. This ensures that no current is sourced to
the OUTPUT REFERENCE when the IC is working by itself.
- The slave units attempt to drive their error amplifier
voltage to be within a predetermined offset (30mV
typical) of the master error voltage (the share bus). The
current-share error is nominally (30mV/EAO)*100%
assuming no other source of error. With a 2.5V full load
error amp voltage, the current-share error at full load
would be -1.2% (slaves relative to master).
- The bandwidth of the current sharing loop should be
much lower than that of the voltage loop to eliminate
noise pickup and interactions between the voltage
regulation loop and the current loop. A 0.1µF capacitor is
recommended between CS_COMP and VSS pins to
achieve a low current sharing loop bandwidth (100Hz to
500Hz).
(EQ. 10)
Where dt = Duty Cycle / fSW - tLEB (s). Duty cycle is
discussed in detail in application note AN1002.
- The voltage representation of the current flowing
through the power train at ISENSE pin is normally scaled
such that the desired peak current is less than or equal
to Vclamp-200mV-Vramp, where the clamping voltage is
set at the CSS pin.
• SYNC Outputs (SYNC1, SYNC2)
- SYNC1 and SYNC2 are the gate control signals for the
output synchronous rectifiers. They are biased by VDD and
are capable of driving capacitive loads up to 20pF at
1MHz clock frequency (500kHz switching frequency).
These outputs are turned off sooner than the turn-off at
UPPER1 and UPPER2 by the clock dead time, DT.
- Inverting both SYNC signals or both LOWER signals is
another possible way to control the drivers of the
CS_COMP
0.1µF
30mV
+
-
+
-
EAO
+
OTA
1k
ADJ
EANI
(+)
OUTPUT
REFERENCE
SHARE
30k
FIGURE 13. SIMPLIFIED CURRENT SHARE CIRCUIT
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FN9066.7
October 28, 2015
ISL6551
• Power-good (DCOK)
- DCOK pin is an open-drain output capable of sinking 5mA.
It is low when the output voltage is within the UVOV
window. The static regulation limit is ±3%, while the ±5%
is the dynamic regulation limit. It indicates power-good
when the EAI is within -3% to +5% on the rising edge and
within +3% to -5%on the falling edge, as shown in
Figure 14.
18K
EAI
VOUT
1K
EANI
R
15N
C
+
EAO
1.10V
EAI
+5%
VOUT
1.00V
+3%
EANI
0.90V
-3%
1.05V
-5%
1.00V
EAI
0.95V
FIGURE 15. OUTPUT TRANSIENT REJECTION
DCOK
FAULT
FIGURE 14. UNDERVOLTAGE-OVERVOLTAGE WINDOW
- The DCOK comparator might not be triggered even though
the output voltage exceeds ±5% limits at load transients.
This is because the feedback network of the error amplifier
filters out part of the transients and the EAI only sees the
remaining portion that is still within the limits, as illustrated
in Figure 15. The lower the “zero (1/RC)” of the error
amplifier, the larger the portion of the transient is filtered
out.
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FN9066.7
October 28, 2015
ISL6551
Additional Applications
Information
operation of the ISL6551, see Block/Pin Functional
Descriptions.
Table 1 highlights parameter setting for the ISL6551.
Designers can use this table as a design checklist. For detailed
TABLE 1. PARAMETER SETTING HIGHLIGHTS/CHECKLIST
PARAMETER
PIN NAME
FORMULA OR SETTING HIGHLIGHT
UNIT
FIGURE #
kHz
1, 5
Frequency
CT
Set 50% Duty Cycle Pulses with a fixed frequency
Dead Time
RD
DT = M x RD/kΩ , where M = 11.4
ns
6
tRESDLY = 4.01 x R_RESDLY/kΩ + 13
ns
10
Vramp = BGREF/(R_RA x 500E-12) x dt
V
-
Resonant Delay
R_RESDLY
Ramp Adjust
R_RA
Current Sense
ISENSE
<Vclamp-200mV-Vramp
V
-
Peak Current
PKILIM
<BGREF and slightly higher than Vclamp
V
9
Bandgap Reference
BGREF
1.263V ±2%, 399kΩ pull-up, no more than 100µA load
V
-
Leading Edge Blanking
R_LEB
tLEB = 2 x R_LEB/kΩ + 15, never leave it floating
ns
11, 12
0.1µ for a low current loop bandwidth (100Hz to 500Hz)
Hz
13
Current Share Compensation
CS_COMP
Soft-start and Output Rise Time
CSS
tss = Vclamp x Css/Iss, trise = EANI x CSS / Iss, Iss = 10µA ±20%
S
7
Clamp Voltage (Vclamp)
CSS
Vclamp = Iss x Rcss, or reference based clamp
V
7, 8
EANI, EAO<Vclamp
V
-
Error Amplifier
EANI, EAI, EAO
Share Support
SHARE
30k load and a resistor (1k, typ) between EANI and OUTPUT REF.
-
-
Latching Shutdown
LATSD
Latch IC off at >3V
V
-
Power-good
DCOK
±5% with hysteresis, Sink up to 5mA, transient rejection
V
14, 15
Turn-on/off at TTL level
V
-
Connect to PGND in only one single point
-
-
Single point to VSS plane
-
-
IC Enable
ON/OFF
Reference Ground
VSS
Power Ground
PGND
Upper Drivers
UPPER1, UPPER2
Capacitive load up to 1.6nF at fSW = 500kHz
-
-
Lower Drivers
LOWER1, LOWER2
Capacitive load up to 1.6nF at fSW = 500kHz
-
-
SYNC1, SYNC2
Capacitive load up to 20pF at fSW = 500kHz
-
-
12V ±10%, 0.1µF decoupling capacitor
V
-
Need decoupling capacitors
V
-
Synchronous Drive Signals
Bias for Control Circuits
VDD
Biases for Bridge Drivers
VDDP1, VDDP2
NOTE: VDD = 12V at room temperature, unless otherwise stated.
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FN9066.7
October 28, 2015
ISL6551
Figure 16 shows the block diagram of a power supply system
employing the ISL6551 full bridge controller. The ISL6551 not
only is a full bridge PWM controller but also can be used as a
push-pull PWM controller. Users can design a power supply by
selecting appropriate blocks in the “System Blocks Chart” based
on the power system requirements. Figures 17A, 18A, 19A, 20A,
21A, 22A, 23, 24A, 25, 26A and 28A have been used in the
200W telecom power supply reference design, which can be
found in the application note AN1002. To meet the specifications
of the power supply, minor modifications of each block are
required. To take full advantage of the integrated features of the
ISL6551, “secondary side control” is recommended.
BIASES
PRIMARY BIAS
SECONDARY BIAS
VIN
INPUT
FILTER
PRIMARY
FETs
CURRENT
SENSE
MAIN
TRANSFORMER
ISL6551
CONTROLLER
PRIMARY FET
DRIVERS
SUPERVISOR
CIRCUITS
RECTIFIERS
OUTPUT
FILTER
VOUT
SECONDARY
DRIVERS
FEEDBACK
FIGURE 16. BLOCK DIAGRAM OF A POWER SUPPLY SYSTEM USING ISL6551 CONTROLLER
System Blocks Chart
VIN
LIN
VIN
VINF
VINF
CIN
CIN
FIGURE 17A. GENERAL
FIGURE 17B. EMI
FIGURE 17. INPUT FILTERS
General- Input capacitors are required to absorb the power
switch (FET) pulsating currents.
EMI- For good EMI performance, the ripple current that is
reflected back to the input line can be reduced by an input
L-C filter, which filters the differential-mode noises and
operates at two times the switching frequency, i.e., the clock
frequency (Fclock). In some cases, an additional
common-mode choke might be required to filter the commonmode noises.
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18
FN9066.7
October 28, 2015
ISL6551
Current Sense
ISENSE
VINF
ISENSE
T_CURRENT
Q3_S
CURRENT_SEN_P
Q4_S
FIGURE 18B. TOP SENSE
FIGURE 18A. TWO-LEG SENSE
Q3_S and Q4_S
ISENSE
RSENSE
FIGURE 18C. RESISTOR SENSE (PRIMARY CONTROL)
FIGURE 18. CURRENT SENSE
Primary FETs
VINF
or CURRENT_SEN_P
P1–
Q1
Q1_G
P–
Q2
Q2_G
Q3
Q4
Q4_G
Q3_S
Q3
Q3_G
P+
Q3_G
P2–
Q3_S
Q4
Q4_G
Q4_S
Q4_S
FIGURE 19A. FULL BRIDGE
FIGURE 19B. PUSH-PULL
FIGURE 19. PRIMARY FETs
Two-leg Sense- Senses the current that flows through both lower
primary FETs. Operates at the switching frequency.
Top Sense- Senses the sum of the current that flows through both
upper primary FETs. Operates at the clock frequency.
Resistor Sense- This simple scheme is used in a primary side
control system. The sum of the current that flows through both
lower primary FETs is sensed with a low impedance power
resistor. The sources of Q3 and Q4 and ISENSE should be tied at
the same point as close as possible.
DCM Flyback- Use a PWM controller to develop both primary
and secondary biases with discontinuous current mode
flyback topology
Full Bridge- Four MOSFETs are required for full bridge
converters. The drain-to-source voltage rating of the MOSFETs
is VIN.
Push-pull- Only the two lower MOSFETs are required for
push-pull converters. The two upper drivers are not used. The
VDS of the MOSFETs is 2xVIN.
BIASES
Linear Regulator- In a primary side control system, a linear
regulator derived from the input line can be used for the
start-up purpose and an extra winding coupled with the main
transformer can provide the controller power after the start
up.
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19
FN9066.7
October 28, 2015
ISL6551
Feedback
VREF = 5V
VOPOUT
IL207
EAO
EAI
VOPOUT
EAI
TL431
EAO
FIGURE 20B. PRIMARY CONTROL
FIGURE 20A. SECONDARY CONTROL
FIGURE 20. FEEDBACK
Secondary Control- In secondary side control systems, only a
few resistors and capacitors are required to complete the
feedback loop.
Primary Control- This feedback loop configuration for primary
side control systems requires an optocoupler for isolation. The
bandwidth is limited by the optocoupler.
Rectifiers
SYNCHRONOUS FETs
S+
SYNCHRONOUS FETs
SCHOTTKY
S+
S+
SCHOTTKY
S+
SYNP
SYNN
SYNP
SYNN
S–
S–
S–
S–
FIGURE 21B. CONVENTIONAL RECTIFIERS
FIGURE 21A. CURRENT DOUBLER RECTIFIERS
S+
S–
FIGURE 21C. SELF-DRIVEN RECTIFIERS
FIGURE 21. RECTIFIER
Current Doubler Rectifiers:
Conventional Rectifiers:
• Synchronous FETs are used for low output voltage, high
output current and/or high efficiency applications.
• Synchronous FETs are used for low output voltage, high
output current and/or high efficiency applications.
• Schottky diodes are used for lower current applications. Pins
S+ and S- are connected to the output filter and the main
transformer with current doubler configurations.
• Schottky diodes are used for lower current applications. Pins
S+ and S- are connected to the main transformer with
conventional configurations.
Self-driven Rectifiers- For low output voltage applications, both
FETs can be driven by the voltage across the secondary
winding. This can work with all kinds of main transformer
configurations as shown in Figures 22A through 22D.
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20
FN9066.7
October 28, 2015
ISL6551
Main Transformers
P+
S+
P+
S+
VOUTF
P–
P–
S–
FIGURE 22A. FULL BRIDGE AND CURRENT DOUBLER
P1–
FIGURE 22B. CONVENTIONAL FULL BRIDGE
P1–
S+
S+
VINF
or CURRENT_SEN_P
VINF
or CURRENT_SEN_P
P2–
S–
VOUTF
S–
P2–
S–
FIGURE 22D. CONVENTIONAL PUSH-PULL
FIGURE 22C. PUSH-PULL AND CURRENT DOUBLER
FIGURE 22. MAIN TRANSFORMERS
Full Bridge and Current Doubler- No center tap is required. The
secondary winding carries half of the load, i.e., only half of the
load is reflected to the primary.
Supervisor Circuits
Conventional Full Bridge- Center tap is required on the
secondary side and no center tap is required on the primary
side. The secondary winding carries all the load. i.e., all the
load is reflected to the primary.
• Intersil ISL6550 Supervisor And Monitor (SAM). Its QFN
package requires less space than the SOIC package.
Push-pull and Current Doubler- Center tap is required on the
primary side and no center tap is required on the secondary
side. The secondary winding carries half of the load, i.e., only
half of the load is reflected to the primary.
Conventional Push-pull- Both primary and secondary sides
require center taps. The secondary winding carries all the load,
i.e., all the load is reflected to the primary.
INTEGRATED SOLUTION
• Over-temperature protection (discrete)
• Input UV lockout (discrete)
DISCRETE SOLUTION
• Differential amplifier
• VCC undervoltage lockout
• Programmable output OV and UV
• Programmable output
• Status indicators (PGOOD and START)
• Precision reference
• Over-temperature protection
• Input UV lockout
VOPOUT
VREF5
BDAC
VCC
1
20 UVDLY
VOPP
2
VOPM
3
19 OVUVSEN
18 PGOOD
PGOOD
VOPOUT
4
17 START
START
PEN
VREF5
5
16 PEN
GND
6
15 VID0
BDAC
7
14 VID1
OVUVTH
8
13 VID2
DACHI
9
12 VID3
DACLO 10
11 VID4
FIGURE 23. ISL6550 SOIC
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21
FN9066.7
October 28, 2015
ISL6551
The Integrated Solution- Is much simpler than a discrete
solution. Over-temperature protection and input undervoltage
lockout can be added for better system protection and
performance.
The Discrete Solution- Requires a significant number of
components to implement the features that the ISL6550 can
provide.
Output Filter
LOUT
LOUT
S+
VOUT
VOUTF
COUT
FCLOCK
VOUT
COUT
S–
FIGURE 24B. CONVENTIONAL FILTER
FIGURE 24A. CURRENT DOUBLER FILTER
FIGURE 24. OUTPUT FILTER
Current Doubler Filter- Two inductors are needed, but they can be
integrated and coupled into one core. Each inductor carries half of
the load operating at the switching frequency.
ISL6551 Controller- It can be used as a full bridge or push-pull
PWM controller. Secondary Drivers.
MIC4421BM
Conventional Filter- One inductor is needed. The inductor carries
all the load operating at two times the switching frequency.
SYNC2
IN OUT
/LOWER1
Controller
27 VDDP1
RD 3
26 VDDP2
R_RA 5
24 UPPER1
ISENSE 6
23 UPPER2
ICL6551
SOIC
22 LOWER1
SYNN
GND
FIGURE 26A. INVERTING DRIVERS
MIC4422BM
INPUT
UV & OV
SYNC1
IN OUT
21 LOWER2
R_LEB 9
20 SYNC1
CS_COMP 10
OUTPUT
REFERENCE CSS 11
(BDAC)
EANI 12
19 SYNC2
EAI 13
16 LSTSD
EAO 14
15 SHARE
EAO
IN OUT
25 PGND
R_RESDLY 4
EAI
SYNC1
/LOWER2
28 VDD
CT 2
BGREF 8
SYNP
GND
VSS 1
PKILIM 7
MIC4421BM
18 ON / OFF
17 DCOK
MIC4422BM
SYNP
IN OUT
SYNC2
SYNN
GND
GND
FIGURE 26B. NONINVERTING DRIVERS
LED
LSTSD
IN OUT
SHARE
BUS
T_SYN
SYNP
GND
SYN1
FIGURE 25. ISL6551 CONTROLLER
SYN2
IN OUT
fSW
SYNN
GND
INVERTING
NON INVERTING
SYN1
SYNC2/LOWER1
SYNC1
SYN2
SYNC1/LOWER2
SYNC2
IC
MIC4421BM
MIC4422BM
FIGURE 26C. PRIMARY CONTROL
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22
FN9066.7
October 28, 2015
ISL6551
Inverting Drivers- Inverting the SYNC signals or the LOWER
signals with external high current drivers to drive the
synchronous FETs.
Primary Control- This requires a pulse transformer, operating
at the switching frequency, for isolation. There are three
options to drive the synchronous FETs, as described in previous
lines.
Noninverting Drivers- Cascading SYNC signals with
noninverting high current drivers to drive the synchronous
FETs. There is a dead time between SYNC1 and SYNC2. For a
higher efficiency, Schottky diodes are normally in parallel with
the synchronous FETs to reduce the conduction losses during
the dead time in high output current applications.
Primary FET Drivers
HIP2100IB
Q3_G
HO
Q3_G
HS
LI
VSS LO
Q3_S
HI
LOWER1
Q3_S
Q4_G
LOWER1
Q4_S
Q4_S
LOWER2
LOWER2
Q4_G
FIGURE 27B. PUSH-PULL HIGH CURRENT DRIVERS
FIGURE 27A. PUSH-PULL MEDIUM CURRENT DRIVERS
HIP2100IB
LOWER1
LOWER2
PGND
HO
Q3_G
HS
Q3_S
VSS LO
Q4_G
HI
LI
Q4_S
FIGURE 27C. PUSH-PULL PRIMARY CONTROL
FIGURE 27. PUSH-PULL DRIVERS
Push-pull Medium CurrenPRIMARY CONTROLt Drivers- Upper
drivers are not used. No external drivers are required.
Secondary control. Operate at the switching frequency.
Push-pull High Current Drivers- Upper drivers are not used.
External high current drivers are required and less power is
dissipated in the ISL6551 controller. Secondary control.
Operate at the switching frequency.
Push-pull Primary Control- Upper drivers are not used. Both
lower drivers can directly drive the power switches. External
drivers are required in high gate capacitance applications.
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23
FN9066.7
October 28, 2015
ISL6551
Full Bridge Drivers
HIP2100IB
HI
HO
HS
LI
VSS LO
UPPER1
Q1_G
Q1_G
P–
Q3_G
UPPER1
P–
Q3_S
UPPER2
P+
UPPER2
HIP2100IB
HI
HO
HS
LI
VSS LO
Q2_G
Q2_G
P+
Q3_G
Q4_G
LOWER1
Q4_S
Q3_S
LOWER1
LOWER2
Q4_S
LOWER2
Q4_G
FIGURE 28B. FULL BRIDGE MEDIUM CURRENT DRIVERS
FIGURE 28A. FULL BRIDGE HIGH CURRENT DRIVERS
HIP2100IB
UPPER1
LOWER1
HI
HO
HS
LI
VSS LO
PGND
Q1G
P–
Q3_G
Q3_S
HIP2100IB
UPPER2
HI
LOWER2
LI
VSS LO
PGND
HO
HS
Q2_G
P+
Q4_G
Q4_S
FIGURE 28C. FULL BRIDGE PRIMARY CONTROL
FIGURE 28. FULL BRIDGE DRIVERS
Full Bridge High Current Drivers- External high current drivers are
required and less power is dissipated in the ISL6551 controller.
Secondary control. Operate at the switching frequency.
Full Bridge Medium Current Drivers- No external drivers are
required. Secondary control. Operate at the switching frequency.
Full Bridge Primary Control- Lower drivers can directly drive the
power switches, while upper drivers require the assistance of
level-shifting circuits such as a pulse transformer or Intersil’s
HIP2100 half-bridge driver. External high current drivers are not
required in medium power applications, but level-shifting circuits
are still required for upper drivers. Operate at the switching
frequency.
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24
FN9066.7
October 28, 2015
Submit Document Feedback
Simplified Typical Application Schematics
SB+48V
SB+12V
SA+12V
VDD
HB
HO
HS
UPPER1
LOWER1
VS VS
OUT IN
OUT NC
GND GND
LO
VSS
LI
HI
SYNC2
3.3Vout
MIC4421
HIP2100
25
UPPER2
SA+12V
LOWER2
VS VS
OUT IN
OUT NC
GND GND
LOWER1
SB+12V
VDD
HB
HO
HS
LOWER2
SYNC1
MIC4421
LO
VSS
LI
HI
+
HIP2100
SA+12V
V+
+
V-
SA+12V
-
OUT
20
19
18
17
16
15
14
13
12
11
UVDLY
VCC
OVU VSEN VOPP
PGOOD
VOPM
START VOPOUT
PEN
VREF5
VID0
G ND
BDAC
VID1
OVUVTH
VID2
DACHI
VID3
DACLO
VID4
ISL6550
1.263V
PGND
UPPER1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
UPPER2
LOWER1
LOWER2
SYNC1
SYNC2
LED
VDD
VSS
VDDP1
CT
VDDP2
RD
PGND R_RESDLY
R_RA
UPPER1
ISENSE
UPPER2
PKILIM
LOWER1
BGREF
LOWER2
R_LEB
SYNC1
SYNC2 CS_COMP
ON/OFF
CSS
DCOK
EANI
LATSD
EAI
SHARE
EAO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
ISL6551
FN9066.7
October 28, 2015
SHARE BUS
Note: 200W TELECOMMUNICATION POWER SUPPLY (SEE AN1002 FOR DETAILS)
1
2
3
4
5
6
7
8
9
10
ISL6551
-
PGOOD
ISL6551
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
CHANGE
October 28, 2015
FN9066.7
Updated Ordering Information Table on page 3.
April 30, 2015
FN9066.6
- Updated entire datasheet to Intersil new standard.
-Removed obsolete package “QFN” throughout the datasheet.
-Added Rev History and about intersil verbiage.
-Updated M28.3 POD from rev 0 to rev 1 by adding land pattern.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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26
FN9066.7
October 28, 2015
ISL6551
Small Outline Plastic Packages (SOIC)
M28.3 (JEDEC MS-013-AE ISSUE C)
N
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
H
0.25(0.010) M
B M
INCHES
E
SYMBOL
-B-
1
2
3
L
SEATING PLANE
-A-
A
D
h x 45o
a
e
A1
B
C
0.10(0.004)
0.25(0.010) M
C A M
B S
MAX
MILLIMETERS
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
A1
0.0040
0.0118
0.10
0.30
-
B
0.013
0.0200
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.6969
0.7125
17.70
18.10
3
E
0.2914
0.2992
7.40
7.60
4
e
-C-
MIN
0.05 BSC
h
0.01
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6

10.00
-
0.394
N
0.419
1.27 BSC
H
28
0o
10.65
-
28
8o
0o
7
8o
Rev. 1, 1/13
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
TYPICAL RECOMMENDED LAND PATTERN
(1.50mm)
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
(9.38mm)
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch)
(1.27mm TYP)
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(0.51mm TYP)
27
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
FN9066.7
October 28, 2015
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