DATASHEET

ISL6721A
Data Sheet
Flexible Single-ended Current Mode PWM
Controller
The ISL6721A is a low power, single-ended pulse width
modulating (PWM) current mode controller designed for a
wide range of DC/DC conversion applications including
boost, flyback, and isolated output configurations. Peak
current mode control effectively handles power transients
and provides inherent overcurrent protection. Other features
include a low power mode where the supply current drops to
less than 200µA during overvoltage and overcurrent
shutdown faults. It differs from the ISL6721 in that the UVLO
and UV thresholds have been modified.
August 23, 2011
FN6797.0
Features
• 1A MOSFET Gate Driver
• 100µA Startup Current
• Fast Transient Response with Peak Current Mode Control
• Adjustable Switching Frequency up to 1MHz
• Bidirectional Synchronization
• Low Power Disable Mode
• Delayed Restart from OV and OC Shutdown Faults
• Adjustable Slope Compensation
This advanced BiCMOS design features low operating
current, adjustable operating frequency up to 1MHz,
adjustable soft-start, and a bidirectional SYNC signal that
allows the oscillator to be locked to an external clock for
noise sensitive applications.
• Adjustable Soft-start
Applications
• Integrated Thermal Shutdown
• Adjustable Overcurrent Shutdown Delay
• Adjustable UV and OV Monitors
• Leading Edge Blanking
• 1% Tolerance Voltage Reference
• Telecom and Datacom Power
• Pb-Free (RoHS Compliant)
• Wireless Base Station Power
• File Server Power
• Industrial Power Systems
• Isolated Buck and Flyback Regulators
• Boost Regulators
Pinouts
ISL6721A
(16 LD QFN)
TOP VIEW
12 LGND
OV 6
11 SS
10 COMP
RTCT 7
9 FB
ISET 8
1
15
14
13
SYNC
1
12
VCC
SLOPE
2
11
VREF
UV
3
10
LGND
OV
4
9
SS
5
6
7
8
COMP
13 VREF
UV 5
16
FB
SLOPE 4
PGND
14 VCC
ISET
SYNC 3
VC
15 PGND
GATE
16 VC
RTCT
GATE 1
ISENSE 2
ISENSE
ISL6721A
(16 LD TSSOP)
TOP VIEW
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2003-2005, 2007, 2008, 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL6721A
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART MARKING
TEMP RANGE (°C)
PACKAGE
PKG. DWG. #
ISL6721AARZ
21AZ
-40 to +105
16 Ld QFN
L16.3x3B
ISL6721AAVZ
6721A AVZ
-40 to +105
16 Ld TSSOP
M16.173
NOTES:
1. *Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6721A. For more information on MSL please see
Tech Brief TB363.
2
FN6797.0
August 23, 2011
ISL6721A
Functional Block Diagram
VREF
5.00 V
1%
VCC
START/STOP
UV COMPARATOR
+
-
VREF
SOFT-START
CHARGE
70µA
CURRENT
ENABLE
ON
BG +SS CHARGE
VOLTAGE CLAMP
THERMAL
PROTECTION
SS
OC
FAULT
SS CHARGED
RESTART
DELAY
25µA
+
-
15µA
+
-
LGND
4.375V
OC
ISET
SS DCHG ON
0.8
ISENSE
5k
+
VREF
53µA
+
-
Σ
+
SHTDN
OVERCURRENT
COMPARATOR
100mV
+
OVERCURRENT
SHUTDOWN
DELAY
OC DETECT
SS CHG
SLOPE
0.1
+
SS CLAMP
+
PWM
COMPARATOR
VFB
ERROR
AMPLIFIE
R
+
-
R
Q
SET DOMINANT
+
-
VREF
VREF
UV COMPARATOR
4.65V
+
1/3
Q
100nS
BLANKING
START
BG
+
-
VREF
2.50V
BLANKING
COMPARATOR
12k
ON
-
30K
+
UV
+
-
3.0V
1.5V
1.93V
3.0V
+
-
20K
OV
+
-
+
2.5V
S
+
-
COMP
270mV
SS LOW
COMPARATOR
FAULT
LATCH
SS
+
-
-
SS LOW
+
OSCILLATOR
COMPARATOR
-
RTCT
Bi-Directional
Synchronization
+
1mA
S
Q
R
Q
VC
GATE
OSC IN
VREF
ON
36k
CLK OUT
+
-
4V
NO EXT SYNC
2V
EXT SYNC BLANKING
+
SYNC IN
PGND
SYNC OUT
VREF
100
SYNC
4.5k
3
FN6797.0
August 23, 2011
ISL6721A
Typical Application - 48V Input Dual
Output Flyback, 3.3V @ 2.5A, 1.8V @ 1.0A
SP1
SP2
CR5
T1
ISOLATION
XFMR
+3.3V
C21
+
+ C16
C15
R21
VIN+ P9
+1.8V
C18
R24
CR4
C2
C20
C17
CR2
C5
+
C22
C19 +
RETURN
CR6
R1
R16
36-75V
R17
R18
C6
C1
C3
R19
TP1
U2
Q1
C14
R2
R3
R4
R15
R22
C13
R23
VIN-
U3
R20
TP2
R25
C4
Q2
U4
VC
GATE
D1
TP3
ISENSE
SYNC
VCC
SYNC
UV
R5
OV
ISL6721A
SLOPE
PGND
R14
VREF
LGND
SS
TP4
R26
R6
TP5
RTCT
D2
ISET
COMP
VFB
R27
Q3
C12
R8
C11
R10
C7
VR1
R7
4
C9
C8
R11
R9
R12
R13
C10
FN6797.0
August 23, 2011
ISL6721A
Typical Boost Converter Application
Schematic
CR1
L1
VIN+
+VOUT
+
C2
R12
C3
C12
RETURN
Q1
R8
R1
R4
R3
R2
C11
C1
VIN+
R10
U1
C4
C10
GATE
VC
ISENSE PGND
SYNC
VCC
SLOPE VREF
RTCT
ISET
ISL6721A
UV
OV
LGND
SS
COMP
R9
VFB
R5
R11
C7
C9
C6
C5
R6
C8
R7
VIN-
5
FN6797.0
August 23, 2011
ISL6721A
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VCC, VC . . . . . . . . . . . . . . . . . GND -0.3V to +20.0V
GATE . . . . . . . . . . . . . . . . GND - 0.3V to Gate Output Limit Voltage
PGND to LGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3V
VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 5.3V
Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VREF
Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1A
Thermal Resistance (Typical)
θJA (°C/W)
θJC (°C/W)
16 Ld QFN (Notes 5, 6) . . . . . . . . . . . .
44
4
16 Ld TSSOP (Notes 7, 8) . . . . . . . . . .
105
33
Maximum Junction Temperature . . . . . . . . . . . . . . .-55°C to +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range
ISL6721Axx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C
Supply Voltage Range (Typical, Note 4) . . . . . . . . 9VDC to 18VDC
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4. All voltages are with respect to GND.
5. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
6. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
7. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
8. For θJC, the “case temp” location is taken at the package top center.
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application
schematic on page 3 and page 4. 9V < VCC = VC < 20V, RT = 11kΩ, CT = 330 pF. Typical values are at
TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +105°C.
MIN
(Note 9)
TYP
MAX
(Note 9)
UNITS
START Threshold
6.40
6.80
6.90
V
STOP Threshold
5.85
6.20
6.30
V
Hysteresis
0.50
0.60
1.00
V
-
100
175
µA
-
200
300
µA
PARAMETER
TEST CONDITIONS
UNDERVOLTAGE LOCKOUT
Start-Up Current, ICC
VCC < START Threshold
OC/OV Fault Operating Current, ICC
Operating Current, ICC
(Note 11)
-
4.5
10.0
mA
Operating Supply Current, IC
Includes 1nF GATE loading
-
8.0
12.0
mA
Line, load, 0°C to +105°C
4.95
5.00
5.05
V
Line, load, -40°C to +105°C
4.90
5.00
5.05
V
-
5
-
mV
Fault Voltage
4.50
4.65
4.75
V
VREF Good Voltage
4.65
4.80
4.95
V
Hysteresis
75
165
250
mV
Operational Current
-10
-
-
mA
Current Limit
-20
-
-
mA
-
5
-
kΩ
0.08
0.10
0.11
V
0
-
1.5
V
REFERENCE VOLTAGE
Overall Accuracy
Long Term Stability
TA = +125°C, 1000 hours (Note 10)
CURRENT SENSE
Input Impedance
Offset Voltage
Input Voltage Range
6
FN6797.0
August 23, 2011
ISL6721A
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application
schematic on page 3 and page 4. 9V < VCC = VC < 20V, RT = 11kΩ, CT = 330 pF. Typical values are at
TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +105°C. (Continued)
PARAMETER
TEST CONDITIONS
Blanking Time
(Note 10)
Gain, ACS
VSLOPE = 0V, VFB = 2.3V,
VISET = 0.35V, 1.5V
ACS = ΔISET/ΔISENSE
MIN
(Note 9)
TYP
MAX
(Note 9)
UNITS
30
60
100
ns
0.77
0.79
0.81
V/V
ERROR AMPLIFIER
Open Loop Voltage Gain
(Note 10)
60
90
-
dB
Gain-Bandwidth Product
(Note 10)
-
15
-
MHz
Reference Voltage Initial Accuracy
VFB = COMP, TA = +25°C
(Note 10)
2.465
2.515
2.565
V
Reference Voltage
VFB = COMP
2.44
2.515
2.590
V
COMP to PWM Gain, ACOMP
COMP = 4V, TA = +25°C
0.31
0.33
0.35
V/V
COMP to PWM Offset
COMP = 4V (Note 10)
0.51
0.75
0.88
V
FB Input Bias Current
VFB = 0V
-2
0.1
2
µA
COMP Sink Current
COMP = 1.5V, VFB = 2.7V
2
6
-
mA
COMP Source Current
COMP = 1.5V, VFB = 2.3V
-0.25
-0.5
-
mA
COMP VOH
VFB = 2.3V
4.25
4.4
5.0
V
COMP VOL
VFB = 2.7V
0.4
0.8
1.2
V
PSRR
Frequency = 120Hz (Note 10)
60
80
-
dB
SS Clamp, VCOMP
SS = 2.5V, VFB = 0V, ISET = 2V
2.4
2.5
2.6
V
289
318
347
kHz
OSCILLATOR
Frequency Accuracy
Frequency Variation with VCC
T = +105°C (f20V - f9V)/f9V
T = -40°C (f20V -f9V)/f9V
-
2
2
3
3
%
Temperature Stability
(Note 10)
-
8
-
%
Maximum Duty Cycle
(Note 12)
68
75
81
%
-
3.00
-
V
-
4.00
-
V
-
1.50
-
V
0.75
0.70
1.0
1.0
1.2
1.2
mA
-
-
2.5
V
25
-
-
ns
0.65 x Free
Running
(Period)
-
1.0
MHz
-
4.5
-
kΩ
Comparator High Threshold - Free Running
Comparator High Threshold - with External SYNC
(Note 10)
Comparator Low Threshold
Discharge Current
0°C to +105°C
-40°C to +105°C
SYNCHRONIZATION
Input High Threshold
Input Pulse Width
Input Frequency Range
(Note 10)
Input Impedance
VOH
RLOAD = 4.5kΩ
2.5
-
-
V
VOL
RLOAD = open
-
-
0.1
V
SYNC Advance
SYNC rising edge to GATE falling
edge, CGATE = CSYNC = 100pF
-
25
55
ns
7
FN6797.0
August 23, 2011
ISL6721A
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application
schematic on page 3 and page 4. 9V < VCC = VC < 20V, RT = 11kΩ, CT = 330 pF. Typical values are at
TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +105°C. (Continued)
PARAMETER
Output Pulse Width
MIN
(Note 9)
TYP
MAX
(Note 9)
UNITS
CSYNC = 100pF
50
-
-
ns
SS = 2V
-40
-55
-70
µA
4.26
4.50
4.74
V
30
40
55
µA
TEST CONDITIONS
SOFT-START
Charging Current
Charged Threshold Voltage
Initial Overcurrent Discharge Current
Sustained OC Threshold < SS <
Charged Threshold
Overcurrent Shutdown Threshold Voltage
Charged Threshold minus,
TA = +25°C
0.095
0.125
0.155
V
Fault Discharge Current
SS = 2V
0.25
1.0
-
mA
Reset Threshold Voltage
TA = +25°C
0.22
0.27
0.31
V
Charge Current
SLOPE = 2V, 0°C to +105°C
-40°C to +105°C
-45
-41
-53
-53
-65
-65
µA
Slope Compensation Gain
Fraction of slope voltage added to
ISENSE, TA = +25°C
0.097
-
0.103
V/V
Fraction of slope voltage added to
ISENSE
0.082
-
0.118
V/V
-
0.1
0.2
V
11.0
13.5
16.0
V
SLOPE COMPENSATION
VRTCT = 4.5V
Discharge Voltage
GATE OUTPUT
Gate Output Limit Voltage
VC = 20V, CGATE = 1nF,
IOUT = 0mA
Gate VOH
VC - GATE, VC = 10V,
IOUT = 150mA
-
1.5
2.2
V
Gate VOL
GATE - PGND, IOUT = 150mA
IOUT = 10mA
-
1.2
0.6
1.5
0.8
V
Peak Output Current
VC = 20V, CGATE = 1nF (Note 10)
-
1.0
-
A
Output “Faulted” Leakage
VC = 20V, UV = 0V, GATE = 2V
1.2
2.6
-
mA
Rise Time
VC = 20V, CGATE = 1nF
1V < GATE < 9V
-
60
100
ns
Fall Time
VC = 20V, CGATE = 1nF
1V < GATE < 9V
-
15
40
ns
Minimum ON time
ISET = 0.5V; VFB = 0V; VC = 11V
ISENSE to GATE w/10:1 Divider
RTCT = 4.75V through 1kΩ
(Note 10)
-
-
110
ns
Minimum ISET Voltage
-
-
0.35
V
Maximum ISET Voltage
1.2
-
-
V
OVERCURRENT PROTECTION
ISET Bias Current
VISET = 1.00V
-1.0
-
1.0
µA
Restart Delay
TA = +25°C
150
295
445
ms
Overvoltage Threshold
2.4
2.5
2.6
V
Undervoltage Fault Threshold
1.89
1.93
2.00
V
OV AND UV VOLTAGE MONITOR
8
FN6797.0
August 23, 2011
ISL6721A
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application
schematic on page 3 and page 4. 9V < VCC = VC < 20V, RT = 11kΩ, CT = 330 pF. Typical values are at
TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +105°C. (Continued)
PARAMETER
TEST CONDITIONS
MIN
(Note 9)
TYP
MAX
(Note 9)
UNITS
1.96
2.01
2.10
V
20
50
100
mV
Undervoltage Clear Threshold
Undervoltage Hysteresis Voltage
UV Bias Current
VUV = 2.10 V
-1.0
-
1.0
µA
OV Bias Current
VOV = 2.00 V
-1.0
-
1.0
µA
Thermal Shutdown
(Note 10)
120
130
140
°C
Thermal Shutdown Clear
(Note 10)
105
120
135
°C
Hysteresis
(Note 10)
-
10
-
°C
THERMAL PROTECTION
NOTES:
9. Parameters with MIN and/or MAX limits are 100% tested at 25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
10. This parameter, although guaranteed by characterization or correlation testing, is not 100% tested in production.
11. This is the VCC current consumed when the device is active but not switching. Does not include gate drive current.
12. This is the maximum duty cycle achievable using the specified values of RT and CT. Larger or smaller maximum duty cycles may be obtained
using other values for RT and CT. See Equations 1, 2, 3 and 4.
1.002
1.002
1.002
1.002
1.000
1
1.000
1
NORMALIZED
Normalized
VrefVREF
NORMALIZED
EA REFERENCE
Normalized
EA Reference
Typical Performance Curves
0.998
0.998
0.995
0.995
0.993
0.993
0.991
0.991
-40
-10
20
50
80
110
0.998
0.998
0.995
0.995
0.993
0.993
0.991
0.991
-40
-10
FIGURE 1. EA REFERENCE VOLTAGE vs TEMPERATURE
80
110
103
0.996
FREQUENCY (kHz)
NORMALIZED FREQUENCY
50
FIGURE 2. VREF REFERENCE VOLTAGE vs TEMPERATURE
1.002
0.989
0.983
0.976
0.970
-40
20
TEMPERATURE (°C)
TEMPERATURE (°C)
-10
20
50
80
110
TEMPERATURE (°C)
FIGURE 3. OSCILLATOR FREQUENCY vs TEMPERATURE
9
100pF
100
10
10
20
30
40
50 60 70
RT (kΩ)
80
220pF
330pF
470pF
680pF
1000pF
2000pF
90 100
FIGURE 4. RESISTANCE FOR CT CAPACITOR VALUES GIVEN
FN6797.0
August 23, 2011
ISL6721A
Pin Descriptions
SLOPE - Means by which the ISENSE ramp slope may be
increased for improved noise immunity or improved control
loop stability for duty cycles greater than 50%. An internal
current source charges an external capacitor to GND during
each switching cycle. The resulting ramp is scaled and
added to the ISENSE signal.
SYNC - A bidirectional synchronization signal used to
coordinate the switching frequency of multiple units.
Synchronization may be achieved by connecting the SYNC
signal of each unit together or by using an external master
clock signal. The oscillator timing capacitor, CT, is still
required, even if an external clock is used. The first unit to
assert this signal assumes control.
RTCT - This is the oscillator timing control pin. The
operational frequency and maximum duty cycle are set by
connecting a resistor, RT, between VREF and this pin and a
timing capacitor, CT, from this pin to LGND. The oscillator
produces a sawtooth waveform with a programmable
frequency range of 100kHz to 1.0MHz. The charge time, tC,
the discharge time, tD, the switching frequency, fsw, and the
maximum duty cycle, Dmax, can be calculated from
Equations 1, 2, 3 and 4:
t C ≈ 0.655 • R T • C T
(EQ. 1)
S
0.001 • R T – 3.6⎞
t D ≈ – R • C • LN ⎛ -----------------------------------------T
T
⎝ 0.001 • R T – 1.9⎠
1
f sw = ----------------tD + tC
S
Hz
(EQ. 2)
(EQ. 3)
Dmax = t C • f sw
(EQ. 4)
Figure 4 may be used as a guideline in selecting the
capacitor and resistor values required for a given frequency.
COMP - COMP is the output of the error amplifier and the
input of the PWM comparator. The control loop frequency
compensation network is connected between the COMP and
FB pins.
The ISL6721A features a built-in full cycle soft-start.
Soft-start is implemented as a clamp on the maximum
COMP voltage.
FB - Feedback voltage input connected to the inverting input
of the error amplifier. The non-inverting input of the error
amplifier is internally tied to a reference voltage. Current
sense leading edge blanking is disabled when the FB input
is less than 2.0V.
OV - Overvoltage monitor input pin. This signal is compared
to an internal 2.5V reference to detect an overvoltage
condition.
10
UV - Undervoltage monitor input pin. This signal is
compared to an internal 1.45V reference to detect an
undervoltage condition.
ISENSE - This is the input to the current sense comparators.
The IC has two current sensing comparators, a PWM
comparator for peak current mode control, and an
overcurrent protection comparator. The overcurrent
comparator threshold is adjustable through the ISET pin.
Exceeding the overcurrent threshold will start a delayed
shutdown sequence. Once an overcurrent condition is
detected, the soft-start charge current source is disabled and
a discharge current source is enabled. The soft-start capacitor
begins discharging, and if it discharges to less than 4.375V
(sustained overcurrent threshold), a shutdown condition
occurs and the GATE output is forced low. At this point a
reduced discharge current takes over until the soft-start
voltage reaches 0.27V (reset threshold). The GATE output
remains low until the reset threshold is attained. At this point,
a soft-start cycle begins.
If the overcurrent condition ceases, and then an additional
50µs period elapses before the shutdown threshold is
reached, no shutdown occurs and the soft-start voltage is
allowed to recharge.
LGND - LGND is a small signal reference ground for all
analog functions on this device.
PGND - This pin provides a dedicated ground for the output
gate driver. The LGND and PGND pins should be connected
externally using a short printed circuit board trace close to
the IC. This is imperative to prevent large, high frequency
switching currents flowing through the ground metallization
inside the IC. (Decouple VC to PGND with a low ESR 0.1µF
or larger capacitor.)
GATE - This is the device output. It is a high current power
driver capable of driving the gate of a power MOSFET with
peak currents of 1.0A. This GATE output is actively held low
when VCC is below the UVLO threshold.
The output high voltage is clamped to ~13.5V. Voltages
exceeding this clamp value should not be applied to the
GATE pin. The output stage provides very low impedance to
overshoot and undershoot.
VC - This pin is for separate collector supply to the output
gate drive. Separate VC and PGND helps decouple the IC’s
analog circuitry from the high power gate drive noise.
(Decouple VC to PGND with a low ESR 0.1µF or larger
capacitor.)
VCC - VCC is the power connection for the device. Although
quiescent current, ICC, is low, it is dependent on the
frequency of operation. To optimize noise immunity, bypass
VCC to LGND with a ceramic capacitor as close to the VCC
and LGND pins as possible.
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ISL6721A
The total supply current (IC plus ICC) will be higher,
depending on the load applied to GATE. Total current is the
sum of the quiescent current and the average gate current.
Knowing the operating frequency, fsw, and the MOSFET
gate charge, Qg, the average GATE output current can be
calculated in Equation 5:
Igate = Qg • f sw
A
(EQ. 5)
VREF - The 5V reference voltage output. Bypass to LGND
with a 0.01µF or larger capacitor to filter this output as
needed. Using capacitance less than this value may result in
unstable operation.
SS - Connect the soft-start capacitor between this pin and
LGND to control the duration of soft-start. The value of the
capacitor determines both the rate of increase of the duty
cycle during start-up, and also controls the overcurrent
shutdown delay.
ISET - A DC voltage between 0.35V and 1.2V applied to this
input sets the pulse-by-pulse overcurrent threshold. When
overcurrent inception occurs, the SS capacitor begins to
discharge and starts the overcurrent delayed shutdown
cycle.
Thermal Pad (QFN Package Only) - The thermal pad
located on the bottom of the QFN package is electrically
isolated. It is recommended that it be connected to signal
ground.
Functional Description
Features
The ISL6721A current mode PWMs make an ideal choice for
low-cost flyback and forward topology applications requiring
enhanced control and supervisory capability. With adjustable
overvoltage and undervoltage thresholds, overcurrent
threshold, and hic-cup delay, a highly flexible design with
minimal external components is possible. Other features
include peak current mode control, adjustable soft-start,
slope compensation, adjustable oscillator frequency and a
bi-directional synchronization clock input.
Oscillator
The ISL6721A have a sawtooth oscillator with a
programmable frequency range to 1MHz, which can be
programmed with a resistor and capacitor on the RTCT pin.
(Please refer to Figure 4 for the resistance and capacitance
required for a given frequency.)
Implementing Synchronization
The oscillator can be synchronized to an external clock
applied at the SYNC pin or by connecting the SYNC pins of
multiple ICs together. If an external master clock signal is
used, it must be at least 65% of the free running frequency of
the oscillator for proper synchronization. The external
master clock signal should have a pulse width greater than
20ns. If no master clock is used, the first device to assert
11
SYNC assumes control of the SYNC signal. An external
SYNC pulse is ignored if it occurs during the first 1/3 of the
switching cycle.
During normal operation the RTCT voltage charges from
1.5V to 3.0V and back during each cycle. Clock and SYNC
signals are generated when the 3.0V threshold is reached. If
an external clock signal is detected during the latter 2/3 of
the charging cycle, the oscillator switches to external
synchronization mode and relies upon the external SYNC
signal to terminate the oscillator cycle. The generation of a
SYNC signal is inhibited in this mode. If the RTCT voltage
exceeds 4.0V (i.e. no external SYNC signal terminates the
cycle), the oscillator reverts to the internal clock mode and a
SYNC signal is generated.
Soft-Start Operation
The ISL6721A features soft-start using an external capacitor
in conjunction with an internal current source. Soft-start is
used to reduce voltage stresses and surge currents during
start up.
Upon start up, the soft-start circuitry clamps the error amplifier
output (COMP pin) to a value proportional to the soft-start
voltage. The error amplifier output rises as the soft-start
capacitor voltage rises. This has the effect of increasing the
output pulse width from zero to the steady state operating duty
cycle during the soft-start period. When the soft-start voltage
exceeds the error amplifier voltage, soft-start is completed.
Soft-start forces a controlled output voltage rise. Soft-start
occurs during start-up and after recovery from a fault condition
or overcurrent shutdown. The soft-start voltage is clamped to
4.5V.
Gate Drive
The ISL6721A is capable of sourcing and sinking 1A peak
current. Separate collector supply (VC) and power ground
(PGnd) pins help isolate the IC’s analog circuitry from the
high power gate drive noise. To limit the peak current
through the IC, an external resistor may be placed between
the totem-pole output of the IC (GATE pin) and the gate of
the MOSFET. This small series resistor also damps any
oscillations caused by the resonant tank of the parasitic
inductances in the traces of the board and the FET’s input
capacitance.
Slope Compensation
For applications where the maximum duty cycle is less than
50%, slope compensation may be used to improve noise
immunity, particularly at lighter loads. The amount of slope
compensation required for noise immunity is determined
empirically, but is generally about 10% of the full scale
current feedback signal. For applications where the duty
cycle is greater than 50%, slope compensation is required to
prevent instability. Slope compensation is a technique in
which the current feedback signal is modified by adding
additional slope to it. The minimum amount of slope
compensation required corresponds to 1/2 the inductor
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ISENSE SIGNAL (V)
downslope. However, adding excessive slope compensation
results in a control loop that behaves more as a voltage
mode controller than as current mode controller (Figure 5).
CURRENT SENSE SIGNAL
Current Sense Signal
DOWNSLOPE
Downslope
Otherwise another shutdown cycle occurs. A UV condition
also results in a shutdown fault, but the device does not
enter the low power mode and no restart delay occurs when
the fault clears.
A resistor divider between VIN and LGND to each input
determines the operational thresholds. The UV threshold
has a fixed hysteresis of 75mV nominal.
Overcurrent Operation
TIME
Time
FIGURE 5. SLOPE COMPENSATION
The minimum amount of capacitance to place at the SLOPE
pin is calculated in Equation 6:
C SLOPE = 4.24 ×10
–6
t ON
• ----------------------V SLOPE
F
(EQ. 6)
where tON is the On time and VSLOPE is the amount of
voltage to be added as slope compensation to the current
feedback signal. In general, the amount of slope
compensation added is 2 to 3 times the minimum required.
Example:
Assume the inductor current signal presented at the ISENSE
pin decreases 125mV during the Off period, and:
Switching Frequency, fsw = 250kHz
Duty Cycle, D = 60%
tON = D/fsw = 0.6/250E3 = 2.4µs
tOFF = (1 - D)/fsw = 1.6µs
Determine the downslope:
Downslope = 0.125V/1.6µs = 78mV/µs. Now determine the
amount of voltage that must be added to the current sense
signal by the end of the On time (Equation 7).
1
V SLOPE = --- • 0.078 • 2.4 = 94mV
2
(EQ. 7)
–6
Overcurrent delayed shutdown is enabled once the soft-start
cycle is complete. If an overcurrent condition is detected, the
soft-start charging current source is disabled and the
discharging current source is enabled. The soft-start
capacitor is discharged at a rate of 40µA. At the same time,
a 50µs retriggerable one-shot timer is activated and it
remains active for 50µs after the overcurrent condition stops.
The soft-start discharge cycle cannot be reset until the oneshot timer becomes inactive. If the soft-start capacitor
discharges by more than 0.125V to 4.375V, the output is
disabled and the soft-start capacitor is discharged. The
output remains disabled and ICC drops to 200µA for
approximately 295ms. A new soft-start cycle is then initiated.
The shutdown and restart behavior of the OC protection is
often referred to as hic-cup operation due to its repetitive
start-up and shutdown characteristic.
If the overcurrent condition ceases at least 50µs prior to the
soft-start voltage reaching 4.375V, the soft-start charging
and discharging currents revert to normal operation and the
soft-start voltage is allowed to recover.
Hiccup OC protection may be defeated by setting ISET to a
voltage that exceeds the Error Amplifier current control
voltage, or about 1.5V.
Leading Edge Blanking
Therefore (Equation 8),
C SLOPE ( MIN ) = 4.24 ×10
The overcurrent threshold level is set by the voltage applied
at the ISET pin. Setting the overcurrent level may be
accomplished by using a resistor divider network from VREF
to LGND. The ISET threshold should be set at a level that
corresponds to the desired peak output inductor current plus
the additive effects of slope compensation.
–6
2.4 ×10
• ----------------------- ≈ 110pF
0.094
(EQ. 8)
An appropriate slope compensation capacitance for this
example would be 1/2 to 1/3 the calculated value, or
between 68pF and 33pF.
Overvoltage and Undervoltage Monitor
The OV and UV signals are inputs to a window comparator
used to monitor the input voltage level to the converter. If the
voltage falls outside of the user designated operating range,
a shutdown fault occurs. For OV faults, the supply current,
ICC, is reduced to 200µA for ~295ms at which time recovery
is attempted. If the fault is cleared, a soft-start cycle begins.
12
The initial 100ns of the current feedback signal input at
ISENSE is removed by the leading edge blanking circuitry.
The blanking period begins when the GATE output leading
edge exceeds 3.0V. Leading edge blanking prevents current
spikes from parasitic elements in the power supply from
causing false trips of the PWM comparator and the
overcurrent comparator.
Fault Conditions
A Fault condition occurs if VREF falls below 4.65V, the OV
input exceeds 2.50V, the UV input falls below 1.45V, or the
junction temperature of the die exceeds ~+130°C. When a
Fault is detected the GATE output is disabled, and the
soft-start capacitor is quickly discharged. When the Fault
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ISL6721A
condition clears and the soft-start voltage is below the reset
threshold, a soft-start cycle begins.
Ground Plane Requirements
Careful layout is essential for satisfactory operation of the
device. A good ground plane must be employed. A unique
section of the ground plane must be designated for high di/dt
currents associated with the output stage. Power ground
(PGND) can be separated from the logic ground (LGND) and
connected at a single point. VC should be bypassed directly
to PGND with good high frequency capacitors. The return
connection for input power and the bulk input capacitor
should be connected to the PGND ground plane.
Reference Design
The Typical Application Schematic on page 4 features the
ISL6721A in a conventional dual output 10W discontinuous
mode flyback DC/DC converter. The ISL6721EVAL1
demonstration unit implements this design and is available
for evaluation.
The input voltage range is from 36VDC to 75VDC, and the
two outputs are 3.3V @ 2.5A and 1.8V @ 1.0A. Cross
regulation is achieved using the weighted sum of the two
outputs.
Circuit Element Descriptions
The converter design may be broken down into the following
functional blocks:
Input Storage and Filtering Capacitance: C1, C2, C3
Isolation Transformer: T1
Primary voltage Clamp: CR6, R24, C18
Start Bias Regulator: R1, R2, R6, Q3, VR1
Operating Bias and Regulator: R25, Q2, D1, C5, CR2, D2
Main MOSFET Power Switch: Q1
Current Sense Network: R4, R3, R23, C4
Feedback Network:, R13, R15, R16, R17, R18, R19, R20,
R26, R27, C13, C14, U2, U3
Control Circuit:C7, C8, C9, C10, C11, C12, R5, R6, R8, R9,
R10, R11, R12, R14, R22
Output Rectification and Filtering: CR4, CR5, C15, C16, C19,
C20, C21, C22
VOUT(2): 1.8V @ 1.0A
VOUT(BIAS): 12V @ 50mA
POUT: 10W
Efficiency: 70%
Maximum Duty Cycle, DMAX: 0.45
Transformer Design
The design of a flyback transformer is a non-trivial affair. It is
an iterative process which requires a great deal of
experience to achieve the desired result. It is a process of
many compromises, and even experienced designers will
produce different designs when presented with identical
requirements. The iterative design process is not presented
here for clarity.
The abbreviated design process follows:
• Select a core geometry suitable for the application.
Constraints of height, footprint, mounting preference, and
operating environment will affect the choice.
• Select suitable core material(s).
• Select maximum flux density desired for operation.
• Select core size. Core size will be dictated by the
capability of the core structure to store the required
energy, the number of turns that have to be wound, and
the wire gauge needed. Often the window area (the space
used for the windings) and power loss determine the final
core size. For flyback transformers, the ability to store
energy is the critical factor in determining the core size.
The cross sectional area of the core and the length of the
air gap in the magnetic path determine the energy storage
capability.
• Determine maximum desired flux density. Depending on
the frequency of operation, the core material selected, and
the operating environment, the allowed flux density must
be determined. The decision of what flux density to allow
is often difficult to determine initially. Usually the highest
flux density that produces an acceptable design is used,
but often the winding geometry dictates a larger core than
is required based on flux density and energy storage
calculations.
• Determine the number of primary turns.
• Determine the turns ratio.
• Select the wire gauge for each winding.
Secondary Snubber: R21, C17
• Determine winding order and insulation requirements.
Design Criteria
• Verify the design.
The following design requirements were selected:
Input Power:
Switching Frequency, fsw: 200kHz
POUT/Efficiency = 14.3W (use 15W)
VIN: 36V to 75V
Max ON time: tON(MAX) = DMAX/fsw = 2.25µs
VOUT(1): 3.3V @ 2.5A
Average Input Current: IAVG(IN) = PIN/VIN(MIN) = 0.42A
13
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ISL6721A
lg = 1.56 • 10-3
Peak Primary Current (Equation 9):
2 • I AVG ( IN )
I PPK = ----------------------------------------- = 1.87
f sw • t ON ( MAX )
(EQ. 9)
A
μH
2
(EQ. 10)
Choose desired primary inductance to be 40µH.
The core structure must be able to deliver a certain amount
of energy to the secondary on each switching cycle in order
to maintain the specified output power (Equation 11).
〈 V OUT + Vd〉
Δw = P OUT • -----------------------------------f •V
sw
joules
OUT
(EQ. 11)
where Δw is the amount of energy required to be transferred
each cycle and Vd is the drop across the output rectifier.
The capacity of a gapped ferrite core structure to store
energy is dependent on the volume of the airgap and can be
expressed in Equation 12:
2 • μ o • Δw
Vg = Aeff • lg = ----------------------------2
ΔB
m
3
(EQ. 12)
where Aeff is the effective cross sectional area of the core in
m2, lg is the length of the airgap in meters, µo is the
permeability of free space (4π • 10-7), and ΔB is the change
in flux density in Tesla.
A core structure having less airgap volume than calculated will
be incapable of providing the full output power over some
portion of its operating range. On the other hand, if the length
of the airgap becomes large, magnetic field fringing around
the gap occurs. This has the effect of increasing the airgap
volume. Some fringing is usually acceptable, but excessive
fringing can cause increased losses in the windings around
the gap resulting in excessive heating. Once a suitable core
and gap combination are found, the iterative design cycle
begins. A design is developed and checked for ease of
assembly and thermal performance. If the core does not allow
adequate space for the windings, then a core with a larger
window area is required. If the transformer runs hot, it may be
necessary to lower the flux density (more primary turns, lower
operating frequency), select a less lossy core material,
change the geometry of the windings (winding order), use
heavier gauge wire or multi-filar windings, and/or change the
type of wire used (Litz wire, for example).
For simplicity, only the final design is further described.
An EPCOS EFD 20/10/7 core using N87 material gapped to
an AL value of 25nH/N2 was chosen. It has more than the
required air gap volume to store the energy required, but
was needed for the window area it provides.
Aeff = 31 • 10-6
m2
14
The flux density ΔB is only 0.069T or 690 gauss, a relatively
low value.
Since (Equation 13):
Maximum Primary Inductance (Equation 10):
V IN ( MIN ) • t ON ( MAX )
Lp ( max ) = --------------------------------------------------------- = 43.3
I PPK
m
μ o • N p • Aeff
L p = ---------------------------------------lg
(EQ. 13)
μH
the number of primary turns, Np, may be calculated. The
result is Np = 40 turns. The secondary turns may be
calculated as follows (Equation 14):
Ig • 〈 Vout + Vd〉 • tr
N s ≤ -------------------------------------------------------N p • Ippk • μ o • Aeff
(EQ. 14)
where tr is the time required to reset the core. Since
discontinuous MMF mode operation is desired, the core
must completely reset during the off time. To maintain
discontinuous mode operation, the maximum time allowed to
reset the core is tsw - tON(MAX) where tsw = 1/fsw. The
minimum time is application dependent and at the designers
discretion knowing that the secondary winding RMS current
and ripple current stress in the output capacitors increases
with decreasing reset time. The calculation for maximum Ns
for the 3.3 V output using t = tsw - tON (MAX) = 2.75µs is 5.52
turns.
The determination of the number of secondary turns is also
dependent on the number of outputs and the required turns
ratios required to generate them. If Schottky output rectifiers
are used and we assume a forward voltage drop of 0.45V,
the required turns ratio for the two output voltages, 3.3V and
1.8V, is 5:3.
With a turns ratio of 5:3 for the secondary windings, we will
use Ns1 = 5 turns and Ns2 = 3 turns. Checking the reset time
using these values for the number of secondary turns yields
a duration of Tr = 2.33µs or about 47% of the switching
period, an acceptable result.
The bias winding turns may be calculated similarly, only a
diode forward drop of 0.7V is used. The rounded off result is
17 turns for a 12V bias.
The next step is to determine the wire gauge. The RMS
current in the primary winding may be calculated using
Equation 15:
t ON ( MAX )
I P ( RMS ) = I PPK • -------------------------3 • t sw
A
(EQ. 15)
The peak and RMS current values in the remaining windings
may be calculated using Equations 16 and 17:
2 • I OUT • t sw
I SPK = ------------------------------------Tr
t sw
I RMS = 2 • I OUT • -------------3 • Tr
(EQ. 16)
A
A
(EQ. 17)
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The RMS current for the primary winding is 0.72A, for the
3.3V output, 4.23A, for the 1.8V output, 1.69A, and for the
bias winding, 85mA.
To minimize the transformer leakage inductance, the primary
was split into two sections connected in parallel and
positioned such that the other windings were sandwiched
between them. The output windings were configured so that
the 1.8V winding is a tap off of the 3.3V winding. Tapping the
1.8V output requires that the shared portion of the
secondary conduct the combined current of both outputs.
The secondary wire gauge must be selected accordingly.
The determination of current carrying capacity of wire is a
compromise between performance, size, and cost. It is
affected by many design constraints such as operating
frequency (harmonic content of the waveform) and the
winding proximity/geometry. It generally ranges between 250
and 1000 circular mils per ampere. A circular mil is defined
as the area of a circle 0.001” (1 mil) in diameter. As the
frequency of operation increases, the AC resistance of the
wire increases due to skin and proximity effects. Using
heavier gauge wire may not alleviate the problem. Instead
multiple strands of wire in parallel must be used. In some
cases, Litz wire is required.
conduction losses is complicated by the variation of rDS(ON)
with temperature. As junction temperature increases, so
does rDS(ON), which increases losses and raises the
junction temperature more, and so on. It is possible for the
device to enter a thermal runaway situation without proper
heatsinking. As a general rule of thumb, doubling the +25°C
rDS(ON) specification yields a reasonable value for
estimating the conduction losses at +125°C junction
temperature.
The switching losses have two components: capacitive
switching losses and voltage/current overlap losses. The
capacitive losses occur during turn on of the device and may
be calculated in Equation 19:
2
1
Pswcap = --- • Cfet • Vin • f sw
2
(EQ. 19)
where Cfet is the equivalent output capacitance of the
MOSFET. Device output capacitance is specified on
datasheets as Coss and is non-linear with applied voltage.
To find the equivalent discrete capacitance, Cfet, a charge
model is used. Using a known current source, the time
required to charge the MOSFET drain to the desired
operating voltage is determined and the equivalent
capacitance may be calculated in Equation 20:
Ichg • t
Cfet = -------------------V
The winding configuration selected is:
W
F
(EQ. 20)
Primary #1: 40T, 2 #30 bifilar
The internal spacing and insulation system was designed for
1500VDC dielectric withstand rating between the primary
and secondary windings.
The other component of the switching loss is due to the
overlap of voltage and current during the switching
transition. A switching transition occurs when the MOSFET
is in the process of either turning on or off. Since the load is
inductive, there is no overlap of voltage and current during
the turn on transition, so only the turn off transition is of
significance. The power dissipation may be estimated using
Equation 21:
Power MOSFET Selection
1
P sw ≈ --- • I PPK • V IN • t OL • f sw
x
Secondary: 5T, 0.003” (3 mil) copper foil tapped at 3T
Bias: 17T #32
Primary #2: 40T, 2 #30 bifilar
Selection of the main switching MOSFET requires
consideration of the voltage and current stresses that will be
encountered in the application, the power dissipated by the
device, its size, and its cost.
The input voltage range of the converter is 36VDC to
75VDC. This suggests a MOSFET with a voltage rating of
150V is required due to the flyback voltage likely to be seen
on the primary of the isolation transformer.
(EQ. 21)
where tOL is the duration of the overlap period and x ranges
from about 3 through 6 in typical applications and depends
on where the waveforms intersect. This estimate may predict
higher dissipation than is realized because a portion of the
turn off drain current is attributable to the charging of the
device output capacitance (Coss) and is not dissipative
during this portion of the switching cycle (Figure 6).
The losses associated with MOSFET operation may be
divided into three categories: conduction, switching, and
gate drive.
The conduction losses are due to the MOSFET’s ON
resistance (Equation 18).
Pcond = r DS ( ON ) • Iprms
2
W
(EQ. 18)
where rDS(ON) is the ON resistance of the MOSFET and
Iprms is the RMS primary current. Determining the
15
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August 23, 2011
ISL6721A
1.8V output: 50mV total output ripple and noise
ESR: 30mV
Ip p k
Capacitor ΔQ: 5mV
ESL: 15mV
For the 3.3V output (Equation 23):
V D -S
ΔV
0.060
ESR ≤ --------------------------------- = ----------------------------- = 7.3mΩ
I SPK – I OUT
10.73 – 2.5
Tol
FIGURE 6. SWITCHING CYCLE
The final component of MOSFET loss is caused by the
charging of the gate capacitance through the device gate
resistance. Depending on the relative value of any external
resistance in the gate drive circuit, a portion of this power will
be dissipated externally (Equation 22).
Pgate = Qg • Vg • f sw
(EQ. 22)
W
Once the losses are known, the device package must be
selected and the heatsinking method designed. Since the
design requires a small surface mount part, a 8 Ld SOIC
package was selected. A Fairchild FDS2570 MOSFET was
selected based on these criteria. The overall losses are
estimated at 400mW.
Output Filter Design
In a flyback design, the primary concern for the design of the
output filter is the capacitor ripple current stress and the
ripple and noise specification of the output.
The current flowing in and out of the output capacitors is the
difference between the winding current and the output current.
The peak secondary current, ISPK, is 10.73A for the 3.3V
output and 4.29A for the 1.8V output. The current flowing into
the output filter capacitor is the difference between the winding
current and the output current. Looking at the 3.3V output, the
peak winding current is ISPK = 10.73A. The capacitor must
store this amount minus the output current of 2.5A, or 8.23A.
The RMS ripple current in the 3.3V output capacitor is about
3.5ARMS. The RMS ripple current in the 1.8V output capacitor
is about 1.4ARMS.
Voltage deviation on the output during the switching cycle
(ripple and noise) is caused by the change in charge of the
output capacitance, the equivalent series resistance (ESR),
and equivalent series inductance (ESL). Each of these
components must be assigned a portion of the total ripple
and noise specification. How much to allow for each
contributor is dependent on the capacitor technology used.
For purposes of this discussion, we will assume the following:
3.3V output: 100mV total output ripple and noise
ESR: 60mV
(EQ. 23)
The change in voltage due to the change in charge of the
output capacitor, ΔQ, determines how much capacitance is
required on the output (Equation 24).
–6
( Ispk – Iout ) • Tr
( 10.73 – 2.5 ) • 2.33 ×10
C ≥ ---------------------------------------------- = ------------------------------------------------------------------- = 960μF
2 • 0.010
2 • ΔV
(EQ. 24)
ESL adds to the ripple and noise voltage in proportion to the
rate of change of current into the capacitor (V = L • di/dt)
(Equation 25).
–9
V • dt
0.030 • 200 ×10
L ≤ --------------- = ---------------------------------------------- = 0.56nH
10.73
di
(EQ. 25)
Capacitors having high capacitance usually do not have
sufficiently low ESL. High frequency capacitors such as
surface mount ceramic or film are connected in parallel with
the high capacitance capacitors to address the effects of
ESL. A combination of high frequency and high ripple
capability capacitors is used to achieve the desired overall
performance. The analysis of the 1.8V output is similar to
that of the 3.3V output and is omitted for brevity. Two
OSCON 4SEP560M (560µF) electrolytic capacitors and a
22µF X5R ceramic 1210 capacitor were selected for both the
3.3 and 1.8V outputs. The 4SEP560M electrolytic capacitors
are each rated at 4520mA ripple current and 13mΩ of ESR.
The ripple current rating of just one of these capacitors is
adequate, but two are needed to meet the minimum ESR
and capacitance values.
The bias output is of such low power and current that it
places negligible stress on its filter capacitor. A single 0.1µF
ceramic capacitor was selected.
Control Loop Design
The major components of the feedback control loop are a
programmable shunt regulator, an opto-coupler, and the
inverting amplifier of the ISL6721A. The opto-coupler is used
to transfer the error signal across the isolation barrier. The
opto-coupler offers a convenient means to cross the
isolation barrier, but it adds complexity to the feedback
control loop. It adds a pole at about 10kHz and a significant
amount of gain variation due the current transfer ratio (CTR).
The CTR of the opto-coupler varies with initial tolerance,
temperature, forward current, and age.
Capacitor ΔQ: 10mV
ESL: 30mV
16
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August 23, 2011
ISL6721A
A block diagram of the feedback control loop is shown in
Figure 7.
PRIMARY SIDE AMPLIFIER
REF +
POWER
STAGE
PWM
Z3
-
VOUT
Z4
ERROR AMPLIFIER
Z2
ISOLATION
+
Z1
signal in the control IC must be taken into account. The
maximum peak primary current was determined earlier to be
1.87A, so a choice of 2.25A peak primary current for current
limit is reasonable. A current gain, AEXT, of 0.5V/A was
selected to achieve this (Equation 26).
ISET = 2.25 • 0.8 • 0.5 + 0.100 = 1.00
(EQ. 26)
V
The control to output transfer function may be represented as
shown in Equation 27:
s
1 + -----vo
ωz
R o • L s • f sw
------ = K • --------------------------------- • ----------------vc
s
2
1 + ------ωp
(EQ. 27)
REF
If we ignore the current feedback sampled-data effects
(Equations 28 through 35):
FIGURE 7. FEEDBACK CONTROL LOOP
The loop compensation is placed around the Error Amplifier
(EA) on the secondary side of the converter. The primary
side amplifier located in the control IC is used as a unity gain
inverting amplifier and provides no loop compensation. A
Type 2 error amplifier configuration was selected as a
precaution in case operation in continuous mode should
occur at some operating point (Figure 8).
VOUT
I spk ( max )
K = -------------------------V c ( max )
(EQ. 28)
R o = LoadResis tan ce
(EQ. 29)
L s = SecondaryInduc tan ce
(EQ. 30)
2
ω p = -------------------Ro • Co
or
1
f p = ----------------------------π • Ro • Co
(EQ. 31)
1
ω z = -------------------Rc • Co
or
1
f z = -------------------------------------2 • π • Rc • Co
(EQ. 32)
C o = OutputCapaci tan ce
(EQ. 33)
R c = OutputCapaci tan ceE SR
(EQ. 34)
V c ( max ) = ControlVoltageRange
(EQ. 35)
VERROR
+
REF
FIGURE 8. TYPE 2 ERROR AMPLIFIER
Development of a small signal model for current mode
control is rather complex. The method of reference1 was
selected for its ability to accurately predict loop behavior. To
further simplify the analysis, the converter will be modeled as
a single output supply with all of the output capacitance
reflected to the 3.3V output. Once the “single” output system
is compensated, adjustments to the compensation will be
required based on actual loop measurements.
The first parameter to determine is the peak current
feedback loop gain. Since this application is low power, a
resistor in series with the source of the power switching
MOSFET is used for the current feedback signal. For higher
power applications, a resistor would dissipate too much
power and current transformer would be used instead.
There is limited flexibility to adjust the current loop behavior
due to the need to provide overcurrent protection. Current
limit and the current loop gain are determined by the current
sense resistor and the ISET threshold. ISET was set at 1.0V,
near its maximum, to minimize noise effects. When
determining ISET, the internal gain and offset of the ISENSE
17
The value of K may be determined by assuming all of the
output power is delivered by the 3.3V output at the threshold
of current limit. The maximum power allowed was
determined earlier as 15W, therefore (Equations 36, 37):
P out
–6
15
2 • ------------ • t sw
2 • -------- • 5 ×10
V out
3.3
I spk ( max ) = ------------------------------------ = ------------------------------------------ = 19.5
–6
Tr
2.33 ×10
(EQ. 36)
1
v c ( max ) = V ISENSE • A EXT • A CS • --------------------- = 2.93
A
V
(EQ. 37)
COMP
A
where AEXT is the external gain of the current feedback
network, ACS is the IC internal gain, and ACOMP is the gain
between the error amplifier and the PWM comparator.
The Type 2 compensation configuration has two poles and
one zero. The first pole is at the origin, and provides the
integration characteristic which results in excellent DC
regulation. Referring to the Typical Application Schematic on
FN6797.0
August 23, 2011
ISL6721A
C 13 + C 14
1
f pc = ------------------------------------------------------------ ≈ -------------------------------------------2 • π • R 15 • C 14 • C 13 2 • π • R 15 • C 14
(EQ. 38)
1
f zc = -------------------------------------------2 • π • R 15 • C 13
(EQ. 39)
A Bode plot of the closed loop system at low line, max load
appears in Figures 9A and 9B.
GAIN (dB)
page 4, the remaining pole and zero for the compensator are
located at (Equations 38, 39):
The ratio of R15 to the parallel combination of R17 and R18
determine the mid band gain of the error amplifier
(Equation 40).
R 15 • ( R 17 + R 18 )
A midband = -----------------------------------------------R 17 • R 18
50
40
30
20
10
0
-10
-20
-30
-40
-50
10k
100k
1M
10M
100M
10M
100M
FREQUENCY (Hz)
(EQ. 40)
FIGURE 9A. GAIN
The higher the desired bandwidth of the converter, the more
difficult it is to create a solution that is stable over the entire
operating range. A good rule of thumb is to limit the bandwidth
to about fsw/4. For this example, the bandwidth will be further
limited due to the low GBWP of the LM431-based Error
Amplifier and the opto-coupler. A bandwidth of approximately
5kHz was selected.
For the EA compensation, the first pole is placed at the
origin by default (C14 is an integrating capacitor). The first
zero is placed below the crossover frequency, fco, usually
around 1/3 fco. The second pole is placed at the lower of the
ESR zero or at one half of the switching frequency. The
midband gain is then adjusted to obtain the desired
crossover frequency. If the phase margin is not adequate,
the crossover frequency may have to be reduced.
Using this technique to determine the compensation, the
following values for the EA components were selected.
R17 = R18 = R15 = 1kΩ
R20 = open
200
PHASE MARGIN (°)
From Equation 27, it can be seen that the control to output
transfer function frequency dependence is a function of the
output load resistance, the value of output capacitance, and
the output capacitance ESR. These variations must be
considered when compensating the control loop. The worst
case small signal operating point for the converter is at
minimum VIN, maximum load, maximum COUT, and
minimum ESR.
150
100
50
0
-50
-100
10k
100k
1M
FREQUENCY (Hz)
FIGURE 9B. PHASE MARGIN
Regulation Performance
TABLE 1. OUTPUT LOAD REGULATION, VIN = 48V
IOUT (A), 3.3V
IOUT (A), 1.8V VOUT (V), 3.3V VOUT (V), 1.8V
0
0.030
3.351
1.825
0.39
0.030
3.281
1.956
0.88
0.030
3.251
1.988
1.38
0.030
3.223
2.014
1.87
0.030
3.204
2.029
2.39
0.030
3.185
2.057
2.89
0030
3.168
2.084
3.37
0.030
3.153
2.103
0
0.52
3.471
1.497
C13 = 100nF
0.39
0.52
3.283
1.800
C14 = 100pF
0.88
0.52
3.254
1.836
1.38
0.52
3.233
1.848
1.87
0.52
3.218
1.855
2.39
0.52
3.203
1.859
2.89
0.52
3.191
1.862
0
1.05
3.619
1.347
0.39
1.05
3.290
1.730
18
FN6797.0
August 23, 2011
ISL6721A
TABLE 1. OUTPUT LOAD REGULATION, VIN = 48V (Continued)
IOUT (A), 3.3V
IOUT (A), 1.8V VOUT (V), 3.3V VOUT (V), 1.8V
0.88
1.05
3.254
1.785
1.38
1.05
3.235
1.805
1.87
1.05
3.220
1.814
2.39
1.05
3.207
1.820
0
1.55
3.699
1.265
0.39
1.55
3.306
1.682
0.88
1.55
3.260
1.750
1.38
1.55
3.239
1.776
1.87
1.55
3.224
1.789
0
2.07
3.762
1.201
0.39
2.07
3.329
1.645
0.88
2.07
3.270
1.722
1.38
2.07
3.245
1.752
0
2.62
3.819
1.142
0.39
2.62
3.355
1.612
0.88
2.62
3.282
1.697
0
3.14
3.869
1.091
0.39
3.14
3.383
1.581
Waveforms
Typical waveforms can be found in Figures 10 through 12.
Figure 10 shows the steady state operation of the sawtooth
oscillator waveform at RTCT (Trace 2), the SYNC output
pulse (Trace 1), and the GATE output to the converter FET
(Trace 3). Figure 11 shows the converter behavior while
operating in an overcurrent fault condition. Trace 1 is the
soft-start voltage, which increases from 0V to 4.5V, at which
point the OC fault function is enabled. The OC condition is
detected and the soft-start capacitor is discharged to the
4.375V OC fault threshold at which point the IC enters the
fault shutdown mode. Trace 2 shows the behavior of the
timing capacitor voltage during a shutdown fault. Most of the
functions of the IC are de-powered during a fault, and the
oscillator is among those functions. During a fault, the IC is
turned off until the restart delay has timed out. After the
delay, power is restored and the IC resumes normal
operation. Trace 3 is the GATE output during the soft-start
cycle and OC fault.
NOTE:
Trace 1: SYNC Output
Trace 2: RTCT Sawtooth
Trace 3: GATE Output
FIGURE 10. TYPICAL WAVEFORMS
19
FN6797.0
August 23, 2011
ISL6721A
NOTE:
Trace 1: SS
Trace 2: RTCT Sawtooth
Trace 3: GATE Output
NOTE:
Trace 1: VD-S
Trace 3: VG-S
FIGURE 11. SOFT-START WITH OVERCURRENT FAULT
FIGURE 12. GATE AND DRAIN-SOURCE WAVEFORMS
Figure 12 shows the switching FET waveforms during
steady state operation. Trace 1 is drain-source voltage and
Trace 2 is gate-source voltage.
20
FN6797.0
August 23, 2011
ISL6721A
Component List
REFERENCE DESIGNATOR
VALUE
C1, C2, C3
1.0µF
Capacitor, 1812, X7R, 100V, 20%
C5, C13
0.1µF
Capacitor, 0603, X7R, 25V, 10%
C15, C16, C19, C20
560µF
Capacitor, Radial, SANYO 4SEP560M
C17
470pF
Capacitor, 0603, COG, 50V, 5%
C18
0.01µF
Capacitor, 0805, X7R, 50V, 10%
C21, C22
22µF
Capacitor, 1210, X5R, 10V, 20%
C4, C14
100pF
Capacitor, 0603, COG, 50V, 5%
C6
1500pF
Capacitor, Disc, Murata DE1E3KX152MA5BA01
C7
DESCRIPTION
0Ω Jumper, 0603
C8
330pF
Capacitor, 0603, COG, 50V, 5%
C9, C10, C11, C12
0.22µF
Capacitor, 0603, X7R, 16V, 10%
CR2, CR6
Diode, Fairchild ES1C
CR4, CR5
Diode, IR 12CWQ03FN
D1
Zener, 18V, Zetex BZX84C18
D2
Diode, Schottky, BAT54C
Q1
FET, Fairchild FDS2570
Q2
Transistor, Zetex FMMT491A
Q3
Transistor, ON MJD31C
R1, R2
1.00k
Resistor, 1206, 1%
R10
20.0k
Resistor, 0603, 1%
R7, R9, R11, R26, R27
10.0k
Resistor, 0603, 1%
R12
38.3k
Resistor, 0603, 1%
R13, R15, R17, R18, R19, R25
1.00k
Resistor, 0603, 1%
R14
10
Resistor, 0603, 1%
R16
165
Resistor, 0603, 1%
R21
10.0
Resistor, 1206, 1%
R22
5.11
Resistor, 0603, 1%
R24
3.92k
Resistor, 2512, 1%
R3, R23
100
Resistor, 0603, 1%
R4
1.00
Resistor, 2512, 1%
R5
221k
Resistor, 0603, 1%
R6
75.0k
Resistor, 0603, 1%
R8, R20
OMIT
T1
Transformer, MIDCOM 31555
U2
Opto-coupler, NEC PS2801-1
U3
Shunt Reference, National LM431BIM3
U4
PWM, Intersil ISL6721IB
VR1
Zener, 15V, Zetex BZX84C15
21
FN6797.0
August 23, 2011
ISL6721A
References
1. Ridley, R., “A New Continuous-Time Model for Current
Mode Control”, IEEE Transactions on Power Electronics,
Vol. 6, No. 2, April 1991.
2. Dixon, Lloyd H., “Closing the Feedback Loop”, Unitrode
Power Supply Design Seminar, SEM-700, 1990.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
22
FN6797.0
August 23, 2011
ISL6721A
Package Outline Drawing
M16.173
16 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 2, 5/10
A
1
3
5.00 ±0.10
SEE DETAIL "X"
9
16
6.40
PIN #1
I.D. MARK
4.40 ±0.10
2
3
0.20 C B A
1
8
B
0.65
0.09-0.20
END VIEW
TOP VIEW
1.00 REF
- 0.05
H
C
1.20 MAX
SEATING
PLANE
0.90 +0.15/-0.10
GAUGE
PLANE
0.25 +0.05/-0.06 5
0.10 M C B A
0.10 C
0°-8°
0.05 MIN
0.15 MAX
SIDE VIEW
0.25
0.60 ±0.15
DETAIL "X"
(1.45)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
(5.65)
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
3. Dimensions are measured at datum plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.08mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead
(0.65 TYP)
(0.35 TYP)
TYPICAL RECOMMENDED LAND PATTERN
is 0.07mm.
6. Dimension in ( ) are for reference only.
7. Conforms to JEDEC MO-153.
23
FN6797.0
August 23, 2011
ISL6721A
L16.3x3B
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 4/07
4X 1.5
3.00
12X 0.50
A
B
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
16
13
12
3.00
1
1 .70
+ 0.10
- 0.15
4
9
0.15
(4X)
5
8
0.10 M C A B
+ 0.07
4 16X 0.23 - 0.05
TOP VIEW
16X 0.40 ± 0.10
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0 . 90 ± 0.1
C
BASE PLANE
SEATING PLANE
0.08 C
( 2. 80 TYP )
SIDE VIEW
(
1. 70 )
( 12X 0 . 5 )
( 16X 0 . 23 )
C
0 . 2 REF
5
0 . 00 MIN.
0 . 05 MAX.
( 16X 0 . 60)
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
24
FN6797.0
August 23, 2011
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