DATASHEET

ISL6729
®
Data Sheet
December 1, 2005
Low-Cost Single-Ended Current-Mode
PWM for Microcontroller Based Power
Converters
The ISL6729 pulse width modulating (PWM) current mode
controller is designed for power conversion applications that
are based on a microcontroller or other device which can
generate a digital clock signal at the desired switching
frequency. Similar to the ISL684x family of products, the
ISL6729 provides the basic current mode PWM control
features, but eliminates the error amplifier, the oscillator, and
the reference. An external clock signal applied to the
oscillator input provides the time base and sets the
maximum duty cycle. The reduced feature set is ideal for
those applications where a microcontroller is available to
provide the monitor and control functions. The analog PWM
provides the cycle by cycle peak current mode control,
leaving the monitor and control overhead to the
microcontroller.
PART
MARKING
Features
• 5V Operation
• 1A MOSFET gate driver
• 400µA startup current
• 30ns propagation delay current sense to output
• Fast transient response with peak current mode control
• Switching frequency to 2MHz
• 20ns rise and fall times with 1nF output load
• Maximum Duty Cycle Determined by Clock Input Duty
Cycle
• Tight tolerance current limit threshold
• Pb-free plus anneal available (RoHS compliant)
Applications
• Telecom and Datacom Power
Ordering Information
PART
NUMBER
• Wireless Base Station Power
TEMP.
PKG.
RANGE (°C) PACKAGE DWG. #
• File Server Power
ISL6729IB
ISL6729IB
-40 to 105
8 Ld SOIC
M8.15
• Industrial Power Systems
ISL6729IBZ
(See Note)
6729IBZ
-40 to 105
8 Ld SOIC
(Pb-free)
M8.15
• PC Power Supplies
ISL6729IU
6729
-40 to 105
8 Ld MSOP M8.118
ISL6729IUZ
(See Note)
6729Z
-40 to 105
8 Ld MSOP M8.118
(Pb-free)
• Isolated Buck and Flyback Regulators
Add -T to part number for Tape and Reel packaging.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
PART NUMBER
RISING UVLO
MAX. DUTY CYCLE
ISL6729
4.75V
100%
1
FN9152.2
• Boost Regulators
Pinout
ISL6729 (8 LD SOIC, MSOP)
TOP VIEW
COMP
1
8
N/C
N/C
2
7
VDD
CS
3
6
OUT
CLKS
4
5
GND
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Functional Block Diagram
VDD
START/STOP
UV COMPARATOR
VDDOK
+
-
2
BG
+
-
GND
+
-
+
-
CS
100mV
PWM
COMPARATOR
OUT
ISL6729
2R
1.1V
CLAMP
COMP
R
CLK
S Q
R Q
FN9152.2
December 1, 2005
Typical Application - Interleaved Multi-Phase Isolated Converter
VOLTAGE FEEDBACK
ERROR
AMPLIFIER
5V
1 COMP
3
CLOCK φ1
ISOLATION
8
2
VDD 7
3 CS
OUT 6
POWER STAGE
VOUT
4 CLK GND 5
ISL6729
CURRENT FEEDBACK
1 COMP
MICROCONTROLLER
2
VDD 7
3 CS
OUT 6
POWER STAGE
ISL6729
CLOCK φ2
8
4 CLK GND 5
ISL6729
CURRENT FEEDBACK
1 COMP
2
8
VDD 7
POWER STAGE
3 CS OUT 6
CLOCK φ3
4 CLK GND 5
ISL6729
CURRENT FEEDBACK
FN9152.2
December 1, 2005
ISL6729
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +6.5V
OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VDD + 0.3V
Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 6.5V
Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1A
ESD Classification
Human Body Model (Per MIL-STD-883 Method 3015.7) . . .2000V
Charged Device Model (Per EOS/ESD DS5.3, 4/14/93) . . .1000V
Thermal Resistance (Typical, Note 1)
θJA (°C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100
MSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
130
Maximum Junction Temperature . . . . . . . . . . . . . . . . -55°C to 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(SOIC, MSOP- Lead Tips Only)
Operating Conditions
Temperature Range
ISL6729Ix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 105°C
Supply Voltage Range (Typical)
ISL6729 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75V-5.25V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. All voltages are with respect to GND.
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application
schematic. VDD = 5V, CLK = 50kHz, TA = -40 to 105°C (Note 3), Typical values are at TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
START Threshold
4.15
4.50
4.75
V
STOP Threshold
4.00
4.30
4.60
-
0.2
-
V
UNDERVOLTAGE LOCKOUT
Hysteresis
Start-Up Current, IDD
VDD < START Threshold
-
0.4
12
mA
Operating Current, IDD
(Note 4)
-
3.3
5.5
mA
Operating Supply Current, ID
Includes 1nF GATE loading
-
4.1
6.0
mA
-1.0
-
1.0
µA
CURRENT SENSE
Input Bias Current
VCS = 1V
CS Offset Voltage
VCS = 0V (Note 5)
95
100
105
mV
COMP to PWM Comparator Offset Voltage
VCS = 0V (Note 5)
0.80
1.15
1.30
V
0.91
0.97
1.03
V
2.5
3.0
3.5
V/V
-
25
40
ns
Input High Voltage Level, VIH
-
2.8
-
V
Input Low Voltage Level, VIL
-
2.7
-
V
(Note 5)
2
-
-
MHz
Gate VOH
VDD - OUT, IOUT = -200mA
-
1.0
2.0
V
Gate VOL
OUT - GND, IOUT = 200mA
-
1.0
2.0
V
Peak Output Current
COUT = 1nF (Note 5)
1.0
-
-
A
Rise Time
COUT = 1nF (Note 5)
-
20
40
ns
Fall Time
COUT = 1nF (Note 5)
-
20
40
ns
CS Input Signal, Maximum
Gain, ACS = ∆VCOMP/∆VCS
0 < VCS < 910mV, VFB = 0V. (Note 5)
CS to OUT Delay
(Note 5)
CLOCK
Maximum Clock Rate
OUTPUT
4
FN9152.2
December 1, 2005
ISL6729
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application
schematic. VDD = 5V, CLK = 50kHz, TA = -40 to 105°C (Note 3), Typical values are at TA = 25°C (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Maximum Duty Cycle
-
99
-
%
Minimum Duty Cycle
-
-
0
%
PWM
NOTES:
3. Specifications at -40°C are guaranteed by design, not production tested.
4. This is the VDD current consumed when the device is active but not switching. Does not include gate drive current.
5. Guaranteed by design, not 100% tested in production.
Pin Descriptions
Ground Plane Requirements
CLK - This is the oscillator timing control pin. The
operational frequency and maximum duty cycle are set by
applying a 5V amplitude clock signal to CLK. The logic high
duration defines the maximum ON time for the output. A
maximum clock rate up to 2.0MHz is possible.
Careful layout is essential for satisfactory operation of the
device. A good ground plane must be employed. A unique
section of the ground plane must be designated for high di/dt
currents associated with the output stage. VDD should be
bypassed directly to GND with good high frequency
capacitors.
COMP - COMP is the input to the PWM comparator and is
typically controlled through an external error amplifier.
CS - This is the current sense input to the PWM comparator.
The range of the input signal is nominally 0 to 1.0V and has
an internal offset of 100mV.
GND - GND is the power and small signal reference ground
for all functions.
OUT - This is the drive output to the power switching device.
It is a high current output capable of driving the gate of a
power MOSFET with peak currents of 1.0A. This GATE
output is actively held low when VDD is below the UVLO
threshold.
VDD - VDD is the 5V power connection for the IC. The IC will
operate from 4.75V to 5.25V. However, the accuracy of the
voltage clamp on the COMP signal, which determines the
over current threshold, is dependent on the accuracy of
VDD. A tight tolerance on VDD will result in a tight over
current threshold.
The total supply current will depend on the load applied to
OUT. Total IDD current is the sum of the operating current
and the average output current. Knowing the operating
frequency, f, and the MOSFET gate charge, Qg, the average
output current can be calculated from:
I OUT = Qg × f
(EQ. 1)
To optimize noise immunity, bypass VDD to GND with a
ceramic capacitor as close to the VDD and GND pins as
possible.
5
Applications Information
Microcontrollers are becoming more popular for monitoring
and supervisory functions in power converters due to their
flexibility, capability, and declining prices. Many applications
would like to take advantage of this flexibility and use them
to perform the control loop function as well. There are many
examples of voltage mode control using digital signal
processing techniques. However, microcontrollers available
today do not have the execution speed required for peak
current mode control at the operational frequencies of
modern switch-mode power supplies. As such, they are
unable to detect the peak current and terminate the
switching cycle within the few nanosecond window required.
The ISL6729 provides the analog circuitry required to
perform peak current control, but delegates the oscillator
function to the microcontroller. This arrangement allows the
microcontroller to control soft-start, maximum duty cycle,
and operational frequency of the power converter, as well as
performing the traditional overhead functions such as fault
monitoring and system interface.
Application of the ISL6729 is similar to the ISL684x family of
PWM converters except that the input bias voltage has been
changed to 5V and the oscillator, reference, and error
amplifier functions have been removed. An external digital
clock signal, such as the PWM output of a microcontroller,
must be supplied to control the frequency and maximum
duty cycle. The frequency of the applied clock signal and the
frequency of operation of the PWM are identical. The duty
cycle of the clock is the maximum duty cycle of the PWM.
Soft-start may be accomplished by incrementing the duty
cycle of the applied clock signal from zero to the maximum
desired value in a time frame appropriate for the application.
FN9152.2
December 1, 2005
ISL6729
The Typical Application block diagram illustrates how the
ISL6729 may be used for an interleaved power converter. In
this example, three clock signals of equal duty cycle, but
phased 120º apart, are applied to separate power stages.
Each phase shares a common voltage feedback signal, but
uses separate current feed back signals from each power
stage for regulation. Excellent current sharing behavior is
assured since each phase must produce the same peak
current. Accuracy is determined by the variation of the
output inductor value and the feedback components.
Multiple output power supplies can be created in a similar
fashion. Only one clock signal is required if in-phase
operation is desired. Each stage may be independently
controlled using separate voltage and current feedback
loops.
6
FN9152.2
December 1, 2005
ISL6729
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
N
INDEX
AREA
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
0.25(0.010) M
H
B M
INCHES
E
SYMBOL
-B1
2
A
3
L
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
B S
MIN
MAX
MIN
MAX
NOTES
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.1890
0.1968
4.80
5.00
3
E
0.1497
0.1574
3.80
4.00
4
e
α
0.050 BSC
-
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
α
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
1.27 BSC
H
N
NOTES:
MILLIMETERS
8
0°
1.27
8
8°
0°
6
7
8°
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
7
FN9152.2
December 1, 2005
ISL6729
Mini Small Outline Plastic Packages (MSOP)
N
M8.118 (JEDEC MO-187AA)
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1
INCHES
E
-B-
INDEX
AREA
1 2
0.20 (0.008)
A B C
TOP VIEW
4X θ
0.25
(0.010)
R1
R
GAUGE
PLANE
SEATING
PLANE -CA
4X θ
A2
A1
b
-H-
0.10 (0.004)
L
SEATING
PLANE
C
MIN
MAX
MIN
MAX
NOTES
A
0.037
0.043
0.94
1.10
-
A1
0.002
0.006
0.05
0.15
-
A2
0.030
0.037
0.75
0.95
-
b
0.010
0.014
0.25
0.36
9
c
0.004
0.008
0.09
0.20
-
D
0.116
0.120
2.95
3.05
3
E1
0.116
0.120
2.95
3.05
4
0.026 BSC
0.20 (0.008)
C
C
a
SIDE VIEW
CL
E1
0.20 (0.008)
C D
-
0.187
0.199
4.75
5.05
-
L
0.016
0.028
0.40
0.70
6
0.037 REF
N
-A-
0.65 BSC
E
L1
e
D
SYMBOL
e
L1
MILLIMETERS
0.95 REF
8
R
0.003
R1
0
α
-
8
-
0.07
0.003
-
5o
15o
0o
6o
7
-
-
0.07
-
-
5o
15o
-
0o
6o
-B-
Rev. 2 01/03
END VIEW
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. - H - Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (0.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Datums -A -H- .
and - B - to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only.
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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8
FN9152.2
December 1, 2005
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