DATASHEET

DATASHEET
Advanced Double-Ended PWM Controller
ISL6742
Features
The ISL6742 is a high-performance double-ended PWM
controller with advanced synchronous rectifier control and
current limit features. It is suitable for both current- and
voltage-mode control methods.
• Synchronous rectifier control outputs with adjustable
delay/advance
The ISL6742 includes complemented PWM outputs for
Synchronous Rectifier (SR) control. The complemented
outputs may be dynamically advanced or delayed relative to
the main outputs using an external control voltage.
• Adjustable average current signal
• 3% Tolerance cycle-by-cycle peak current limit
• Fast current sense to output delay
• Adjustable oscillator frequency up to 2MHz
• Adjustable dead time control
Its advanced current sensing circuitry employs sample and
hold methods to provide a precise average current signal.
Suitable for average current limiting, a technique which
virtually eliminates the current tail-out common to peak
current limiting methods, it is also applicable to current
sharing circuits and average current-mode control.
• Voltage- or current-mode operation
This advanced BiCMOS design features an adjustable oscillator
frequency up to 2MHz, internal over-temperature protection,
precision dead time control, and short propagation delays.
Additionally, multipulse suppression ensures alternating output
pulses at low duty cycles where pulse skipping may occur.
• 175µA start-up current
ISL6742AAZA
PART
MARKING
TEMP. RANGE
(°C)
ISL 6742AAZ
-40 to +105
• Tight tolerance error amplifier reference over line, load, and
temperature
• Supply UVLO
• Adjustable soft-start
• 70ns leading edge blanking
• Multipulse suppression
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
• Separate RAMP and CS inputs for voltage feed-forward or
current-mode applications
• Internal over-temperature protection
PACKAGE
(RoHS
Compliant)
• Pb-Free (RoHS compliant)
PKG.
DWG. #
16 Ld QSOP M16.15A
NOTES:
1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on
reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pbfree material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is
RoHS compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free
peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
Applications
• Half-bridge, full-bridge, interleaved forward, and push-pull
converters
• Telecom and datacom power
• Wireless base station power
• File server power
• Industrial power systems
Pin Configuration
ISL6742
(16 LD QSOP)
TOP VIEW
3. For Moisture Sensitivity Level (MSL), please see product information
page for ISL6742. For more information on MSL, please see tech brief
TB363
VREF 1
16 SS
VERR 2
15 VADJ
RTD 3
CT 4
13 OUTA
FB 5
12 OUTB
RAMP 6
11 OUTAN
CS 7
10 OUTBN
IOUT 8
December 3, 2015
FN9183.3
1
14 VDD
9 GND
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2005, 2008, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
Submit Document Feedback
Functional Block Diagram
VDD
OUTA
VDD
OUTB
VREF
DELAY/
ADVANCE
TIMING
CONTROL
PWM
STEERING
LOGIC
UVLO
OUTAN
2
OVERTEMPERATURE
PROTECTION
OUTBN
VADJ
GND
SAMPLE
AND
HOLD
VREF
IOUT
CS
+
-
4X
1.00V
+70ns
LEADING
EDGE
BLANKING
OVERCURRENT
COMPARATOR
RTD
OSCILLATOR
VREF
PWM
COMPARATOR
VREF
80mV
1 mA
+
0.33
SS
SOFT-START
CONTROL
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM
VERR
+
-
0.6V
FB
ISL6742
RAMP
CT
FN9183.3
December 3, 2015
Submit Document Feedback
Typical Applications
L1
VIN+
Q3
Q1
Q5
+VOUT
+
C16
C22
C2
T1
C15
C23
R16
RTN
R13
C1
Q4
3
T2
Q2
R1
Q6
R17
EL7212
C17
R15
R25
CR
3
U5
U6
C7
C3
EL7212
CR4
R9
36V TO 75V
C18
T3
C14
CR2
CR1
U1
HIP2100
U2
ISL6742
C13
VIN-
R3
R2
R5
C8
VR1
C6
R22
R23
R20
R21
R10
C9
C12
C11
C10
C19
C20
R18
R11
R6
R4
R19
1 VREF
SS 16
2 VERR
VADJ 15
3 RTD
VDD 14
4 CT
OUTA 13
5 FB
OUTB 12
6 RAMP OUTAN 11
7 CS
OUTBN 10
8 IOUT
GND 9
R12
FIGURE 2. TELECOM PRIMARY SIDE CONTROL HALF-BRIDGE CONVERTER WITH SYNCHRONOUS RECTIFICATION
C21
U3
VR
2
U4
TL431
R24
ISL6742
+VOUT
C5
Q7
C24
R7
VDD LO
HB VSS
HO LI
HS HI
C4
R14
R8
FN9183.3
December 3, 2015
Submit Document Feedback
Typical Applications (Continued)
VIN+
Q1
Q5A
Q5B
R13
CR4
CR3
T3
C9
R14
Q6A
Q6B
Q2
C10
T1
R16
4
R15
+ VOUT
L1
Q16
C20
C19
400 VDC
+
C21 +
C11
C1
R17
Q4
Q7A
Q7B
R12
CR5
CR6
R11
C8
Q12A
Q12B
1
2
3
4
5
6
7
8
R21
C12
R9
R7
R6
Q13A
Q13B
R8
VREF
VERR
RTD
CT
FB
RAMP
CS
IOUT
SS 16
VADJ15
VDD14
OUTA 13
OUTB 12
OUTAN11
OUTBN 10
GND 9
R20
ISL6742
CR2
RETURN
R10
T2
CR1
C18
ISL6742
C6
VREF
Q15
Q3
C7
Q11A
Q11B
VIN-
Q8A
Q8B
Q15
Q14A
Q14B
C17
C16
U1
CR7
C3
SECONDARY
BIAS
SUPPLY
C13
VREF
R22
C4
C2
R5
R2
R3
R18
R4
C5
C14
C15
FN9183.3
December 3, 2015
FIGURE 3. HIGH VOLTAGE INPUT SECONDARY SIDE CONTROL FULL-BRIDGE CONVERTER
R23
U3
+
C22
R19
ISL6742
Absolute Maximum Ratings (Note 5)
Thermal Information
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +20.0V
OUTxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VDD
Signal Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VREF + 0.3V
VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to 6.0V
Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.1A
Thermal Resistance Junction to Ambient (Typical)
JA (°C/W)
100
16 Lead QSOP (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C
Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . . . . . 9VDC to 16 VDC
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. All voltages are with respect to GND.
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to Figures 1, 2, and 3. 9V < VDD < 20V,
RTD = 10.0kΩ, CT = 470pF, TA = -40°C to +105°C, Typical values are at TA = +25°C.
PARAMETER
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
-
-
20
V
SUPPLY VOLTAGE
Supply Voltage
Start-Up Current, IDD
VDD = 5.0V
-
175
400
µA
Operating Current, IDD
RLOAD, COUT = 0
-
7.5
12.0
mA
UVLO START Threshold
8.00
8.75
9.00
V
UVLO STOP Threshold
6.50
7.00
7.50
V
-
1.75
-
V
4.850
5.000
5.150
V
-
3
-
mV
-10
-
-
mA
5
-
-
mA
VREF = 4.85V
-15
-
-100
mA
Current Limit Threshold
VERR = VREF
0.97
1.00
1.03
V
CS to OUT Delay
Excl. LEB (Note 7)
-
35
50
ns
Leading Edge Blanking (LEB) Duration
(Note 7)
50
70
100
ns
CS to OUT Delay + LEB
TA = +25°C
-
-
130
ns
CS Sink Current Device Impedance
VCS = 1.1V
-
-
20
Ω
Input Bias Current
VCS = 0.3V
-1.0
-
1.0
µA
IOUT Sample and Hold Buffer Amplifier Gain
TA = +25°C
4.00
4.09
4.15
V/V
IOUT Sample and Hold VOH
VCS = 1.00V, ILOAD = -300µA
3.9
-
-
V
IOUT Sample and Hold VOL
VCS = 0.00V, ILOAD = 10µA
-
-
0.3
V
RAMP Sink Current Device Impedance
VRAMP = 1.1V
-
-
20
Ω
RAMP to PWM Comparator Offset
TA = +25°C
65
80
95
mV
Hysteresis
REFERENCE VOLTAGE
Overall Accuracy
IVREF = 0mA to -10mA
Long Term Stability
TA = +125°C, 1000 hours (Note 7)
Operational Current (Source)
Operational Current (Sink)
Current Limit
CURRENT SENSE
RAMP
Submit Document Feedback
5
FN9183.3
December 3, 2015
ISL6742
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to Figures 1, 2, and 3. 9V < VDD < 20V,
RTD = 10.0kΩ, CT = 470pF, TA = -40°C to +105°C, Typical values are at TA = +25°C. (Continued)
PARAMETER
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
Bias Current
VRAMP = 0.3V
-5.0
-
-2.0
µA
Clamp Voltage
(Note 7)
6.5
-
8.0
V
SS = 3V
-60
-70
-80
µA
4.410
4.500
4.590
V
10
-
-
mA
0.23
0.27
0.33
V
SOFT-START
Charging Current
SS Clamp Voltage
SS Discharge Current
SS = 2V
Reset Threshold Voltage
TA = +25°C
ERROR AMPLIFIER
Input Common-Mode (CM) Range
(Note 7)
0
-
VREF
V
GBWP
(Note 7)
5
-
-
MHz
VERR VOL
ILOAD = 2mA
-
-
0.4
V
VERR VOH
ILOAD = 0mA
4.20
-
-
V
VERR Pull-Up Current Source
VERR = 2.50V
0.8
1.0
1.3
mA
EA Reference
TA = +25°C
0.594
0.600
0.606
V
0.590
0.600
0.612
V
EA Reference + EA Input Offset Voltage
PULSE WIDTH MODULATOR
Minimum Duty Cycle
VERR < 0.6V
-
-
0
%
Maximum Duty Cycle (Per Half-cycle)
VERR = 4.20V, VRAMP = 0V,
VCS = 0V (Note 8)
-
94
-
%
RTD = 2.00kΩ, CT = 220pF
-
97
-
%
RTD = 2.00kΩ, CT = 470pF
-
99
-
%
0.85
-
1.20
V
0.7
0.8
0.9
V
0.31
0.33
0.35
V/V
(Note 7)
0
-
4.45
V
(Note 7)
165
183
201
kHz
-10
-
+10
%
Zero Duty Cycle VERR Voltage
VERR to PWM Comparator Input Offset
TA = +25°C
VERR to PWM Comparator Input Gain
Common-Mode (CM) Input Range
OSCILLATOR
Frequency Accuracy, Overall
Frequency Variation with VDD
TA = +25°C, (F20V- - F10V)/F10V
-
0.3
1.7
%
Temperature Stability
VDD = 10V, |F-40°C - F0°C|/F0°C
(Note 7)
-
4.5
-
%
|F0°C - F105°C|/F25°C
(Note 7)
-
1.5
-
%
TA = +25°C, VCS = 1.8V
-193
-200
-207
µA
19
21
23
µA/µA
Charge Current
Discharge Current Gain
CT Valley Voltage
Static Threshold
0.75
0.80
0.88
V
CT Peak Voltage
Static Threshold
2.75
2.80
2.88
V
CT Peak-to-Peak Voltage
Static Value
1.92
2.00
2.05
V
1.97
2.00
2.03
V
RTD Voltage
Submit Document Feedback
6
FN9183.3
December 3, 2015
ISL6742
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to Figures 1, 2, and 3. 9V < VDD < 20V,
RTD = 10.0kΩ, CT = 470pF, TA = -40°C to +105°C, Typical values are at TA = +25°C. (Continued)
PARAMETER
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
OUTPUT
High Level Output Voltage (VOH)
IOUT = -10mA, VDD - VOH
-
0.5
1.0
V
Low Level Output Voltage (VOL)
IOUT = 10mA, VOL - GND
-
0.5
1.0
V
Rise Time
COUT = 220pF, VDD = 15V (Note 7)
-
110
200
ns
Fall Time
COUT = 220pF, VDD = 15V (Note 7)
-
90
150
ns
UVLO Output Voltage Clamp
VDD = 7V, ILOAD = 1mA (Note 9)
-
-
1.25
V
Output Delay/Advance Range
OUTAN/OUTBN Relative to OUTA/OUTB
VADJ = 2.50V (Note 7)
-
-
3
ns
VADJ < 2.425V
-40
-
-300
ns
VADJ > 2.575V
40
-
300
ns
Delay Control Voltage Range
OUTAN/OUTBN Relative to OUTA/OUTB
OUTxN Delayed
2.575
-
5.000
V
0
-
2.425
V
VADJ Delay Time
TA = +25°C (OUTx Delayed) (Note 10)
VADJ = 0
280
300
320
ns
VADJ = 0.5V
92
105
118
ns
VADJ = 1.0V
61
70
80
ns
VADJ = 1.5V
48
55
65
ns
VADJ = 2.0V
41
50
58
ns
VADJ = VREF
280
300
320
ns
VADJ = VREF - 0.5V
86
100
114
ns
VADJ = VREF - 1.0V
59
68
77
ns
VADJ = VREF - 1.5V
47
55
62
ns
VADJ = VREF - 2.0V
41
48
55
ns
(Note 7)
130
140
150
°C
Thermal Shutdown Clear
(Note 7)
115
125
135
°C
Hysteresis, Internal Protection
(Note 7)
-
15
-
°C
OUTx Delayed
TA = +25°C (OUTxN Delayed)
THERMAL PROTECTION
Thermal Shutdown
NOTES:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
7. Limits established by characterization and are not production tested.
8. This is the maximum duty cycle achievable using the specified values of RTD and CT. Larger or smaller maximum duty cycles may be obtained using
other values for these components. See Equations 1 through 3.
9. Adjust VDD below the UVLO stop threshold prior to setting at 7V.
10. When OUTx is delayed relative to OUTLxN (VADJ < 2.425V), the delay duration as set by VADJ should not exceed 90% of the CT discharge time (dead
time) as determined by CT and RTD.
Submit Document Feedback
7
FN9183.3
December 3, 2015
ISL6742
Typical Performance Curves
25
CT DISCHARGE CURRENT GAIN
NORMALIZED VREF
1.02
1.01
1.00
0.99
0.98
-40
-25
-10
5
20
35
50
65
80
95
24
23
22
21
20
19
18
110
0
TEMPERATURE (°C)
600
800
1000
FIGURE 5. CT DISCHARGE CURRENT GAIN vs RTD CURRENT
1•104
1•103
FREQUENCY (kHz)
DEAD TIME (ns)
400
RTD CURRENT (µA)
FIGURE 4. REFERENCE VOLTAGE vs TEMPERATURE
1•103
CT =
1000pF
680pF
470pF
330pF
220pF
100pF
100
10
200
0
10
20
30
40
50
60
RTD (kΩ)
70
80
FIGURE 6. DEAD TIME (DT) vs CAPACITANCE
Submit Document Feedback
8
90
100
100
10
0.1
RTD=
10kΩ
50kΩ
100kΩ
1
CT (nF)
10
FIGURE 7. CAPACITANCE vs FREQUENCY
FN9183.3
December 3, 2015
ISL6742
Pin Descriptions
VDD - VDD is the power connection for the IC. To optimize
noise immunity, bypass VDD to GND with a 0.1µF or larger high
frequency ceramic capacitor as close to the VDD and GND pins
as possible.
VDD is monitored for supply voltage Undervoltage Lockout
(UVLO). The start and stop thresholds track each other
resulting in relatively constant hysteresis.
GND - Signal and power ground connections for this device.
Due to high peak currents and high frequency operation, a low
impedance layout is necessary. Ground planes and short
traces are highly recommended.
VREF - The 5V reference voltage output having 3% tolerance
over line, load and operating temperature. Bypass to GND with
a 0.1µF to 2.2µF low ESR capacitor.
CT - The oscillator timing capacitor is connected between this
pin and GND. It is charged through an internal 200µA current
source and discharged with a user adjustable current source
controlled by RTD.
RTD - This is the oscillator timing capacitor discharge current
control pin. The current flowing in a resistor connected
between this pin and GND determines the magnitude of the
current that discharges CT. The CT discharge current is
nominally 20x the resistor current. The PWM dead time is
determined by the timing capacitor discharge duration. The
voltage at RTD is nominally 2V. The minimum recommended
value of RTD is 2.00kΩ.
CS - This is the input to the overcurrent comparator and the
average current sample and hold circuit. The overcurrent
comparator threshold is set at 1V nominal. The CS pin is
shorted to GND at the termination of either PWM output.
Depending on the current sensing source impedance, a series
input resistor may be required due to the delay between the
internal clock and the external power switch. This delay may
result in CS being discharged prior to the power switching
device being turned off.
OUTA and OUTB - These paired outputs are the pulse width
modulated outputs for controlling the switching FETs in
alternate sequence.
OUTAN and OUTBN - These outputs are the complements of
OUTA and OUTB, respectively. These outputs are suitable for
control of synchronous rectifiers. The phase relationship
between each output and its complement is set by a control
voltage applied to VADJ.
VADJ - A 0V to 5V control voltage applied to this input sets the
relative delay or advance between OUTA/OUTB and
OUTAN/OUTBN.
The range of phase delay/advance is either zero or 40ns to
300ns with the phase differential increasing as the voltage
deviation from 2.5V increases. The relationship between the
control voltage and phase differential is non-linear. The gain
(t/V) is low for control voltages near 2.5V and rapidly
increases as the voltage approaches the extremes of the
control range. This behavior provides the designer increased
accuracy when selecting a shorter delay/advance duration.
When the PWM outputs are delayed relative to the SR outputs
(VADJ < 2.425V), the delay time should not exceed 90% of the
dead time as determined by RTD and CT.
IOUT - Output of the 4x buffer amplifier of the sample and
hold circuitry that captures and averages the CS signal.
RAMP - This is the input for the sawtooth waveform for the
PWM comparator. The RAMP pin is shorted to GND at the
termination of the PWM signal. A sawtooth voltage waveform
is required at this input. For current-mode control this pin is
connected directly to CS and the current loop feedback signal
is applied to both inputs. For voltage-mode control, the
oscillator sawtooth waveform may be buffered and used to
generate an appropriate signal, or RAMP may be connected to
the input voltage through an RC network for voltage feed
forward control, or RAMP may be connected to VREF through
an RC network to produce the desired sawtooth waveform.
FB - FB is the inverting input to the Error Amplifier (EA). The
amplifier may be used as the error amplifier for voltage
feedback or used as the average current limit amplifier (IEA). If
the amplifier is not used, FB should be grounded.
VERR - The VERR pin is the output of the error amplifier and
controls the inverting input of the PWM comparator. Feedback
compensation components connect between VERR and FB.
There is a nominal 1mA pull-up current source connected to
VERR. Soft-start is implemented as a voltage clamp on the
VERR signal.
The outputs, OUTA and OUTB, reduce to 0% duty cycle when
VERR is pulled below 0.6V. OUTAN and OUTBN, the
complements of OUTA and OUTB, respectively, go to 100%
duty cycle when this occurs.
SS - Connect the soft-start timing capacitor between this pin
and GND to control the duration of soft-start. The value of the
capacitor determines the rate of increase of the duty cycle
during start-up. Although no minimum value of capacitance is
required, it is recommended that a value of at least 100pF be
used for noise immunity.
SS may also be used to inhibit the outputs by grounding
through a small transistor in an open collector/drain
configuration.
Voltages below 2.425V result in OUTAN/OUTBN being
advanced relative to OUTA/OUTB. Voltages above 2.575V
result in OUTAN/OUTBN being delayed relative to OUTA/OUTB.
A voltage of 2.50V ±75mV results in zero phase difference. A
weak internal 50% divider from VREF results in no phase delay
if this input is left floating.
Submit Document Feedback
9
FN9183.3
December 3, 2015
ISL6742
Functional Description
Features
The ISL6742 PWM is an excellent choice for low cost bridge
and push-pull topologies in applications requiring accurate
duty cycle and dead time control. With its many protection and
control features, a highly flexible design with minimal external
components is possible. Among its many features are
current- or voltage-mode control, adjustable soft-start, peak
and average overcurrent protection, thermal protection,
synchronous rectifier outputs with variable delay/advance
timing and adjustable oscillator frequency.
zero to the regulation pulse width during the soft-start period.
When the soft-start voltage exceeds the error voltage, soft-start
is completed. Soft-start occurs during start-up and after recovery
from a fault condition. The soft-start charging period may be
calculated using Equation 6:
t = 64.3  C
ms
(EQ. 6)
Where t is the charging period in ms and C is the value of the
soft-start capacitor in µF. The soft-start duration experienced
by the power supply will be less than or equal to this value,
depending on when the feedback loop takes control.
The ISL6742 oscillator, with a programmable frequency range
to 2MHz, is set with only an external resistor and capacitor.
The soft-start voltage is clamped to 4.50V with an overall
tolerance of 2%. It is suitable for use as a “soft-started”
reference provided the current draw is kept well below the
70µA charging current.
The switching period is the sum of the timing capacitor charge
and discharge durations. The charge duration is determined by
CT and a fixed 200µA internal current source. The discharge
duration is determined by RTD and CT.
The outputs may be inhibited by using the SS pin as a disable
input. Pulling SS below 0.27V forces all outputs low. An open
collector/drain configuration may be used to couple the
disable signal to the SS pin.
Oscillator
3
t C  11.5  10  CT
S
(EQ. 1)
t D   0.06  RTD  CT  + 50  10
1
t SW = t C + t D = ---------f SW
–9
S
S
(EQ. 2)
(EQ. 3)
Where tC and tD are the charge and discharge times,
respectively, tSW is the oscillator period, and fSW is the
oscillator frequency. Since the ISL6742 is a double-ended
controller, one output switching cycle requires two oscillator
cycles. The actual charge and discharge times will be slightly
longer than calculated due to internal propagation delays of
approximately 10ns/transition. This delay adds directly to the
switching duration, but also causes slight overshoot of the
timing capacitor peak and valley voltage thresholds, effectively
increasing the peak-to-peak voltage on the timing capacitor.
Additionally, if very low discharge currents are used, there will
be increased error due to the input impedance at the CT pin.
The maximum duty cycle, D, and percent Dead Time (DT) can
be calculated from:
tC
D = ---------t SW
(EQ. 4)
DT = 1 – D
(EQ. 5)
Gate Drive
The ISL6742 outputs are capable of sourcing and sinking
10mA (at rated VOH, VOL) and are intended to be used in
conjunction with integrated FET drivers or discrete bipolar
totem pole drivers. The typical ON-resistance of the outputs is
50Ω.
Overcurrent Operation
Two overcurrent protection mechanisms are available to the
power supply designer. The first method is cycle-by-cycle peak
overcurrent protection, which provides fast response. The
second method is a slower, averaging method, which produces
constant or “brick-wall” current limit behavior. If voltage-mode
control is used, the average overcurrent protection also
maintains flux balance in the transformer by maintaining duty
cycle symmetry between half-cycles.
The current sense signal applied to the CS pin connects to the
peak current comparator and a sample and hold averaging
circuit. After a 70ns Leading Edge Blanking (LEB) delay, the
current sense signal is actively sampled during the on-time, the
average current for the cycle is determined, and the result is
amplified by 4x and output on the IOUT pin. If an RC filter is
placed on the CS input, its time constant should not exceed
~50ns or significant error may be introduced on IOUT.
Soft-Start Operation
The ISL6742 features a soft-start using an external capacitor in
conjunction with an internal current source. Soft-start reduces
component stresses and surge currents during start-up.
Upon start-up, the soft-start circuitry limits the error voltage
input (VERR) to a value equal to the soft-start voltage. The
output pulse width increases as the soft-start capacitor voltage
increases. This has the effect of increasing the duty cycle from
Submit Document Feedback
10
FN9183.3
December 3, 2015
ISL6742
most PWM controllers, except it cannot source current.
Instead, VERR has a separate internal 1mA pull-up current
source.
CHANNEL 1 (YELLOW): OUTA
CHANNEL 3 (BLUE): CS
CHANNEL 2 (RED): OUTB
CHANNEL 4 (GREEN): IOUT
FIGURE 8. CS INPUT vs IOUT
Figure 8 shows the relationship between the CS signal and
IOUT under steady state conditions. IOUT is 4x the average of
CS. Figure 9 shows the dynamic behavior of the current
averaging circuitry when CS is modulated by an external sine
wave. Notice IOUT is updated by the sample and hold circuitry
at the termination of the active output pulse.
Configure the IEA as an integrating (Type I) amplifier using the
internal 0.6V reference. The voltage applied at FB is integrated
against the 0.6V reference. The resulting signal, VERR, is
applied to the PWM comparator where it is compared to the
sawtooth voltage on RAMP. If FB is less than 0.6V, the IEA will
be open loop (can’t source current), VERR will be at a level
determined by the voltage loop, and the duty cycle is
unaffected. As the output load increases, IOUT will increase,
and the voltage applied to FB will increase until it reaches
0.6V. At this point the IEA will reduce VERR as required to
maintain the output current at the level that corresponds to
the 0.6V reference. When the output current again drops
below the average current limit threshold, the IEA returns to an
open loop condition, and the duty cycle is again controlled by
the voltage loop.
The average current control loop behaves much the same as
the voltage control loop found in typical power supplies except
it regulates current rather than voltage.
The EA available on the ISL6742 may also be used as the
voltage EA for the voltage feedback control loop rather than
the current EA as described previously. An external op amp
may be used as either the current or voltage EA providing the
circuit is not allowed to source current into VERR. The external
EA must only sink current, which may be accomplished by
adding a diode in series with its output.
The 4x gain of the sample and hold buffer allows a range of
150mV to 1000mV peak on the CS signal, depending on the
resistor divider placed on IOUT. The overall bandwidth of the
average current loop is determined by the integrating current
EA compensation and the divider on IOUT.
1
ISL6742
2 VERR
3
C10
CHANNEL 1 (YELLOW): OUTA
CHANNEL 3 (BLUE): CS
CHANNEL 2 (RED): OUTB
CHANNEL 4 (GREEN): IOUT
4
5 FB
0.6V +
6
S&H
7 CS
4x
8 IOUT
150mV TO
1000mV
FIGURE 9. DYNAMIC BEHAVIOR OF CS vs IOUT
The average current signal on IOUT remains accurate provided
that the output inductor current is continuous (CCM operation).
Once the inductor current becomes discontinuous (DCM
operation), IOUT represents 1/2 the peak inductor current rather
than the average current. This occurs because the sample and
hold circuitry is active only during the on-time of the switching
cycle. It is unable to detect when the inductor current reaches
zero during the off-time.
If average overcurrent limit is desired, IOUT may be used with
the available error amplifier of the ISL6742. Typically, IOUT is
divided down and filtered as required to achieve the desired
amplitude. The resulting signal is input to the current error
amplifier (IEA). The IEA is similar to the voltage EA found in
Submit Document Feedback
11
R6
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
R5
R4
FIGURE 10. AVERAGE OVERCURRENT IMPLEMENTATION
The current EA crossover frequency, assuming R6 >> (R4||R5),
is expressed in Equation 7:
1
f CO = ----------------------------------2  R6  C10
Hz
(EQ. 7)
FN9183.3
December 3, 2015
ISL6742
Where fCO is the crossover frequency. A capacitor in parallel
with R4 may be used to provide a double-pole roll-off.
The average current loop bandwidth is normally set to be much
less than the switching frequency, typically less than 5kHz and
often as slow as a few hundred hertz or less. This is especially
useful if the application experiences large surges. The average
current loop can be set to the steady state overcurrent threshold
and have a time response that is longer than the required
transient. The peak current limit can be set higher than the
expected transient so that it does not interfere with the
transient, but still protects for short-term larger faults. In
essence, a 2-stage overcurrent response is possible.
The peak overcurrent behavior is similar to most other PWM
controllers. If the peak current exceeds 1V, the active output
pulse is terminated immediately.
If voltage-mode control is used in a bridge topology, it should
be noted that peak current limit results in inherently unstable
operation. DC blocking capacitors used in voltage-mode bridge
topologies become unbalanced, as does the flux in the
transformer core. The average overcurrent circuitry prevents
this behavior by maintaining symmetric duty cycles for each
half-cycle. If the average current limit circuitry is not used, a
latching overcurrent shutdown method using external
components is recommended.
The CS to output propagation delay is increased by the Leading
Edge Blanking (LEB) interval. The effective delay is the sum of
the two delays and is 130ns maximum.
Voltage Feed-Forward Operation
Voltage feed-forward is a technique used to regulate the
output voltage for changes in input voltage without the
intervention of the control loop. Voltage feed-forward is often
implemented in voltage-mode control loops, but is redundant
and unnecessary in peak current-mode control loops.
Voltage feed-forward operates by modulating the sawtooth
ramp in direct proportion to the input voltage. Figure 11
demonstrates the concept.
VIN
1
16
2
15
14
3
R3
4
C7
13
ISL6742
5
12
6 RAMP
11
7
10
8
GND 9
FIGURE 12. VOLTAGE FEED-FORWARD CONTROL
Referring to Figure 12, the charging time of the ramp capacitor
is expressed in Equation 8:
V RAMP  PEAK 

t = – R 3  C 7  ln  1 – ----------------------------------------
V IN  MIN  

s
(EQ. 8)
For optimum performance, the maximum value of the
capacitor should be limited to 10nF. The DC current through
the resistor should be limited to 3mA. For example, if the
oscillator frequency is 400kHz, the minimum input voltage is
300V and a 4.7nF ramp capacitor is selected. The value of the
resistor can be determined by rearranging Equation 8.
–6
–t
– 2.5  10
R 3 = ------------------------------------------------------------------------- = -----------------------------------------------------------–9
1
V RAMP  PEAK 

4.7  10  ln  1 – ----------
C 7  ln  1 – ----------------------------------------

300
V

IN  MIN   
VIN
= 159
ERROR VOLTAGE
k
(EQ. 9)
Where t is equal to the oscillator period minus the dead time.
If the dead time is short relative to the oscillator period, it can
be ignored for this calculation.
RAMP
CT
When implemented, the voltage feed-forward feature also
provides a volt-second clamp on the transformer. The
maximum duty cycle is determined by the lesser of the
oscillator period or the RAMP charge time. As the input voltage
increases, the RAMP charge time decreases, limiting the duty
cycle proportionately.
OUTA, OUTB
FIGURE 11. VOLTAGE FEED-FORWARD BEHAVIOR
Input voltage feed-forward may be implemented using the
RAMP input. An RC network connected between the input
voltage and ground, as shown in Figure 12, generates a
voltage ramp proportional to the amplitude of the source
Submit Document Feedback
voltage. At the termination of the active output pulse, RAMP is
discharged to ground so that a repetitive sawtooth waveform is
created. The RAMP waveform is compared to the VERR voltage
to determine duty cycle. The selection of the RC components
depends upon the desired input voltage operating range and
the frequency of the oscillator. In typical applications, the RC
components are selected so that the ramp amplitude reaches
1V at minimum input voltage within the duration of one halfcycle.
12
If feed-forward operation is not desired, the RC network may be
connected to VREF or a buffered CT signal rather than the input
voltage. Regardless, a sawtooth waveform must be generated on
RAMP as it is required for proper PWM operation.
FN9183.3
December 3, 2015
ISL6742
Implementing Synchronization
Synchronization to an external clock signal may be
accomplished in the same manner as many PWM controllers
that do not have a separate synchronization input. By injecting
a short pulse across a small resistor in series with the timing
capacitor, the oscillator sawtooth waveform may be
terminated prematurely.
A useful feature of the ISL6742 is the ability to vary the phase
relationship between the PWM outputs (OUTA, OUTB) and their
complements (OUTAN, OUTBN) by ±300ns. This feature allows
the designer to compensate for differences in the signal
propagation delays between the PWM FETs and the SR FETs. A
voltage applied to VADJ controls the phase relationship.
Figures 15 and 16 demonstrate the delay relationships.
The injected pulse width should be narrower than the sawtooth
discharge duration.
1
16
2
15
3
14
4 CT
13
5
CT
ISL6742
6
RS
OUTA
OUTB
11
7
8
12
CT
10
GND 9
OUTAN
(SR1)
OUTBN
(SR2)
FIGURE 13. SYNCHRONIZATION TO AN EXTERNAL CLOCK
FIGURE 15. WAVEFORM TIMING WITH PWM OUTPUTS DELAYED,
0V < VADJ < 2.425V
Synchronous Rectifier Outputs and Control
The ISL6742 provides double-ended PWM outputs, OUTA and
OUTB, and Synchronous Rectifier (SR) outputs, OUTAN and
OUTBN. The SR outputs are the complements of the PWM
outputs. It should be noted that complemented outputs are
used in conjunction with the opposite PWM output, i.e. OUTA
and OUTBN are paired together and OUTB and OUTAN are
paired together.
Referring to Figure 14, the SRs alternate between being both
on during the free-wheeling portion of the cycle (OUTA/OUTB
off), and one or the other being off when OUTA or OUTB is on. If
OUTA is on, its corresponding SR must also be on, indicating
that OUTBN is the correct SR control signal. Likewise, if OUTB
is on, its corresponding SR must also be on, indicating that
OUTAN is the correct SR control signal.
CT
CT
OUTA
OUTB
OUTAN
(SR1)
OUTBN
(SR2)
FIGURE 16. WAVEFORM TIMING WITH SR OUTPUTS DELAYED,
2.575V < VADJ < 5.00V
Setting VADJ to VREF/2 results in no delay on any output. The
no delay voltage has a ±75mV tolerance window. Control
voltages below the VREF/2 zero delay threshold cause the
PWM outputs, OUTA/OUTB, to be delayed. Control voltages
greater than the VREF/2 zero delay threshold cause the SR
outputs, OUTAN/OUTBN, to be delayed. It should be noted that
when the PWM outputs, OUTA/OUTB, are delayed, the CS to
output propagation delay is increased by the amount of the
added delay.
OUTA
OUTB
OUTAN
(SR1)
OUTBN
(SR2)
FIGURE 14. BASIC WAVEFORM TIMING
Submit Document Feedback
13
The delay feature is provided to compensate for mismatched
propagation delays between the PWM and SR outputs as may
be experienced when one set of signals crosses the
FN9183.3
December 3, 2015
ISL6742
primary-secondary isolation boundary. If required, individual
output pulses may be stretched or compressed as required
using external resistors, capacitors and diodes.
Vn can be solved for in terms of input voltage, current
transducer components, and output inductance yielding
Equation 16:
Slope Compensation
t SW  V  R CS N
O
S 1
V e = ----------------------------------------  --------  --- + D – 0.5

N CT  L O
NP  
Peak current-mode control requires slope compensation to
improve noise immunity, particularly at lighter loads, and to
prevent current loop instability, particularly for duty cycles
greater than 50%. Slope compensation may be accomplished
by summing an external ramp with the current feedback signal
or by subtracting the external ramp from the voltage feedback
error signal. Adding the external ramp to the current feedback
signal is the more popular method.
From the small signal current-mode model [1] it can be shown
that the naturally-sampled modulator gain, Fm, without slope
compensation, is expressed in Equation 10:
1
F m = -------------Sn Sn
(EQ. 10)
Where Sn is the slope of the sawtooth signal and tSW is the
duration of the half-cycle. When an external ramp is added, the
modulator gain becomes Equation 11:
1
1
F m = ------------------------------------ = -------------------------m c S n t SW
 S n + S e t SW
(EQ. 11)
Where Se is slope of the external ramp and:
Se
m c = 1 + ------Sn
V
(EQ. 16)
Where RCS is the current sense burden resistor, NCT is the
current transformer turns ratio, LO is the output inductance, VO
is the output voltage, and NS and NP are the secondary and
primary turns, respectively.
The current sense signal, which represents the inductor current
after it has been reflected through the isolation and current
sense transformers, and passed through the current sense
burden resistor, is expressed in Equation 17:
N S  R CS 
D  t SW 
NS

V CS = ------------------------  I O + -------------------  V IN  -------- – V O 
2L O 
NP
N P  N CT 

V
(EQ. 17)
Where VCS is the voltage across the current sense resistor and
IO is the output current at current limit.
Since the peak current limit threshold is 1V, the total current
feedback signal plus the external ramp voltage must sum to
this value when the output load is at the current limit
threshold.
V e + V CS = 1
(EQ. 18)
(EQ. 12)
The criteria for determining the correct amount of external
ramp can be determined by appropriately setting the damping
factor of the double-pole located at half the oscillator
frequency. The double-pole will be critically damped if the Q
factor is set to 1, over-damped for Q > 1, and under-damped
for Q < 1. An under-damped condition may result in current
loop instability.
1
Q = ------------------------------------------------  m c  1 – D  – 0.5 
(EQ. 13)
Where D is the percent of on-time during a half cycle (half
period duty cycle). Setting Q = 1 and solving for Se yields
Equation 14:
1
1
S e = S n   --- + 0.5 ------------- – 1
1–D
 

(EQ. 14)
Since Sn and Se are the on-time slopes of the current ramp
and the external ramp, respectively, they can be multiplied by
tON to obtain the voltage change that occurs during tON.
1
1
V e = V n   --- + 0.5 ------------- – 1
1–D
 

(EQ. 15)
Substituting Equations 16 and 17 into Equation 18 and solving
for RCS yields Equation 19:
N P  N CT
1
R CS = ------------------------  ---------------------------------------------------VO
NS
1 D
I O + -------- t SW  --- + ----
 2
L

(EQ. 19)
O
For simplicity, idealized components have been used for this
discussion, but the effect of magnetizing inductance must be
considered when determining the amount of external ramp to
add. Magnetizing inductance provides a degree of slope
compensation and reduces the amount of external ramp
required. The magnetizing inductance adds primary current in
excess of what is reflected from the inductor current in the
secondary.
V IN  Dt SW
I P = ----------------------------Lm
A
(EQ. 20)
Where VIN is the input voltage that corresponds to the duty
cycle D and Lm is the primary magnetizing inductance. The
effect of the magnetizing current at the current sense resistor,
RCS, is expressed in Equation 21:
I P  R CS
V CS = -------------------------N CT
V
(EQ. 21)
Where Vn is the change in the current feedback signal during
the on time and Ve is the voltage that must be added by the
external ramp.
Submit Document Feedback
14
FN9183.3
December 3, 2015
ISL6742
If VCS is greater than or equal to Ve, then no additional slope
compensation is needed and RCS becomes Equation 22:
Example:
VIN = 280V
N CT
R CS = ---------------------------------------------------------------------------------------------------------------------------------NS 
Dt SW 
NS
  V IN  Dt SW
--------   I O + --------------   V  ------- – V O  + ----------------------------Lm
NP 
2L O  IN N P

VO = 12V
LO = 2.0µH
(EQ. 22)
NP/NS = 20
Lm = 2mH
If VCS is less than Ve, then Equation 19 is still valid for the
value of RCS, but the amount of slope compensation added by
the external ramp must be reduced by VCS.
Adding slope compensation is accomplished in the ISL6742
using an external buffer and the CT signal. A typical application
sums the buffered CT signal with the current sense feedback
and applies the result to the CS pin as shown in Figure 17.
1
VREF
2
ISL6742
3
4
R9
16
15
14
CT
13
5
12
6
11
7
CS
8
10
9
R6
RCS
Oscillator Frequency, fSW = 400kHz
Duty Cycle, D = 85.7%
NCT = 50
R6 = 499Ω
Solve for the current sense resistor, RCS, using Equation 19.
RCS = 15.1Ω.
Determine the amount of voltage, Ve, that must be added to
the current feedback signal using Equation 16.
Ve = 153mV
Next, determine the effect of the magnetizing current from
Equation 21.
VCS = 91mV
Using Equation 24, solve for the summing resistor, R9, from CT
to CS.
CT
C4
IO = 55A
R9 = 13.2kΩ
Determine the new value of RCS, R’CS, using Equation 25.
R’CS = 15.7Ω
FIGURE 17. ADDING SLOPE COMPENSATION
Assuming the designer has selected values for the RC filter (R6
and C4) placed on the CS pin, the value of R9 required to add
the appropriate external ramp can be found by superposition.
2D  R 6
V e – V CS = --------------------R6 + R9
(EQ. 23)
V
Parallel Operation
Rearranging to solve for R9 yields:
 2D – V e + V CS   R 6
R 9 = -----------------------------------------------------------V e – V CS

(EQ. 24)
The value of RCS determined in Equation 19 must be rescaled
so that the current sense signal presented at the CS pin is that
predicted by Equation 17. The divider created by R6 and R9
makes this necessary.
R6 + R9
R CS = ---------------------  R CS
R9
Submit Document Feedback
(EQ. 25)
15
Additional slope compensation may be considered for design
margin. This discussion determines the minimum external
ramp that is required. The buffer transistor used to create the
external ramp from CT should have a sufficiently high gain
(>200) so as to minimize the required base current. Whatever
base current is required reduces the charging current into CT
and will reduce the oscillator frequency.
Parallel operation of converters using the ISL6742 may be
accomplished using the average current signal, IOUT. IOUT
provides a very accurate representation of the output current
and may be used for active current sharing with many sharing
techniques commonly used including master-slave and
average current sharing methods.
Since IOUT represents the average inductor current (CCM
operation), sharing errors introduced by techniques using peak
inductor current are reduced. In particular, the current sharing
error introduced by mismatched switching frequencies is
eliminated.
FN9183.3
December 3, 2015
ISL6742
Figure 18 illustrates a master-slave current sharing method.
U1
VOLTAGE ERROR
AMPLIFIER INVERTING (-)
INPUT
BIAS
1
16
2 ISL6742 15
3
VDD 14
4
13
5
12
6
11
S&H
7 CS
10
4x
8 IOUT
9
+
U2A
-
R2
(>>R1)
VOUT
C1
R1
R5
(>>R1)
R3
U2B
+
R4
(>>R3)
OUTPUT
VOLTAGE
FEEDBACK
DIVIDER
Q1
R7
R6
Amplifier U2A sets the scaling factor from IOUT to ISHARE and
increases the current sourcing capability of ISHARE. U2B is a
low bandwidth amplifier that sets the frequency response and
gain of the current share circuitry. The current share bandwidth
must be much lower than the voltage feedback loop
bandwidth to ensure overall stability. The gain is set by R1 and
R5, and the bandwidth by R5 and C1.
The disconnect in series with ISHARE may be omitted for
power systems that do not require fault isolation. The
disconnect switch is normally implemented with MOSFET or
JFET devices.
Average Current Mode Control
The average current signal produced on IOUT may also be used
for average current mode control rather than peak current
mode control. There are many advantages to average current
mode control, most notably, improved noise immunity and
greater design flexibility of the current feedback loop
compensation. Figure 19 portrays the concept.
C2
DISCONNECT IF P/S FAILS
OR IS TURNED OFF
IOUT
R3
R2
ISHARE
FIGURE 18. MASTER-SLAVE CURRENT SHARING USING AVERAGE
CURRENT
In parallel and redundant applications, the ISHARE signals
from each power supply are connected together. Each power
supply produces a voltage proportional to its average output
current on IOUT, and through limiting resistor R3, on ISHARE.
The unit with the highest ISHARE signal (and highest output
current) sources current onto the ISHARE Bus, and is identified
as the master unit. The units with lower ISHARE signals do not
source current onto ISHARE, and are identified as slave units.
Each slave unit compares the master’s ISHARE signal with its
own, and if there is sufficient difference, turns Q1 on, which
pulls down on the feedback voltage. Reducing the feedback
voltage causes the output voltage to appear low; the feedback
loop compensates by increasing the output voltage, and the
output current increases. Each slave unit will increase its
output voltage until its output current is nearly equal to that of
the master.
The difference between the master’s output current and that of a
slave unit is set by R1 and R2. Some difference is required to
prevent undesirable switching of master and slave roles. This
difference also prevents operation of the current sharing circuitry
when a power supply is operating stand alone.
VERR
U2
+
CURRENT
ERROR
AMPLIFIER
R4
VOUT
C1
R1
OFFSET
U1
+ REF
Rb
VOLTAGE ERROR
AMPLIFIER
FIGURE 19. AVERAGE CURRENT MODE CONTROL
Instead of being compared to a peak current sense signal as it
would be in a peak current mode control configuration, the
voltage amplifier output is integrated against the average
output current. The voltage loop compensation and the current
loop compensation may be adjusted independently.
The voltage error amplifier programs the average output
current of the supply, and its maximum output level
determines the maximum output current. Either IOUT or the
voltage EA output must be scaled appropriately to achieve the
desired current limit setpoint. The offset voltage shown in
Figure 19 must be provided to compensate for input offset
voltage of the current amplifier to ensure that zero duty cycle
operation is achievable.
Depending on the performance requirements of the control
loop, compensation networks other than shown may be
required.
The maximum output voltage that a slave can induce in its
output is controlled by R6 and the output voltage feedback
divider. Typically, the maximum allowed output voltage increase
is limited to a few percent, but must be greater than the
tolerance of the feedback and reference components and any
distribution drops between units. If remote sensing is used, the
adjustment range must also include the difference in
distribution drops between the power supply outputs and the
remote sensing location. The current limit circuit must limit the
voltage change to less than the output overvoltage threshold or
an overvoltage condition can be induced.
Submit Document Feedback
16
FN9183.3
December 3, 2015
ISL6742
Fault Conditions
Ground Plane Requirements
A fault condition occurs if VREF or VDD fall below their
Undervoltage Lockout (UVLO) thresholds or if the thermal
protection is triggered. When a fault is detected, the soft-start
capacitor is quickly discharged, and the outputs are disabled low.
When the fault condition clears and the soft-start voltage is below
the reset threshold, a soft-start cycle begins.
Careful layout is essential for satisfactory operation of the device.
A good ground plane must be employed. VDD and VREF should
be bypassed directly to GND with good high frequency
capacitance.
An overcurrent condition is not considered a fault and does not
result in a shutdown.
References
[1] Ridley, R., “A New Continuous-Time Model for Current Mode
Control”, IEEE Transactions on Power Electronics, Vol. 6, No.
2, April 1991.
Thermal Protection
Internal die over temperature protection is provided. An
integrated temperature sensor protects the device should the
junction temperature exceed +140°C. There is approximately
+15°C of hysteresis.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
CHANGE
December 3, 2015
FN9183.3
Applied Intersil standards to entire datasheet.
Added Note 3.
On page 5, corrected typo in test conditions for the Overall Accuracy parameter by changing from “10mA”
to “-10mA”.
Under “Soft-Start Operation” on page 10, last paragraph corrected typo by changing from “0.25V” to
“0.27V”.
Added Revision History and About Intersil sections.
Updated POD M16.15A to the latest revision changes are as follows:
- Convert to new POD format. Added land pattern
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
Submit Document Feedback
17
FN9183.3
December 3, 2015
ISL6742
Package Outline Drawing
M16.15A
16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE (QSOP/SSOP) 0.150” WIDE BODY
Rev 3, 8/12
16
INDEX
AREA
3.99
3.81
6.20
5.84
4
0.25(0.010) M
B M
-B-
1
TOP VIEW
DETAIL “X”
SEATING PLANE
-A-
1.73
1.55
3
4.98
4.80
GAUGE
PLANE
-C0.25
0.010
0.249
0.102
0.635 BSC
7
0.89
0.41
0.31
0.20
0.41
x 45° 5
0.25
0.10(0.004)
0.17(0.007) M C A M B S
SIDE VIEW 1
8°
0°
1.55
1.40
7.11
0.249
0.191
SIDE VIEW 2
5.59
4.06
0.38
0.635
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number
95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Package length does not include mold flash, protrusions or gate burrs. Mold flash,
protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Package width does not include interlead flash or protrusions. Interlead flash and
protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index feature must be
located within the crosshatched area.
6. Terminal numbers are shown for reference only.
7. Lead width does not include dambar protrusion. Allowable dambar protrusion shall be
0.10mm (0.004 inch) total in excess of “B” dimension at maximum material condition.
8. Controlling dimension: MILLIMETER.
TYPICAL RECOMMENDED LAND PATTERN
Submit Document Feedback
18
FN9183.3
December 3, 2015
Similar pages