DATASHEET

ISL6307B
®
Data Sheet
March 9, 2006
6-Phase VR11 PWM Controller with 8-Bit
VID Code Capable of Precision RDS(ON) or
DCR Differential Current Sensing for
Applications in Which Supply Voltage is
Higher than 5V
The ISL6307B controls microprocessor core voltage
regulation by driving up to 6 synchronous-rectified buck
channels in parallel. Multiphase buck converter architecture
uses interleaved timing to multiply channel ripple frequency
and reduce input and output ripple currents. Lower ripple
results in fewer components, lower component cost, reduced
power dissipation, and smaller implementation area.
Microprocessor loads can generate load transients with
extremely fast edge rates. The ISL6307B features a high
bandwidth control loop and ripple frequencies up to 6MHz to
provide optimal response to the transients.
Today’s microprocessors require a tightly regulated output
voltage position versus load current (droop). The ISL6307B
senses current by utilizing patented techniques to measure
the voltage across the on resistance, RDS(ON), of the lower
MOSFETs or DCR, of the output inductor during the lower
MOSFET conduction intervals. Current sensing provides the
needed signals for precision droop, channel-current
balancing, and overcurrent protection. A programmable
internal temperature compensation function is implemented
to effectively compensate for the temperature coefficient of
the current sense element.
A unity gain, differential amplifier is provided for remote
voltage sensing. Any potential difference between remote
and local grounds can be completely eliminated using the
remote-sense amplifier. Eliminating ground differences
improves regulation and protection accuracy. The thresholdsensitive enable input is available to accurately coordinate
the start up of the ISL6307B with any other voltage rail.
Dynamic-VID™ technology allows seamless on-the-fly VID
changes. The offset pin allows accurate voltage offset
settings that are independent of VID setting.
FN9225.0
Features
• Precision multiphase Core Voltage Regulation
- Differential Remote Voltage Sensing
- ±0.5% System Accuracy Over Life, Load, Line and
Temperature
- Adjustable Precision Reference-Voltage Offset
• Precision RDS(ON) or DCR Current Sensing
- Accurate Load-Line Programming
- Accurate Channel-Current Balancing
- Differential Current Sense
• Microprocessor Voltage Identification Input
- Dynamic VID™ Technology
- 8-Bit VID Input with Selectable VR11 Code and
Extended VR10 Code at 6.25mV Step
- 0.5V to 1.600V operation range
• Threshold-sensitive Enable Function for Power
Sequencing and VTT Enable
• Thermal Monitoring
• Internal 5V Shunt Regulator
• Programmable Temperature Compensation
• Overcurrent Protection
• Overvoltage Protection with OVP Output Indication
• 2, 3, 4, 5 or 6 Phase Operation
• Adjustable Switching Frequency up to 1MHz Per Phase
• QFN Package Option
- QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad
Flat No Leads - Product Outline
- QFN Near Chip Scale Package Footprint; Improves
PCB Efficiency, Thinner in Profile
• Pb-Free Plus Anneal Available (RoHS Compliant)
Ordering Information
PART NUMBER
TEMP.
(°C)
PACKAGE
PKG.
DWG. #
ISL6307BCRZ (Note)
0 to 70 48 Ld 7x7 QFN (Pb-free) L48.7x7
ISL6307BIRZ (Note)
-40 to 85 48 Ld 7x7 QFN (Pb-free) L48.7x7
Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Dynamic VID™ is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL6307B
Pinout
TM
VR_HOT
VR_FAN
VR_RDY
OVP
SS
FS
EN_VTT
EN_PWR
ISEN6-
ISEN6+
PWM6
ISL6307B (48 LD QFN)
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
VID7
1
36
PWM3
VID6
2
35
ISEN3+
VID5
3
34
ISEN3-
VID4
4
33
ISEN1-
VID3
5
32
ISEN1+
VID2
6
31
PWM1
30
PWM4
GND
ISEN2-
IOUT 11
26
ISEN2+
DAC 12
25
PWM2
2
13
14
15
16
17
18
19
20
21
22
23
24
PWM5
27
ISEN5+
OFS 10
ISEN5-
ISEN4-
VCC
28
TCOMP
9
VSEN
VRSEL
RGND
ISEN4+
VDIFF
29
IDROOP
8
FB
VID0
COMP
7
REF
VID1
FN9225.0
March 9, 2006
ISL6307B
ISL6307B Block Diagram
VDIFF
VR_RDY
VCC
OVP
0.875V
RGND
SHUNT
REGULATOR
x1
VSEN
S
OVP
DRIVE
R
POWER-ON
RESET (POR)
EEN_VTT
0.875V
Q
EN_PWR
OVP
THREE-STATE
SOFT-START
AND
FAULT LOGIC
+200mV
CLOCK AND
SAWTOOTH
GENERATOR
∑
SS
∑
DAC
PWM2
PWM
OFFSET
REF
PWM1
PWM
∑
OFS
FS
PWM3
PWM
VRSEL
∑
VID7
PWM4
PWM
VID6
∑
VID5
DYNAMIC
VID
D/A
VID4
VID3
VID2
PWM
PWM5
PWM
PWM6
∑
E/A
VID1
VID0
CHANNEL
CURRENT
BALANCE
COMP
FB
CHANNEL
DETECT
ISEN1+
ISEN1-
I_TRIP
2V
OC2
OC1
1
N
ISEN2+
∑
ISEN2-
TEMPERATURE
COMPENSATION
IOUT
ISEN3+
CHANNEL
CURRENT
SENSE
I_TOT
ISEN3ISEN4+
ISEN4ISEN5+
IDROOP
THERMAL
MONITORING
TEMPERATURE
COMPENSATION
GAIN
ISEN5ISEN6+
ISEN6-
GND
3
TM
VR_FAN
VR_HOT
TCOMP
FN9225.0
March 9, 2006
ISL6307B
Typical Application - 6-Phase Buck Converter with RDS(ON) Sensing and External TCOMP
+12V
VCC
BOOT
VIN
UGATE
NTC2
EXTERNAL TCOMP
COMPENSATION
NETWORK
PVCC
ISL6612
DRIVER
PWM
LGATE
GND
+12V
VCC
+12V
PHASE
BOOT
VIN
UGATE
300Ω
FB
COMP REF
IDROOP
DAC
VDIFF
VSEN
GND
EN_VTT
VR_RDY
DRIVER
PWM
LGATE
GND
+12V
VCC
BOOT
ISL6307B
PWM6
VID6
ISEN6ISEN6+
VID5
VID4
VID3
VID2
PWM4
ISEN4ISEN4+
VID1
VID0
VRSEL
OVP
PWM2
ISEN2ISEN2+
PVCC
ISL6612
LGATE
GND
+12V
VCC
BOOT
VIN
µP
LOAD
UGATE
ISEN1ISEN1+
R IOUT
PWM3
ISEN3-
PVCC
PWM
VR_FAN
PWM5
ISEN5ISEN5+
VR_HOT
ISL6612
+12V
LGATE
VCC
BOOT
TM
EN_PWR
TCOMP OFS FS SS
VIN
UGATE
PVCC
R SS
RT
PHASE
DRIVER
GND
ISEN3+
ROFS
PHASE
DRIVER
PWM
PWM1
IOUT
VIN
UGATE
VID7
+5V
PHASE
VCC
RGND
VTT
ISL6612
PVCC
PWM
+12V
ISL6612
PHASE
DRIVER
LGATE
GND
NTC
+12V
VCC
BOOT
VIN
UGATE
PVCC
PWM
GND
4
ISL6612
PHASE
DRIVER
LGATE
FN9225.0
March 9, 2006
ISL6307B
Typical Application - 6-Phase Buck Converter with RDS(ON) Sensing and Integrated TCOMP
+12V
VCC
BOOT
VIN
UGATE
ISL6612
PVCC
PWM
LGATE
GND
+12V
PHASE
DRIVER
VCC
BOOT
+12V
VIN
UGATE
300Ω
FB
COMP REF
IDROOP
DAC
VDIFF
VSEN
VTT
GND
EN_VTT
PWM
LGATE
GND
+12V
VCC
BOOT
VID6
VID5
VID4
VID3
VID2
PWM4
ISEN4ISEN4+
VID1
VID0
VRSEL
OVP
PWM2
ISEN2ISEN2+
ISL6612
PVCC
PWM
LGATE
GND
+12V
VCC
BOOT
VIN
µP
LOAD
UGATE
ISEN1-
R IOUT
ISEN1+
PVCC
PWM3
ISEN3-
PWM
VR_FAN
PWM5
ISEN5ISEN5+
VR_HOT
ISL6612
+12V
LGATE
VCC
BOOT
EN_PWR
TCOMP OFS FS
VIN
UGATE
SS
+5V
PVCC
R SS
RT
PHASE
DRIVER
GND
ISEN3+
ROFS
PHASE
DRIVER
PWM1
IOUT
VIN
UGATE
PWM6
ISEN6ISEN6+
TM
PHASE
DRIVER
ISL6307B
VID7
+5V
ISL6612
VCC
RGND
VR_RDY
PVCC
PWM
+12V
ISL6612
PHASE
DRIVER
LGATE
GND
NTC
+12V
VCC
BOOT
VIN
UGATE
PVCC
PWM
GND
5
ISL6612
PHASE
DRIVER
LGATE
FN9225.0
March 9, 2006
ISL6307B
Typical Application - 6-Phase Buck Converter with DCR Sensing and External TCOMP
+12V
VCC
BOOT
VIN
UGATE
NTC2
EXTERNAL TCOMP
COMPENSATION
NETWORK
ISL6612
PVCC
DRIVER
PWM
LGATE
GND
+12V
VCC
+12V
PHASE
BOOT
VIN
UGATE
300Ω
FB
COMP REF
IDROOP
DAC
VDIFF
VSEN
VTT
GND
EN_VTT
LGATE
GND
+12V
VCC
BOOT
VID6
VID5
VID4
VID3
VID2
PWM4
ISEN4ISEN4+
VID1
VID0
VRSEL
OVP
PWM2
ISEN2ISEN2+
ISL6612
PVCC
LGATE
GND
+12V
VCC
BOOT
VIN
µP
LOAD
UGATE
ISEN1ISEN1+
R IOUT
PWM3
ISEN3-
PVCC
PWM
VR_FAN
PWM5
ISEN5ISEN5+
VR_HOT
ISL6612
+12V
LGATE
VCC
BOOT
EN_PWR
TCOMP OFS FS
VIN
UGATE
SS
PVCC
RT
PHASE
DRIVER
GND
ISEN3+
ROFS
PHASE
DRIVER
PWM
PWM1
IOUT
VIN
UGATE
PWM6
ISEN6ISEN6+
TM
PHASE
DRIVER
PWM
ISL6307B
VID7
+5V
ISL6612
VCC
RGND
VR_RDY
PVCC
R SS
PWM
+12V
GND
ISL6612
PHASE
DRIVER
LGATE
NTC
+12V
VCC
BOOT
VIN
UGATE
PVCC
PWM
GND
6
ISL6612
PHASE
DRIVER
LGATE
FN9225.0
March 9, 2006
ISL6307B
Typical Application - 6-Phase Buck Converter with DCR Sensing and Integrated TCOMP
+12V
VCC
BOOT
VIN
UGATE
PVCC
ISL6612
PWM
LGATE
GND
+12V
VCC
+12V
PHASE
DRIVER
BOOT
VIN
UGATE
300Ω
FB
IDROOP
COMP REF
VSEN
VTT
LGATE
GND
VCC
RGND
GND
EN_VTT
VR_RDY
+5V
VCC
BOOT
ISL6307B
VID7
PHASE
DRIVER
PWM
DAC
VDIFF
ISL6612
PVCC
UGATE
PWM6
ISEN6ISEN6+
VID6
VID5
VID4
VID3
VID2
PWM4
ISEN4ISEN4+
VID1
VID0
VRSEL
OVP
PWM2
ISEN2ISEN2+
EN
ISL6612
PWM
LGATE
GND
+12V
PHASE
DRIVER
VCC
BOOT
PWM1
IOUT
VIN
VIN
µP
LOAD
UGATE
ISEN1R IOUT
ISEN1+
EN
PWM3
ISEN3-
PWM
PWM5
ISEN5ISEN5+
VR_HOT
TM
+5V
VCC
BOOT
RT
VIN
UGATE
SS
PVCC
ROFS
LGATE
EN_PWR
TCOMPOFS FS
+5V
+12V
PHASE
DRIVER
GND
ISEN3+
VR_FAN
ISL6612
R SS
PWM
+12V
GND
ISL6612
PHASE
DRIVER
LGATE
NTC
+12V
VCC
BOOT
VIN
UGATE
PVCC
PWM
GND
7
ISL6612
PHASE
DRIVER
LGATE
FN9225.0
March 9, 2006
ISL6307B
Absolute Maximum Ratings
Thermal Information
Voltage at VCC when it is connected to enxternal >5V input through
a resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+6V
IAll Pins . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to VCC + 0.3V
ESD (Human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>2kV
ESD (Machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>200V
ESD (Charged device model . . . . . . . . . . . . . . . . . . . . . . . . . >1.5kV
Thermal Resistance (Notes 1, 2)
θJA (°C/W)
θJC (°C/W)
QFN Package. . . . . . . . . . . . . . . . . . . .
32
6.5
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
Operating Conditions
Voltage at VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Ambient Temperature (ISL6307BCRZ) . . . . . . . . . . . . . 0°C to 70°C
Ambient Temperature (ISL6307BIRZ) . . . . . . . . . . . . .-40°C to 85°C
CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational section of this specification is not implied.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Operating Conditions: VCC = 5V or ICC < 25mA (Note 3). Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
SHUNT REGULATOR
VCC Voltage
VCC tied to 12VDC thru 300Ω resistor, RT = 100kΩ
-
5
-
V
VCC Sink Current
VCC tied to 12VDC thru 300Ω resistor, RT = 100kΩ
-
-
25
mA
VCC Rising
4.3
4.5
4.70
V
VCC Falling
3.7
3.9
4.20
V
0.850
0.875
0.910
V
POWER-ON RESET AND ENABLE
POR Threshold
EN_PWR Threshold
Rising
Hysteresis
EN_VTT Threshold
-
130
-
mV
Falling
0.720
0.745
0.775
V
Rising
0.850
0.875
0.910
V
-
130
-
mV
0.720
0.745
0.775
V
Hysteresis
Falling
REFERENCE VOLTAGE AND DAC
System Accuracy of ISL6307BCRZ
(VID = 1V-1.6V), TJ = 0°Cto 70°C)
(Note 3)
-0.5
-
0.5
%VID
System Accuracy of ISL6307BCRZ
(VID = 0.5V-1V),TJ = 0°C to 70°C)
(Note 3)
-0.9
-
0.9
%VID
System Accuracy of ISL6307BIRZ
(VID = 1V-1.6V), TJ = -40°C to 85°C)
(Note 3)
-0.6
-
0.6
%VID
System Accuracy of ISL6307BIRZ
(VID = 0.5V-1V),TJ = -40°C to 85°C)
(Note 3)
-1
-
1
%VID
-60
-40
-20
µA
VID Input Low Level
-
-
0.4
V
VID Input High Level
VID Pull Up
0.8
-
-
V
VRSEL Input Low Level
-
-
0.4
V
VRSEL Input High Level
0.8
-
-
V
DAC Source Current
-
-
7
mA
DAC Sink Current
-
-
300
µA
REF Source Current
45
50
55
µA
REF Sink Current
45
50
55
µA
8
FN9225.0
March 9, 2006
ISL6307B
Electrical Specifications
Operating Conditions: VCC = 5V or ICC < 25mA (Note 3). Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
392
400
408
mV
1.568
1.600
1.632
V
388
400
412
mV
1.552
1.600
1.648
V
225
250
275
kHz
0.08
-
1.0
MHz
-
1.563
-
mV/µs
0.625
-
6.25
mV/µs
Sawtooth Amplitude
-
1.5
-
V
Max Duty Cycle
-
66.7
-
%
-
96
-
dB
PIN-ADJUSTABLE OFFSET
Voltage at OFS Pin for ISL6307BCRZ
Offset resistor connected to ground
Voltage at OFS Pin for ISL6307BIRZ
Offset resistor connected to ground
Voltage below VCC, offset resistor connected to VCC
Voltage below VCC, offset resistor connected to VCC
OSCILLATORS
Accuracy of Switching Frequency Setting
RT = 100kΩ
Adjustment Range of Switching Frequency (Note 4)
Soft-start Ramp Rate (Notes 5, 6)
RSS = 100kΩ
Adjustment Range of Soft-start Ramp Rate (Note 4)
PWM GENERATOR
ERROR AMPLIFIER
Open-Loop Gain
RL = 10kΩ to ground (Note 4)
Open-Loop Bandwidth
CL = 100pF, RL = 10kΩ to ground (Note 4)
-
20
-
MHz
Slew Rate
CL = 100pF
-
9
-
V/µs
Maximum Output Voltage
3.8
4.3
4.9
V
Output High Voltage @ 2mA
3.6
-
-
V
Output Low Voltage @ 2mA
-
-
1.2
V
-
20
-
MHz
REMOTE-SENSE AMPLIFIER
Bandwidth
(Note 4)
Output High Current
VSEN - RGND = 2.5V
-500
-
500
µA
Output High Current
VSEN - RGND = 0.6
-500
-
500
µA
PWM OUTPUT
PWM Output Voltage LOW Threshold
Iload = ±500µA
-
-
0.5
V
PWM Output Voltage HIGH Threshold
Iload = ±500µA
4.3
-
-
V
76
80
84
µA
90
100
110
µA
-
2
-
V
TM Input Voltage for VR_FAN Trip
1.6
1.65
1.69
V
TM Input Voltage for VR_FAN Reset
1.89
1.93
1.98
V
TM Input Voltage for VR_HOT Trip
1.35
1.4
1.44
V
TM Input Voltage for VR_HOT Reset
1.6
1.65
1.69
V
SENSE CURRENT OUTPUT (IDROOP and IOUT)
Sensed Current Tolerance
ISEN1 = ISEN2 = ISEN3 = ISEN4 = ISEN5 = ISEN6 = 80µA
Overcurrent Trip Level
Maximum Voltage at IDROOP and
IOUT Pins
THERMAL MONITORING AND FAN CONTROL
Leakage Current of VR_HOT
With external pull-up resistor connected to 5V
-
-
30
µA
VR_HOT Low Voltage
With 1.250kΩ resistor pull up to 5V, IVR_HOT = 4mA
-
-
0.3
V
Leakage Current of VR_FAN
With external pull-up resistor connected to 5V
-
-
30
µA
VR_FAN Low Voltage
With 1.250kΩ resistor pull up to 5V, IVR_FAN = 4mA
-
-
0.3
V
VR READY AND PROTECTION MONITORS
Leakage current of VR_RDY
With external pull-up resistor connected to 5V
-
-
30
µA
VR_RDY Low Voltage
IVR_RDY = 4mA
-
-
0.3
V
Under Voltage Trip of VR-RDY
VSEN Falling
48
50
52
%VID
9
FN9225.0
March 9, 2006
ISL6307B
Electrical Specifications
Operating Conditions: VCC = 5V or ICC < 25mA (Note 3). Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
VR-RDY Reset Voltage
VDIFF Rising
Overvoltage Protection Threshold
Before valid VID
After valid VID, the voltage above VID
Overvoltage Reset Threshold
MIN
TYP
MAX
UNITS
58
60
62
%VID
1.250
1.275
1.300
V
150
175
200
mV
0.38
0.40
0.42
V
OVP Output High Voltage
IOVP = 4mA
4.5
-
-
V
OVP Output Low Voltage
IOVP = 4mA
-
-
0.25
V
NOTES:
3. These parts are designed and adjusted for accuracy with all errors in the voltage loop included.
4. Spec guaranteed by design.
5. During soft-start, VDAC rises from 0 to 1.1V first and then ramp to VID voltage after receiving valid VID input.
6. Soft-start ramp rate is determined by the adjustable soft-start oscillator frequency at the speed of 6.25mV per cycle.
Functional Pin Description
VCC - Supplies all the power necessary to operate the chip.
The controller starts to operate when the voltage on this pin
exceeds the rising POR threshold and shuts down when the
voltage on this pin drops below the falling POR threshold.
Connect this pin through a series 390Ω resistor to a +12V
supply and a 1µF capacitor from this pin to GND.
GND - Bias and reference ground for the IC. The bottom
metal base of ISL6307B is the GND.
EN_PWR - This pin is a threshold-sensitive enable input for
the controller. Connecting the 12V supply to EN_PWR
through an appropriate resistor divider provides a means to
synchronize power-up of the controller and the MOSFET
driver ICs. When EN_PWR is driven above 0.875V, the
ISL6307B is active depending on status of EN_VTT, the
internal POR, and pending fault states. Driving EN_PWR
below 0.745V will clear all fault states and prime the
ISL6307B to soft-start when re-enabled.
EN_VTT - This pin is another threshold-sensitive enable
input for the controller. It’s typically connected to VTT output
of VTT voltage regulator in the computer mother board.
When EN_VTT is driven above 0.875V, the ISL6307B is
active depending on status of ENLL, the internal POR, and
pending fault states. Driving EN_VTT below 0.745V will clear
all fault states and prime the ISL6307B to soft-start when reenabled.
FS - Use this pin to set up the desired switching frequency. A
resistor, placed from FS to ground will set the switching
frequency. The relationship between the value of the resistor
and the switching frequency will be described by an
approximate Equation 40.
SS - Use this pin to set up the desired start-up oscillator
frequency. A resistor, placed from SS to ground will set up
the soft-start ramp rate.The relationship between the value
of the resistor and the soft-start ramp up time will be
described by approximate equation.
10
VID7, VID6, VID5, VID4, VID3, VID2, VID1 and VID0 These are the inputs to the internal DAC that provides the
reference voltage for output regulation. Connect these pins
either to open-drain outputs with or without external pull-up
resistors or to active-pull-up outputs. VID7-VID0 have 40µA
internal pull-up current sources that diminish to zero as the
voltage rises above the logic-high level. These inputs can be
pulled up as high as VCC plus 0.3V.
When a VID code causes a shut-off, the controller needs to
be reset before it will start again.
VRSEL - VRSEL is the pin used to select Internal VID code.
when it is connected to GND, the extended VR10 code is
selected. When it’s floated or pulled to high, VR11 code is
selected. This input can be pulled up as high as VCC plus 0.3V.
VDIFF, VSEN, and RGND - VSEN and RGND form the
precision differential remote-sense amplifier. This amplifier
converts the differential voltage of the remote output to a
single-ended voltage referenced to local ground. VDIFF is
the amplifier’s output and the input to the regulation and
protection circuitry. Connect VSEN and RGND to the sense
pins of the remote load.
FB and COMP - Inverting input and output of the error
amplifier respectively. FB is connected to VDIFF through a
resistor. A negative current, proportional to output current is
present on the FB pin. A properly sized resistor between
VDIFF and FB sets the load line (droop). The droop scale
factor is set by the ratio of the ISEN resistors and the lower
MOSFET RDS(ON). COMP is tied back to FB through an
external R-C network to compensate the regulator.
DAC and REF - The DAC output pin is the output of the
precision internal DAC reference. The REF input pin is the
positive input of the Error Amp. In typical applications, a 1kΩ,
1% resistor is used between DAC and REF to generate a
precise offset voltage. This voltage is proportional to the
offset current determined by the offset resistor from OFS to
ground or VCC. A capacitor is used between REF and
ground to smooth the voltage transition during Dynamic
VID™ operations.
FN9225.0
March 9, 2006
ISL6307B
PWM1, PWM2, PWM3, PWM4, PWM5, PWM6 - Pulsewidth modulation outputs. Connect these pins to the PWM
input pins of the Intersil driver IC. The number of active
channels is determined by the state of PWM3, PWM4,
PWM5 and PWM 6. Tie PWM3 to VCC to configure for
2-phase operation. Tie PWM4 to VCC to configure for
3-phase operation. Tie PWM5 to VCC to configure for
4-phase operation. Tie PWM6 to VCC to configure for
5-phase operation.
ISEN1+, ISEN1-; ISEN2+, ISEN2-; ISEN3+, ISEN3-;
ISEN4+, ISEN4-; ISEN5+, ISEN5-; ISEN6+, ISEN6- - The
ISEN+ and ISEN- pins are current sense inputs to individual
differential amplifiers. The sensed current is used as a
reference for channel balancing, protection, and regulation.
Inactive channels should have their respective current sense
inputs left open (for example, for 3-phase operation open
ISEN4+).
For DCR sensing, connect each ISEN- pin to the node
between the RC sense elements. Tie the ISEN+ pin to the
other end of the sense capacitor through a resistor, RISEN.
The voltage across the sense capacitor is proportional to the
inductor current. The sense current is proportional to the
output current, and scaled by the DCR of the inductor and
RISEN.
When configured for RDS(ON) current sensing, the ISEN1-,
ISEN2-, ISEN3-, ISEN4-, ISEN5-, ISEN6- pins are grounded
at the lower MOSFET sources. The ISEN1+, ISEN2+,
ISEN3+, ISEN4+, ISEN5+, ISEN6+ pins are then held at a
virtual ground, such that a resistor connected between them,
and the drain terminal of the associated lower MOSFET, will
carry a current proportional to the current flowing through
that channel. The current is determined by the negative
voltage developed across the lower MOSFET’s RDS(ON),
which is the channel current scaled by RDS(ON) and RISEN.
VR_RDY - VR_RDY is used as an indication of the end of
soft-start with certain delay per Intel VR11. It is an opendrain logic output that is low impedance until the soft-start is
completed. It will be pulled low again once the undervoltage
point is reached.
OFS - The OFS pin provides a means to program a DC
offset current for generating a DC offset voltage at the REF
input. The offset current is generated via an external resistor
and precision internal voltage references. The polarity of the
offset is selected by connecting the resistor to GND or VCC.
For no offset, the OFS pin should be left unterminated.
TCOMP - Temperature compensation scaling input. The
voltage sensed on the TM pin is utilized as the temperature
input to adjust ldroop and the overcurrent protection limit to
effectively compensate for the temperature coefficient of the
current sense element. To implement the integrated
temperature compensation, a resistor divider circuit is
needed with one resistor being connected from TCOMP to
VCC of the controller and another resistor being connected
11
from TCOMP to GND. Changing the ratio of the resistor
values will set the gain of the integrated thermal
compensation. When integrated temperature compensation
function is not used, connect TCOMP to GND.
OVP - The Overvoltage protection output indication pin. This
pin can be pulled to VCC and is latched when an overvoltage
condition is detected. When not used, keep this pin open.
IDROOP - The output pin of sensed average channel
current which is probational to load current. In the
application which does not require loadline, leave this pin
open. In the application which requires load line, connect
this pin to FB so that the sensed average current will flow
through the resistor between FB and VDIFF to create a
voltage drop which is probational to load current.
IOUT - IOUT has the same output as IDROOP with
additional OCP adjustment function. In actual application, a
resistor needs to be placed between IOUT and GND to
ensure the proper operation. The Voltage at IOUT pin will be
proportional to the load current. If the voltage is higher than
2V, ISL6307B will go into OCP mode, this means shut down
first and then hiccup. The additional OCP trip level can be
adjusted by changing the resistor value.
TM - TM is an input pin for VR temperature measurement.
Connect this pin through NTC thermistor to GND and a
resistor to 5V. The voltage at this pin is proportional to VR
temperature. ISL6307 monitor the VR temperature based
the voltage at TM pin and output VR_HOT and VR_FAN
control singles.
VR_HOT - An indication output pin of high VR temperature.
It is an open-drain logic output with low impedance. It will be
pulled high when measured VR temperature reaches certain
level.
VR_FAN - An indication output pin of VR temperature high
warning with open-drain logic. It will be pulled high when
measured VR temperature reaches certain level. VR_FAN
will be pulled to high before VR_HOT.
Operation
Multiphase Power Conversion
Microprocessor load current profiles have changed to the
point that the advantages of multiphase power conversion
are impossible to ignore. The technical challenges
associated with producing a single-phase converter which is
both cost-effective and thermally viable, have forced a
change to the cost-saving approach of multiphase. The
ISL6307B controller helps reduce the complexity of
implementation by integrating vital functions and requiring
minimal output components. The block diagrams on pages
4, 5, 6 and 7 provide top level views of multiphase power
conversion using the ISL6307B controller.
FN9225.0
March 9, 2006
ISL6307B
INPUT-CAPACITOR CURRENT, 10A/DIV
IL1 + IL2 + IL3, 7A/DIV
CHANNEL 3
INPUT CURRENT
10A/DIV
IL3, 7A/DIV
PWM3, 5V/DIV
IL2, 7A/DIV
CHANNEL 2
INPUT CURRENT
10A/DIV
PWM2, 5V/DIV
CHANNEL 1
INPUT CURRENT
10A/DIV
IL1, 7A/DIV
PWM1, 5V/DIV
1µs/DIV
1µs/DIV
FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS
FOR 3-PHASE CONVERTER
Interleaving
The switching of each channel in a multiphase converter is
timed to be symmetrically out of phase with each of the other
channels. In a 3-phase converter, each channel switches 1/3
cycle after the previous channel and 1/3 cycle before the
following channel. As a result, the three-phase converter has
a combined ripple frequency three times greater than the
ripple frequency of any one phase. In addition, the peak-topeak amplitude of the combined inductor currents is reduced
in proportion to the number of phases (Equations 1 and 2).
Increased ripple frequency and lower ripple amplitude mean
that the designer can use less per-channel inductance and
lower total output capacitance for any performance
specification.
Figure 1 illustrates the multiplicative effect on output ripple
frequency. The three channel currents (IL1, IL2, and IL3)
combine to form the AC ripple current and the DC load
current. The ripple component has three times the ripple
frequency of each individual channel current. Each PWM
pulse is terminated 1/3 of a cycle after the PWM pulse of the
previous phase. The peak-to-peak current for each phase is
about 7A, and the dc components of the inductor currents
combine to feed the load.
To understand the reduction of ripple current amplitude in the
multiphase circuit, examine the equation representing an
individual channel’s peak-to-peak inductor current.
( V IN – V OUT ) V OUT
I P-P = ----------------------------------------------------L fS V
(EQ. 1)
IN
In Equation 1, VIN and VOUT are the input and output
voltages respectively, L is the single-channel inductor value,
and fS is the switching frequency.
12
FIGURE 2. CHANNEL INPUT CURRENTS AND INPUTCAPACITOR RMS CURRENT FOR 3-PHASE
CONVERTER
The output capacitors conduct the ripple component of the
inductor current. In the case of multiphase converters, the
capacitor current is the sum of the ripple currents from each
of the individual channels. Compare Equation 1 to the
expression for the peak-to-peak current after the summation
of N symmetrically phase-shifted inductor currents in
Equation 2. Peak-to-peak ripple current decreases by an
amount proportional to the number of channels. Outputvoltage ripple is a function of capacitance, capacitor
equivalent series resistance (ESR), and inductor ripple
current. Reducing the inductor ripple current allows the
designer to use fewer or less costly output capacitors.
( V IN – N V OUT ) V OUT
I C, P-P = ----------------------------------------------------------L fS V
(EQ. 2)
IN
Another benefit of interleaving is to reduce input ripple
current. Input capacitance is determined in part by the
maximum input ripple current. Multiphase topologies can
improve overall system cost and size by lowering input ripple
current and allowing the designer to reduce the cost of input
capacitance. The example in Figure 2 illustrates input
currents from a three-phase converter combining to reduce
the total input ripple current.
The converter depicted in Figure 2 delivers 36A to a 1.5V load
from a 12V input. The RMS input capacitor current is 5.9A.
Compare this to a single-phase converter also stepping down
12V to 1.5V at 36A. The single-phase converter has 11.9A
RMS input capacitor current. The single-phase converter
must use an input capacitor bank with twice the RMS current
capacity as the equivalent three-phase converter.
Figures 22, 23 and 24 in the section entitled Input Capacitor
Selection can be used to determine the input-capacitor RMS
current based on load current, duty cycle, and the number of
channels. They are provided as aids in determining the
optimal input capacitor solution. Figure 25 shows the single
phase input-capacitor RMS current for comparison.
FN9225.0
March 9, 2006
ISL6307B
PWM Operation
The timing of each converter leg is set by the number of
active channels. The default channel setting for the
ISL6307B is four. One switching cycle is defined as the time
between PWM1 pulse termination signals. The pulse
termination signal is an internally generated clock signal
which triggers the falling edge of PWM1. The cycle time of
the pulse termination signal is the inverse of the switching
frequency set by the resistor between the FS pin and
ground. Each cycle begins when the clock signal commands
the channel-1 PWM output to go low. The PWM1 transition
signals the channel-1 MOSFET driver to turn off the
channel-1 upper MOSFET and turn on the channel-1
synchronous MOSFET. In the default channel configuration,
the PWM2 pulse terminates 1/4 of a cycle after PWM1. The
PWM3 output follows another 1/4 of a cycle after PWM2.
PWM4 terminates another 1/4 of a cycle after PWM3.
If PWM3 is connected to VCC, two channel operation is
selected and the PWM2 pulse terminates 1/2 of a cycle later.
Connecting PWM4 to VCC selects three channel operation
and the pulse-termination times are spaced in 1/3 cycle
increments. Connecting both PWM3 and PWM4 to VCC
selects single-channel operation.
Once a PWM signal transitions low, it is held low for a
minimum of 1/3 cycle. This forced off time is required to
ensure an accurate current sample. Current sensing is
described in the next section. After the forced off time
expires, the PWM output is enabled. The PWM output state
is driven by the position of the error amplifier output signal,
VCOMP, minus the current correction signal relative to the
sawtooth ramp as illustrated in Figure 7. When the modified
VCOMP voltage crosses the sawtooth ramp, the PWM output
transitions high. The MOSFET driver detects the change in
state of the PWM signal and turns off the synchronous
(lower) MOSFET and turns on the upper MOSFET. The
PWM signal will remain high until the pulse termination
signal marks the beginning of the next cycle by triggering the
PWM signal low.
Current Sampling
During the forced off-time following a PWM transition low,
the associated channel current sense amplifier uses the
ISEN inputs to reproduce a signal proportional to the
inductor current, IL. This current gets sampled starting 1/6
period after each PWM goes low and continuously gets
sampled for 1/3 period, or until the PWM goes high,
whichever comes first. No matter the current sense method,
the sense current, ISEN, is simply a scaled version of the
inductor current. Coincident with the falling edge of the PWM
signal, the sample and hold circuitry samples the sensed
current signal ISEN, as illustrated in Figure 3.
Therefore, the sample current, In, is proportional to the
output current and held for one switching cycle. The sample
current is used for current balance, load-line regulation, and
overcurrent protection.
13
IL
PWM
ISEN
0.5Tsw
SAMPLE CURRENT, In
SWITCHING PERIOD
TIME
FIGURE 3. SAMPLE AND HOLD TIMING
Current Sensing
The ISL6307B supports inductor DCR sensing, MOSFET
RDS(ON) sensing, or resistive sensing techniques. The
internal circuitry, shown in Figures 4, 5, and 6, represents
one channel of an N-channel converter. This circuitry is
repeated for each channel in the converter, but may not be
active depending on the status of the PWM3 and PWM4
pins, as described in the PWM Operation section.
INDUCTOR DCR SENSING
An inductor’s winding is characteristic of a distributed
resistance as measured by the DCR (Direct Current
Resistance) parameter. Consider the inductor DCR as a
separate lumped quantity, as shown in Figure 4. The
channel current IL, flowing through the inductor, will also
pass through the DCR. Equation 3 shows the s-domain
equivalent voltage across the inductor VL.
V L = I L ⋅ ( s ⋅ L + DCR )
(EQ. 3)
A simple R-C network across the inductor extracts the DCR
voltage, as shown in Figure 4.
The voltage on the capacitor VC, can be shown to be
proportional to the channel current IL, see Equation 4.
L
 s ⋅ ------------+ 1 ⋅ ( DCR ⋅ I L )
 DCR

-------------------------------------------------------------------VC =
( s ⋅ RC + 1 )
(EQ. 4)
If the R-C network components are selected such that the
RC time constant (= R*C) matches the inductor time
constant (= L/DCR), the voltage across the capacitor VC is
equal to the voltage drop across the DCR, i.e. proportional to
the channel current.
FN9225.0
March 9, 2006
ISL6307B
VIN
I (s)
L
L
ISL6612
L
+
VC(s)
R
PWM(n)
COUT
COUT
ISL6307B INTERNAL CIRCUIT
-
VL
-
+
VOUT
DCR
INDUCTOR
RISEN(n)
In
C
SAMPLE
&
HOLD
ISEN-(n)
+
ISL6307B INTERNAL CIRCUIT
-
RISEN(n)
(PTC)
In
ISEN+(n)
I
SAMPLE
&
HOLD
I
L
RSENSE VOUT
ISEN-(n)
R
SENSE
SEN = I L ------------------------R
ISEN
FIGURE 5. SENSE RESISTOR IN SERIES WITH INDUCTORS
+
MOSFET RDS(ON) SENSING
ISEN+(n)
DCR
I SEN = I ------------------LR
ISEN
FIGURE 4. DCR SENSING CONFIGURATION
With the internal low-offset current amplifier, the capacitor
voltage VC is replicated across the sense resistor RISEN.
Therefore the current out of ISEN+ pin, ISEN, is proportional
to the inductor current.
Equation 5 shows that the ratio of the channel current to the
sensed current ISEN is driven by the value of the sense
resistor and the DCR of the inductor.
DCR
I SEN = I L ⋅ -----------------R ISEN
(EQ. 5)
The controller can also sense the channel load current by
sampling the voltage across the lower MOSFET RDS(ON)
(see Figure 6). The amplifier is ground-reference by
connecting the ISEN- pin to the source of the lower
MOSFET. ISEN+ pin is connected to the PHASE node
through the current sense resistor RISEN. The voltage
across RISEN is equivalent to the voltage drop across the
RDS(ON) of the lower MOSFET while it is conducting. The
resulting current out of the ISEN+ pin is proportional to the
channel current IL.
In
IL
SAMPLE
&
HOLD
ISEN+(n)
RESISTIVE SENSING
For accurate current sense, a dedicated current-sense
resistor RSENSE in series with each output inductor can
serve as the current sense element (see Figure 5). This
technique is more accurate, but reduces overall converter
efficiency due to the additional power loss on the current
sense element RSENSE.
Equation 6 shows the ratio of the channel current to the
sensed current ISEN.
R SENSE
I SEN = I L ⋅ ----------------------R
(EQ. 6)
ISEN
VIN
R DS ( ON )
I SEN = I --------------------------L R
ISEN
RISEN
(PTC)
-
ISEN-(n)
I L xR DS ( ON )
+
+
N-CHANNEL
MOSFETs
ISL6307B INTERNAL CIRCUIT
EXTERNAL CIRCUIT
FIGURE 6. MOSFET RDS(ON) CURRENT-SENSING CIRCUIT
Equation 7 shows the ratio of the channel current to the
sensed current ISEN.
R DS ( ON )
I SEN = I L -----------------------R ISEN
(EQ. 7)
Both inductor DCR and MOSFET RDS(ON) value will
increase as the temperature increases. Therefore the
sensed current will increase as the temperature of the
current sense element increases. In order to compensate
14
FN9225.0
March 9, 2006
ISL6307B
the temperature effect on the sensed current signal, a
Positive Temperature Coefficient (PTC) resistor can be
selected for the sense resistor RISEN, or the integrated
temperature compensation function of ISL6307B should be
utilized. The integrated temperature compensation function
is described in the Temperature Compensation section.
voltage. The internal and external circuitry which control
voltage regulation is illustrated in Figure 8.
EXTERNAL CIRCUIT
R C CC
COMP
DAC
Channel-Current Balance
The sensed current In from each active channel are summed
together and divided by the number of active channels. The
resulting average current IAVG provides a measure of the
total load current. Channel current balance is achieved by
comparing the sampled current of each channel to the
average current to make an appropriate adjustment to the
PWM duty cycle of each channel. Intersil’s patented currentbalance method is illustrated in Figure 7. In the figure, the
average current combines with the channel 1 current I1 to
create an error signal IER. The filtered error signal modifies
the pulse width commanded by VCOMP to correct any
unbalance and force IER toward zero. The same method for
error signal correction is applied to each active channel.
VCOMP
FILTER
+
SAWTOOTH SIGNAL
IAVG
-
+
I6
I5
IER
÷N
Σ
I4
I3
I2
I1
FIGURE 7. CHANNEL-1 PWM FUNCTION AND CURRENTBALANCE ADJUSTMENT
Channel current balance is essential in achieving the
thermal advantage of multiphase operation. With good
current balance, the power loss is equally dissipated over
multiple devices and a greater area.
Voltage Regulation
The integrating compensation network shown in Figure 8
assures that the steady-state error in the output voltage is
limited only to the error in the reference voltage (output of
the DAC) and offset errors in the OFS current source,
remote-sense and error amplifiers. Intersil specifies the
guaranteed tolerance of the ISL6307B to include the
combined tolerances of each of these elements.
The output of the error amplifier, VCOMP, is compared to the
sawtooth waveform to generate the PWM signals. The PWM
signals control the timing of the Intersil MOSFET drivers and
regulate the converter output to the specified reference
15
REF
CREF
+
-
FB
RFB
IDROOP
+
VDROOP
VDIFF
VOUT+
VOUT-
IAVG
VCOMP
ERROR AMPLIFIER
VSEN
+
RGND
DIFFERENTIAL
REMOTE-SENSE
AMPLIFIER
PWM1
-
f(jω)
RREF
FIGURE 8. OUTPUT VOLTAGE AND LOAD-LINE
REGULATION WITH OFFSET ADJUSTMENT
+
-
ISL6307B INTERNAL CIRCUIT
The ISL6307B incorporates an internal differential remotesense amplifier in the feedback path. The amplifier removes
the voltage error encountered when measuring the output
voltage relative to the local controller ground reference point
resulting in a more accurate means of sensing output
voltage. Connect the microprocessor sense pins to the noninverting input, VSEN, and inverting input, RGND, of the
remote-sense amplifier. The remote-sense output, VDIFF, is
connected to the inverting input of the error amplifier through
an external resistor.
A digital to analog converter (DAC) generates a reference
voltage based on the state of logic signals at pins VID7
through VID0. The DAC decodes the 8-bit logic signal (VID)
into one of the discrete voltages shown in Table 1. Each VID
input offers a 45µA pull-up to an internal 2.5V source for use
with open-drain outputs. The pull-up current diminishes to
zero above the logic threshold to protect voltage-sensitive
output devices. External pull-up resistors can augment the
pull-up current sources if case leakage into the driving
device is greater than 45µA.
Load-Line Regulation
Some microprocessor manufacturers require a preciselycontrolled output resistance. This dependence of output
voltage on load current is often termed “droop” or “load line”
regulation. By adding a well controlled output impedance,
the output voltage can effectively be level shifted in a
direction which works to achieve the load-line regulation
required by these manufacturers.
FN9225.0
March 9, 2006
ISL6307B
TABLE 1. VR10 VID TABLE (WITH 6.25mV EXTENSION)
TABLE 1. VR10 VID TABLE (WITH 6.25mV EXTENSION)
VID4 VID3 VID2 VID1 VID0 VID5
VID6 VOLTAGE
400mV 200mV 100mV 50mV 25mV 12.5mV 6.25mV
(V)
VID6 VOLTAGE
VID4 VID3 VID2 VID1 VID0 VID5
(V)
400mV 200mV 100mV 50mV 25mV 12.5mV 6.25mV
0
1
0
1
0
1
1
1.6
1
0
1
0
0
0
0
1.35625
0
1
0
1
0
1
0
1.59375
1
0
1
0
0
1
1
1.35
0
1
0
1
1
0
1
1.5875
1
0
1
0
0
1
0
1.34375
0
1
0
1
1
0
0
1.58125
1
0
1
0
1
0
1
1.3375
0
1
0
1
1
1
1
1.575
1
0
1
0
1
0
0
1.33125
0
1
0
1
1
1
0
1.56875
1
0
1
0
1
1
1
1.325
0
1
1
0
0
0
1
1.5625
1
0
1
0
1
1
0
1.31875
0
1
1
0
0
0
0
1.55625
1
0
1
1
0
0
1
1.3125
0
1
1
0
0
1
1
1.55
1
0
1
1
0
0
0
1.30625
0
1
1
0
0
1
0
1.54375
1
0
1
1
0
1
1
1.3
0
1
1
0
1
0
1
1.5375
1
0
1
1
0
1
0
1.29375
0
1
1
0
1
0
0
1.53125
1
0
1
1
1
0
1
1.2875
0
1
1
0
1
1
1
1.525
1
0
1
1
1
0
0
1.28125
0
1
1
0
1
1
0
1.51875
1
0
1
1
1
1
1
1.275
0
1
1
1
0
0
1
1.5125
1
0
1
1
1
1
0
1.26875
0
1
1
1
0
0
0
1.50625
1
1
0
0
0
0
1
1.2625
0
1
1
1
0
1
1
1.5
1
1
0
0
0
0
0
1.25625
0
1
1
1
0
1
0
1.49375
1
1
0
0
0
1
1
1.25
0
1
1
1
1
0
1
1.4875
1
1
0
0
0
1
0
1.24375
0
1
1
1
1
0
0
1.48125
1
1
0
0
1
0
1
1.2375
0
1
1
1
1
1
1
1.475
1
1
0
0
1
0
0
1.23125
0
1
1
1
1
1
0
1.46875
1
1
0
0
1
1
1
1.225
1
0
0
0
0
0
1
1.4625
1
1
0
0
1
1
0
1.21875
1
0
0
0
0
0
0
1.45625
1
1
0
1
0
0
1
1.2125
1
0
0
0
0
1
1
1.45
1
1
0
1
0
0
0
1.20625
1
0
0
0
0
1
0
1.44375
1
1
0
1
0
1
1
1.2
1
0
0
0
1
0
1
1.4375
1
1
0
1
0
1
0
1.19375
1
0
0
0
1
0
0
1.43125
1
1
0
1
1
0
1
1.1875
1
0
0
0
1
1
1
1.425
1
1
0
1
1
0
0
1.18125
1
0
0
0
1
1
0
1.41875
1
1
0
1
1
1
1
1.175
1
0
0
1
0
0
1
1.4125
1
1
0
1
1
1
0
1.16875
1
0
0
1
0
0
0
1.40625
1
1
1
0
0
0
1
1.1625
1
0
0
1
0
1
1
1.4
1
1
1
0
0
0
0
1.15625
1
0
0
1
0
1
0
1.39375
1
1
1
0
0
1
1
1.15
1
0
0
1
1
0
1
1.3875
1
1
1
0
0
1
0
1.14375
1
0
0
1
1
0
0
1.38125
1
1
1
0
1
0
1
1.1375
1
0
0
1
1
1
1
1.375
1
1
1
0
1
0
0
1.13125
1
0
0
1
1
1
0
1.36875
1
1
1
0
1
1
1
1.125
1
0
1
0
0
0
1
1.3625
1
1
1
0
1
1
0
1.11875
16
FN9225.0
March 9, 2006
ISL6307B
TABLE 1. VR10 VID TABLE (WITH 6.25mV EXTENSION)
TABLE 1. VR10 VID TABLE (WITH 6.25mV EXTENSION)
VID6 VOLTAGE
VID4 VID3 VID2 VID1 VID0 VID5
(V)
400mV 200mV 100mV 50mV 25mV 12.5mV 6.25mV
VID4 VID3 VID2 VID1 VID0 VID5
VID6 VOLTAGE
400mV 200mV 100mV 50mV 25mV 12.5mV 6.25mV
(V)
1
1
1
1
0
0
1
1.1125
0
0
1
1
1
1
0
0.89375
1
1
1
1
0
0
0
1.10625
0
1
0
0
0
0
1
0.8875
1
1
1
1
0
1
1
1.1
0
1
0
0
0
0
0
0.88125
1
1
1
1
0
1
0
1.09375
0
1
0
0
0
1
1
0.875
1
1
1
1
1
0
1
OFF
0
1
0
0
0
1
0
0.86875
1
1
1
1
1
0
0
OFF
0
1
0
0
1
0
1
0.8625
1
1
1
1
1
1
1
OFF
0
1
0
0
1
0
0
0.85625
1
1
1
1
1
1
0
OFF
0
1
0
0
1
1
1
0.85
0
0
0
0
0
0
1
1.0875
0
1
0
0
1
1
0
0.84375
0
0
0
0
0
0
0
1.08125
0
1
0
1
0
0
1
0.8375
0
0
0
0
0
1
1
1.075
0
1
0
1
0
0
0
0.83125
0
0
0
0
0
1
0
1.06875
0
0
0
0
1
0
1
1.0625
0
0
0
0
1
0
0
1.05625
0
0
0
0
1
1
1
1.05
0
0
0
0
1
1
0
1.04375
0
0
0
1
0
0
1
1.0375
0
0
0
1
0
0
0
1.03125
0
0
0
1
0
1
1
1.025
0
0
0
1
0
1
0
1.01875
0
0
0
1
1
0
1
1.0125
0
0
0
1
1
0
0
1.00625
0
0
0
1
1
1
1
1
0
0
0
1
1
1
0
0.99375
0
0
1
0
0
0
1
0.9875
0
0
1
0
0
0
0
0.98125
0
0
1
0
0
1
1
0.975
0
0
1
0
0
1
0
0.96875
0
0
1
0
1
0
1
0.9625
0
0
1
0
1
0
0
0.95625
0
0
1
0
1
1
1
0.95
0
0
1
0
1
1
0
0.94375
0
0
1
1
0
0
1
0.9375
0
0
1
1
0
0
0
0.93125
0
0
1
1
0
1
1
0.925
0
0
1
1
0
1
0
0.91875
0
0
1
1
1
0
1
0.9125
0
0
1
1
1
0
0
0.90625
0
0
1
1
1
1
1
0.9
17
TABLE 2. VR11 VID 8-BIT
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0
VOLTAGE
0
0
0
0
0
0
0
0
OFF
0
0
0
0
0
0
0
1
OFF
0
0
0
0
0
0
1
0
1.60000
0
0
0
0
0
0
1
1
1.59375
0
0
0
0
0
1
0
0
1.58750
0
0
0
0
0
1
0
1
1.58125
0
0
0
0
0
1
1
0
1.57500
0
0
0
0
0
1
1
1
1.56875
0
0
0
0
1
0
0
0
1.56250
0
0
0
0
1
0
0
1
1.55625
0
0
0
0
1
0
1
0
1.55000
0
0
0
0
1
0
1
1
1.54375
0
0
0
0
1
1
0
0
1.53750
0
0
0
0
1
1
0
1
1.53125
0
0
0
0
1
1
1
0
1.52500
0
0
0
0
1
1
1
1
1.51875
0
0
0
1
0
0
0
0
1.51250
0
0
0
1
0
0
0
1
1.50625
0
0
0
1
0
0
1
0
1.50000
0
0
0
1
0
0
1
1
1.49375
0
0
0
1
0
1
0
0
1.48750
0
0
0
1
0
1
0
1
1.48125
0
0
0
1
0
1
1
0
1.47500
0
0
0
1
0
1
1
1
1.46875
0
0
0
1
1
0
0
0
1.46250
0
0
0
1
1
0
0
1
1.45625
FN9225.0
March 9, 2006
ISL6307B
TABLE 2. VR11 VID 8-BIT (Continued)
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0
TABLE 2. VR11 VID 8-BIT (Continued)
VOLTAGE
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0
VOLTAGE
0
0
0
1
1
0
1
0
1.45000
0
1
0
0
0
0
1
0
1.20000
0
0
0
1
1
0
1
1
1.44375
0
1
0
0
0
0
1
1
1.19375
0
0
0
1
1
1
0
0
1.43750
0
1
0
0
0
1
0
0
1.18750
0
0
0
1
1
1
0
1
1.43125
0
1
0
0
0
1
0
1
1.18125
0
0
0
1
1
1
1
0
1.42500
0
1
0
0
0
1
1
0
1.17500
0
0
0
1
1
1
1
1
1.41875
0
1
0
0
0
1
1
1
1.16875
0
0
1
0
0
0
0
0
1.41250
0
1
0
0
1
0
0
0
1.16250
0
0
1
0
0
0
0
1
1.40625
0
1
0
0
1
0
0
1
1.15625
0
0
1
0
0
0
1
0
1.40000
0
1
0
0
1
0
1
0
1.15000
0
0
1
0
0
0
1
1
1.39375
0
1
0
0
1
0
1
1
1.14375
0
0
1
0
0
1
0
0
1.38750
0
1
0
0
1
1
0
0
1.13750
0
0
1
0
0
1
0
1
1.38125
0
1
0
0
1
1
0
1
1.13125
0
0
1
0
0
1
1
0
1.37500
0
1
0
0
1
1
1
0
1.12500
0
0
1
0
0
1
1
1
1.36875
0
1
0
0
1
1
1
1
1.11875
0
0
1
0
1
0
0
0
1.36250
0
1
0
1
0
0
0
0
1.11250
0
0
1
0
1
0
0
1
1.35625
0
1
0
1
0
0
0
1
1.10625
0
0
1
0
1
0
1
0
1.35000
0
1
0
1
0
0
1
0
1.10000
0
0
1
0
1
0
1
1
1.34375
0
1
0
1
0
0
1
1
1.09375
0
0
1
0
1
1
0
0
1.33750
0
1
0
1
0
1
0
0
1.08750
0
0
1
0
1
1
0
1
1.33125
0
1
0
1
0
1
0
1
1.08125
0
0
1
0
1
1
1
0
1.32500
0
1
0
1
0
1
1
0
1.07500
0
0
1
0
1
1
1
1
1.31875
0
1
0
1
0
1
1
1
1.06875
0
0
1
1
0
0
0
0
1.31250
0
1
0
1
1
0
0
0
1.06250
0
0
1
1
0
0
0
1
1.30625
0
1
0
1
1
0
0
1
1.05625
0
0
1
1
0
0
1
0
1.30000
0
1
0
1
1
0
1
0
1.05000
0
0
1
1
0
0
1
1
1.29375
0
1
0
1
1
0
1
1
1.04375
0
0
1
1
0
1
0
0
1.28750
0
1
0
1
1
1
0
0
1.03750
0
0
1
1
0
1
0
1
1.28125
0
1
0
1
1
1
0
1
1.03125
0
0
1
1
0
1
1
0
1.27500
0
1
0
1
1
1
1
0
1.02500
0
0
1
1
0
1
1
1
1.26875
0
1
0
1
1
1
1
1
1.01875
0
0
1
1
1
0
0
0
1.26250
0
1
1
0
0
0
0
0
1.01250
0
0
1
1
1
0
0
1
1.25625
0
1
1
0
0
0
0
1
1.00625
0
0
1
1
1
0
1
0
1.25000
0
1
1
0
0
0
1
0
1.00000
0
0
1
1
1
0
1
1
1.24375
0
1
1
0
0
0
1
1
0.99375
0
0
1
1
1
1
0
0
1.23750
0
1
1
0
0
1
0
0
0.98750
0
0
1
1
1
1
0
1
1.23125
0
1
1
0
0
1
0
1
0.98125
0
0
1
1
1
1
1
0
1.22500
0
1
1
0
0
1
1
0
0.97500
0
0
1
1
1
1
1
1
1.21875
0
1
1
0
0
1
1
1
0.96875
0
1
0
0
0
0
0
0
1.21250
0
1
1
0
1
0
0
0
0.96250
0
1
0
0
0
0
0
1
1.20625
0
1
1
0
1
0
0
1
0.95625
18
FN9225.0
March 9, 2006
ISL6307B
TABLE 2. VR11 VID 8-BIT (Continued)
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0
TABLE 2. VR11 VID 8-BIT (Continued)
VOLTAGE
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0
VOLTAGE
0
1
1
0
1
0
1
0
0.95000
1
0
0
1
0
0
1
0
0.70000
0
1
1
0
1
0
1
1
0.94375
1
0
0
1
0
0
1
1
0.69375
0
1
1
0
1
1
0
0
0.93750
1
0
0
1
0
1
0
0
0.68750
0
1
1
0
1
1
0
1
0.93125
1
0
0
1
0
1
0
1
0.68125
0
1
1
0
1
1
1
0
0.92500
1
0
0
1
0
1
1
0
0.67500
0
1
1
0
1
1
1
1
0.91875
1
0
0
1
0
1
1
1
0.66875
0
1
1
1
0
0
0
0
0.91250
1
0
0
1
1
0
0
0
0.66250
0
1
1
1
0
0
0
1
0.90625
1
0
0
1
1
0
0
1
0.65625
0
1
1
1
0
0
1
0
0.90000
1
0
0
1
1
0
1
0
0.65000
0
1
1
1
0
0
1
1
0.89375
1
0
0
1
1
0
1
1
0.64375
0
1
1
1
0
1
0
0
0.88750
1
0
0
1
1
1
0
0
0.63750
0
1
1
1
0
1
0
1
0.88125
1
0
0
1
1
1
0
1
0.63125
0
1
1
1
0
1
1
0
0.87500
1
0
0
1
1
1
1
0
0.62500
0
1
1
1
0
1
1
1
0.86875
1
0
0
1
1
1
1
1
0.61875
0
1
1
1
1
0
0
0
0.86250
1
0
1
0
0
0
0
0
0.61250
0
1
1
1
1
0
0
1
0.85625
1
0
1
0
0
0
0
1
0.60625
0
1
1
1
1
0
1
0
0.85000
1
0
1
0
0
0
1
0
0.60000
0
1
1
1
1
0
1
1
0.84375
1
0
1
0
0
0
1
1
0.59375
0
1
1
1
1
1
0
0
0.83750
1
0
1
0
0
1
0
0
0.58750
0
1
1
1
1
1
0
1
0.83125
1
0
1
0
0
1
0
1
0.58125
0
1
1
1
1
1
1
0
0.82500
1
0
1
0
0
1
1
0
0.57500
0
1
1
1
1
1
1
1
0.81875
1
0
1
0
0
1
1
1
0.56875
1
0
0
0
0
0
0
0
0.81250
1
0
1
0
1
0
0
0
0.56250
1
0
0
0
0
0
0
1
0.80625
1
0
1
0
1
0
0
1
0.55625
1
0
0
0
0
0
1
0
0.80000
1
0
1
0
1
0
1
0
0.55000
1
0
0
0
0
0
1
1
0.79375
1
0
1
0
1
0
1
1
0.54375
1
0
0
0
0
1
0
0
0.78750
1
0
1
0
1
1
0
0
0.53750
1
0
0
0
0
1
0
1
0.78125
1
0
1
0
1
1
0
1
0.53125
1
0
0
0
0
1
1
0
0.77500
1
0
1
0
1
1
1
0
0.52500
1
0
0
0
0
1
1
1
0.76875
1
0
1
0
1
1
1
1
0.51875
1
0
0
0
1
0
0
0
0.76250
1
0
1
1
0
0
0
0
0.51250
1
0
0
0
1
0
0
1
0.75625
1
0
1
1
0
0
0
1
0.50625
1
0
0
0
1
0
1
0
0.75000
1
0
1
1
0
0
1
0
0.50000
1
0
0
0
1
0
1
1
0.74375
1
1
1
1
1
1
1
0
OFF
1
0
0
0
1
1
0
0
0.73750
1
1
1
1
1
1
1
1
OFF
1
0
0
0
1
1
0
1
0.73125
1
0
0
0
1
1
1
0
0.72500
1
0
0
0
1
1
1
1
0.71875
1
0
0
1
0
0
0
0
0.71250
1
0
0
1
0
0
0
1
0.70625
19
In other cases, the designer may determine that a more
cost-effective solution can be achieved by adding droop.
Droop can help to reduce the output-voltage spike that
results from fast load-current demand changes.
FN9225.0
March 9, 2006
ISL6307B
The magnitude of the spike is dictated by the ESR and ESL
of the output capacitors selected. By positioning the no-load
voltage level near the upper specification limit, a larger
negative spike can be sustained without crossing the lower
limit. By adding a well controlled output impedance, the
output voltage under load can effectively be level shifted
down so that a larger positive spike can be sustained without
crossing the upper specification limit.
As shown in Figure 8, a current proportional to the average
current in all active channels, IAVG, flows from FB through a
load-line regulation resistor, RFB. The resulting voltage drop
across RFB is proportional to the output current, effectively
creating an output voltage droop with a steady-state value
defined as
V DROOP = I AVG R FB
Once the desired output offset voltage has been determined,
use the following formulas to set ROFS:
For Positive Offset (connect ROFS to VCC):
1.6 × R REF
R OFS = ----------------------------V OFFSET
(EQ. 11)
For Negative Offset (connect ROFS to GND):
0.4 × R REF
R OFS = ----------------------------V OFFSET
(EQ. 12)
FB
(EQ. 8)
DYNAMIC
VID D/A
The regulated output voltage is reduced by the droop voltage
VDROOP. The output voltage as a function of load current is
derived by combining Equation 8 with the appropriate
sample current expression defined by the current sense
method employed.
 I OUT R X

- ------------------ R FB
V OUT = V REF – V OFFSET –  ----------- 6 R ISEN

RREF
E/A
REF
(EQ. 9)
Where VREF is the reference voltage, VOFS is the
programmed offset voltage, IOUT is the total output current
of the converter, RISEN is the sense resistor in the ISEN line,
N is the number of active channels, and RFB is the feedback
resistor. RX has a value of DCR, resistor or RDS(ON), or
RSENSE depending on the sensing method.
Therefore the equivalent loadline impedance, i.e. Droop
impedance, is equal to:
R FB R X
-----------------R LL = -----------N R ISEN
DAC
VCC
OR
GND
1.6V
-
ROFS
+
+
0.4V
VCC
-
ISL6307BCR
OFS
GND
FIGURE 9. OUTPUT VOLTAGE OFFSET PROGRAMMING
WITH ISL6307B
(EQ. 10)
Dynamic VID
Output-Voltage Offset Programming
The ISL6307B allows the designer to accurately adjust the
offset voltage. When a resistor, ROFS, is connected between
OFS to VCC, the voltage across it is regulated to 1.6V. This
causes a proportional current (IOFS) to flow into OFS. If
ROFS is connected to ground, the voltage across it is
regulated to 0.4V, and IOFS flows out of OFS. A resistor
between DAC and REF, RREF, is selected so that the
product (IOFS x ROFS) is equal to the desired offset voltage.
These functions are shown in Figure 9.
As it may be noticed in Figure 9, the OFSOUT pin must be
connected to the REF pin for this current injection to function
in ISL6307B. The current flow through RREF creates an
offset at the REF pin, which is ultimately duplicated at the
output of the regulator.
20
Modern microprocessors need to make changes to their
core voltage as part of normal operation. They direct the
core-voltage regulator to do this by making changes to the
VID inputs during regulator operation. The power
management solution is required to monitor the DAC inputs
and respond to on-the-fly VID changes in a controlled
manner. Supervising the safe output voltage transition within
the DAC range of the processor without discontinuity or
disruption is a necessary function of the core-voltage
regulator.
The ISL6307B checks the VID inputs six times every
switching cycle. If the VID code is found to have been
changed, the controller waits half of a complete cycle before
executing a 12.5mV change. If during the half-cycle wait
period, the difference between DAC level and the new VID
code changes, no change is made. If the VID code is more
than 1-bit higher or lower than the DAC (not recommended),
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ISL6307B
the controller will execute 12.5mV changes six times per
cycle until VID and DAC are equal. It is for this reason that it
is important to carefully control the rate of VID stepping in
1-bit increments.
In order to ensure the smooth transition of output voltage
during VID change, a VID step change smoothing network
composed of RREF and CREF is required for an ISL6307B
based voltage regulator. The selection of RREF is based on
the desired offset as detailed above in Output-Voltage Offset
Programming. The selection of CREF is based on the time
duration for 1-bit VID change and the allowable delay time.
Assuming the microprocessor controls the VID change at
1-bit every TVID, the relationship between the time constant
of RREF and CREF network and TVID is given by
Equation 13.
(EQ. 13)
C REF R REF = T VID
Operation Initialization
Prior to converter initialization, proper conditions must exist
on the enable inputs and VCC. When the conditions are met,
the controller begins soft-start. Once the output voltage is
within the proper window of operation, VR_RDY asserts a
logic 1.
ISL6307B INTERNAL CIRCUIT
EXTERNAL CIRCUIT
+12V
VCC
POR
CIRCUIT
ENABLE
COMPARATOR
10kΩ
EN_PWR
+
-
910Ω
0.875V
+
EN_VTT
-
0.875V
following input conditions must be met before the ISL6307B
is released from shutdown mode.
1. The bias voltage applied at VCC must reach the internal
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
the ISL6307B is guaranteed. Hysteresis between the
rising and falling thresholds assure that once enabled,
the ISL6307B will not inadvertently turn off unless the
bias voltage drops substantially (see Electrical
Specifications).
2. The ISL6307B features an enable input (EN_PWR) for
power sequencing between the controller bias voltage
and another voltage rail. The enable comparator holds
the ISL6307B in shutdown until the voltage at EN_PWR
rises above 0.875V. The enable comparator has about
130mV of hysteresis to prevent bounce. It is important
that the driver ICs reach their POR level before the
ISL6307B becomes enabled. The schematic in Figure 10
demonstrates sequencing the ISL6307B with the
ISL66xx family of Intersil MOSFET drivers, which require
12V bias.
3. The voltage on EN_VTT must be higher than 0.875V to
enable the controller. This pin is typically connected to the
output of VTT VR.
When all conditions above are satisfied, ISL6307B begins
the soft-start and ramps the output voltage to 1.1V first. After
remaining at 1.1V for some time, ISL6307B reads the VID
code at VID input pins. If the VID code is valid, ISL6307B will
regulate the output to the final VID setting. If the VID code is
OFF code, ISL6307B will shut down. Cycling Vcc, EN_PWR
or EN_VTT is needed to restart.
Soft-start
ISL6307B based VR has 4 periods during soft-start, as
shown in Figure 11. After Vcc, EN_VTT and EN_PWR reach
their POR and enable thresholds, The controller will have
fixed delay period TD1. After this delay period, the VR will
begin first soft-start ramp until the output voltage reaches
1.1V, Vboot voltage. Then, the controller will regulate the VR
voltage at 1.1V for another fixed period, TD3. At the end of
TD3 period, ISL6307B will read the VID signals. If the VID
code is valid, ISL6307B will initiate the second soft-start
ramp until the voltage reaches the VID voltage minus offset
voltage.
The soft-start time is the sum of the 4 periods as shown in
the following equation.
SOFT-START
AND
FAULT LOGIC
T SS = TD1 + TD2 + TD3 + TD4
FIGURE 10. POWER SEQUENCING USING THRESHOLDSENSITIVE ENABLE (EN) FUNCTION
Enable and Disable
While in shutdown mode, the PWM outputs are held in a
high-impedance state to assure the drivers remain off. The
21
(EQ. 14)
TD1 is the fixed delay with typical value as 1.36ms. TD3 is
determined by the fixed 85µs plus the time to obtain valid
VID voltage. If the VID is valid before the output reaches the
1.1V, the minimum time to valid the VID input is 500ns.
Therefore the minimum TD3 is about 86µs.
During TD2 and TD4, ISL6307B digitally controls the DAC
voltage change at 6.25mV per step. The time for each step is
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ISL6307B
determined by the frequency of the soft-start oscillator which
is defined by the resistor Rss from SS pin to GND. The 2
soft-start ramp times, Assuming the output voltage is 0V
before soft-start, TD2 and TD4 can be calculated based on
the following equations.
UV
(EQ. 15)
(EQ. 16)
For example, when VID is set to 1.5V and the Rss is set at
100kΩ, the first soft-start ramp time TD2 will be 704µs and
the second soft-start ramp time TD4 will be 256µs.
100µA
+
I1
REPEAT FOR
EACH CHANNEL
50%
( V VID – 1.1 )xR SS
TD4 = ------------------------------------------------ ( µs )
6.25x25
OC
-
+
1.1xR SS
TD2 = ------------------------ ( µs )
6.25x25
VR_RDY
DAC
REFERENCE
SOFT-START, FAULT
-
100µA
+
IAVG
OC1
AND CONTROL LOGIC
IAVG
IOUT
+
VDIFF
VOUT, 500mV/DIV
+
OC2
OV
-
-
R IOUT
2V
OVP
VID + 0.175V
VR_RDY, 5V/DIV
FIGURE 12. POWER GOOD AND PROTECTION CIRCUITRY
TD1
TD2
TD3 TD4
TD5
EN_VTT, 1V/DIV
500µs/DIV
FIGURE 11. SOFT-START WAVEFORMS
Fault Monitoring and Protection
The ISL6307B actively monitors output voltage and current
to detect fault conditions. Fault monitors trigger protective
measures to prevent damage to a microprocessor load. One
common power good indicator is provided for linking to
external system monitors. The schematic in Figure 12
outlines the interaction between the fault monitors and the
power good signal.
VR_RDY Signal
The VR_RDY pin is an open-drain logic output to indicate
that the soft-start period is completed and the output voltage
is within the regulated range. VR_RDY is pulled low during
shutdown and releases high after a successful soft-start and
a fix delay time, TD5. TD5 is fixed delay with typical value at
85µs. VR_RDY will be pulled low when an undervoltage or
overvoltage condition is detected, or the controller is
disabled by a reset from EN_PWR, EN_VTT, POR, or VID
OFF-code.
22
Undervoltage Detection
The undervoltage threshold is set at 50% of the VID voltage.
When the output voltage at VSEN is below the undervoltage
threshold, VR_RDY gets pulled low. When the output
voltage comes back to 60% of the VID voltage, VR_RDY will
return back to high.
Overvoltage Protection
Regardless of the VR being enabled or not, the ISL6307B
overvoltage protection (OVP) circuit will be active after its
POR. The OVP thresholds are different under different
operation conditions. When VR is not enabled and before
the 2nd soft-start, the OVP threshold is 1.275V. Once the
controller detects a valid VID input, the OVP trip point will be
changed to the VID voltage plus 175mV.
Two actions are taken by the ISL6307B to protect the
microprocessor load when an overvoltage condition occurs.
At the inception of an overvoltage event, all PWM outputs
are commanded low instantly (less than 20ns) until the
voltage at VDIFF falls below 0.4V. This causes the Intersil
drivers to turn on the lower MOSFETs and pull the output
voltage below a level that might cause damage to the load.
The PWM outputs remain low until VDIFF falls below 0.4V,
and then PWM signals enter a high-impedance state. The
Intersil drivers respond to the high-impedance input by
turning off both upper and lower MOSFETs. If the
overvoltage condition reoccurs, the ISL6307B will again
command the lower MOSFETs to turn on. The ISL6307B will
continue to protect the load in this fashion as long as the
overvoltage condition recurs.
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ISL6307B
Once an overvoltage condition is detected, normal PWM
operation ceases until the ISL6307B is reset. Cycling the
voltage on EN_PWR, EN_VTT or VCC below the PORfalling threshold will reset the controller. Cycling the VID
codes will not reset the controller.
OUTPUT CURRENT, 50A/DIV
Overcurrent Protection
ISL6307B has two levels of overcurrent protection. Each
phase is protected from a sustained overcurrent condition on
a delayed basis, while the combined phase currents are
protected on an instantaneous basis.
In instantaneous protection mode, the ISL6307B takes
advantage of the proportionality between the load current
and the average current, IAVG, to detect an overcurrent
condition. See the Channel-Current Balance section for
more detail on how the average current is measured. The
average current is continually compared with a constant
100µA reference current as shown in Figure 12. Once the
average current exceeds the reference current, a
comparator triggers the converter to shutdown.
In individual overcurrent protection mode, the ISL6307B
continuously compares the current of each channel with the
same 100µA reference current. If any channel current
exceeds the reference current continuously for eight
consecutive cycles, the comparator triggers the converter to
shutdown.
The overcurrent protection level for the above two OCP
modes can be adjusted by changing the value of current
sensing resistors. In addition, ISL6307 can also adjust the
average OCP threshold level by adjusting the value of the
resistor from IOUT to GND. This provides additional safety
for the voltage regulator.
The following equation can be used to calculate the value of
the resistor RIOUT based on the desired OCP level IAVG,
OCP2.
2
R IOUT = ------------------------------I AVG, OCP2
(EQ. 17)
23
0A
OUTPUT VOLTAGE,
500mV/DIV
0V
2ms/DIV
FIGURE 13. OVERCURRENT BEHAVIOR IN HICCUP MODE.
FSW = 500kHz
At the beginning of overcurrent shutdown, the controller
places all PWM signals in a high-impedance state within
20ns commanding the Intersil MOSFET driver ICs to turn off
both upper and lower MOSFETs. The system remains in this
state a period of 4096 switching cycles. If the controller is still
enabled at the end of this wait period, it will attempt a softstart. If the fault remains, the trip-retry cycles will continue
indefinitely (as shown in Figure 13) until either controller is
disabled or the fault is cleared. Note that the energy
delivered during trip-retry cycling is much less than during
full-load operation, so there, there is no thermal hazard
during this kind of operation.
Current Sense Output
The ISL6307B has 2 current sense output pins IDROOP and
IOUT; they are identical. In typical application, IDROOP pin
is connected to FB pin for the application where load line is
required. IOUT pin was designed for load current
measurement. As shown in typical application schematics
on pages 4 to 7, load current information can be obtained by
measuring the voltage at IOUT pin with a resistor connecting
IOUT PIN to ground. When the programmable temperature
compensation function of ISL6307B is properly used, the
output current at IOUT pin is proportional to load current as
shown in Figure 14.
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March 9, 2006
ISL6307B
VCC
VR_FAN
V_IOUT, 200mV/DIV
RTM1
0.33VCC
VR_HOT
TM
RNTC
oc
0.28VCC
0A
50A
100A
FIGURE 14. VOLTAGE AT IOUT PIN WITH A NTC NETWORK
PLACED BETWEEN IOUT TO GROUND WHEN
LOAD CURRENT CHANGES
FIGURE 15. BLOCK DIAGRAM OF THERMAL MONITORING
FUNCTION
V TM / V CC vs. Tem perature
There are two thermal signals to indicate the temperature
status of the voltage regulator: VR_HOT and VR_FAN. Both
VR_FAN and VR_HOT are open-drain output, and external
pull-up resistors are required.
VR_FAN signal indicates that the temperature of the voltage
regulator is high and more cooling airflow is needed.
VR_HOT signal can be used to inform the system that the
temperature of the voltage regulator is too high and the CPU
should reduce its power consumption. VR_HOT signal may
be tied to the CPU’s PROCHOT# signal.
The diagram of thermal monitoring function block is shown in
Figure 15. One NTC resistor should be placed close to the
power stage of the voltage regulator to sense the operational
temperature, and one pull-up resistor is needed to form the
voltage divider for TM pin. As the temperature of the power
stage increases, the resistance of the NTC will reduce,
resulting in the reduced voltage at TM pin. Figure 16 shows
the TM voltage over the temperature for a typical design with
a recommended 6.8kΩ NTC (P/N: NTHS0805N02N6801
from Vishay) and 1kΩ resistor RTM1. We recommend using
those resistors for the accurate temperature compensation.
There are two comparators with hysteresis to compare the
TM pin voltage to the fixed thresholds for VR_FAN and
VR_HOT signals respectively. VR_FAN signal is set to high
when TM voltage is lower than 33% of Vcc voltage, and is
pulled to GND when TM voltage increases to above 39% of
Vcc voltage. VR_HOT is set to high when TM voltage goes
below 28% of Vcc voltage, and is pulled to GND when TM
voltage goes back to above 33% of Vcc voltage. Figure 17
shows the operation of those signals.
24
90%
80%
V TM / V CC
Thermal monitoring (VR_HOT/VR_FAN)
100%
70%
60%
50%
40%
30%
20%
0
20
40
60
80
100
Tem perature ( oC)
120
140
FIGURE 16. THE RATIO OF TM VOLTAGE TO NTC
TEMPERATURE WITH RECOMMENDED PARTS
TM
0.39*Vcc
0.33*Vcc
0.28*Vcc
VR_FAN
VR_HOT
Temperature
T1
T2
T3
FIGURE 17. VR_HOTAND VR_FAN SIGNAL vs TM VOLTAGE
FN9225.0
March 9, 2006
ISL6307B
Based on the NTC temperature characteristics and the
desired threshold of VR_HOT signal, the pull-up resistor
RTM1 of TM pin is given by:
R TM1 = 2.75xR NTC ( T3 )
VCC
(EQ. 18)
RNTC(T3) is the NTC resistance at the VR_HOT threshold
temperature T3.
The NTC resistance at the set point T2 and release point T1
of VR_FAN signal can be calculated as:
R NTC ( T2 ) = 1.267xR NTC ( T3 )
(EQ. 19)
Isen6
RTM1
TM
oc
Channel current sense
Non-linear
A/D
Isen2
RNTC
I6
D/A
VCC
Isen5
Isen4
Isen3
I5
I4
I3
I2
I1
Isen1
ki
RTC1
R NTC ( T1 ) = 1.644xR NTC ( T3 )
(EQ. 20)
With the NTC resistance value obtained from Equations 19
& 20, the temperature value T2 and T1 can be found from
the NTC datasheet.
Temperature Compensation
ISL6307B supports inductor DCR sensing, MOSFET
RDS(ON) sensing, or resistive sensing techniques. Both
inductor DCR and MSOFET RDS(ON) have the positive
temperature coefficient, which is about +0.38%/°C. Because
the voltage across inductor or MOSFET is sensed for the
output current information, the sensed current has the same
positive temperature coefficient as the inductor DCR or
MOSFET RDS(ON).
In order to obtain the correct current information, there
should be a way to correct the temperature impact on the
current sense component. ISL6307B provides two methods:
integrated temperature compensation and external
temperature compensation.
Integrated Temperature Compensation
When TCOMP voltage is equal or greater than Vcc/15,
ISL6307B will utilize the voltage at TM and TCOMP pins to
compensate the temperature impact on the sensed current.
The block diagram of this function is shown in Figure 18.
TCOMP
4-bit
A/D
Droop, Iout &
Over current protection
RTC2
FIGURE 18. BLOCK DIAGRAM OF INTEGRATED
TEMPERATURE COMPENSATION
When the TM NTC is placed close to the current sense
component (inductor or MOSFET), the temperature of the
NTC will track the temperature of the current sense
component. Therefore, the TM voltage can be utilized to
obtain the temperature of the current sense component.
Based on Vcc voltage, ISL6307B converts the TM pin
voltage to a 6-bit TM digital signal for temperature
compensation. With the non-linear A/D converter of
ISL6307B, TM digital signal is linearly proportional to the
NTC temperature. For accurate temperature compensation,
the ratio of the TM voltage to the NTC temperature of the
practical design should be similar to that in Figure 16.
Depending on the location of the NTC and the air-flowing,
the NTC may be cooler or hotter than the current sense
component. TCOMP pin voltage can be utilized to correct
the temperature difference between NTC and the current
sense component. When a different NTC type or different
voltage divider is used for the TM function, TCOMP voltage
can also be used to compensate for the difference between
the recommended TM voltage curve in Figure 16 and that of
the actual design. According to the Vcc voltage, ISL6307B
converts the TCOMP pin voltage to a 4-bit TCOMP digital
signal as TCOMP factor N.
TCOMP factor N is an integer between 0 and 15. The
integrated temperature compensation function is disabled for
N = 0. For N = 4, the NTC temperature is equal to the
temperature of the current sense component. For N < 4, the
NTC is hotter than the current sense component. The NTC is
cooler than the current sense component for N > 4. When
N>4, the larger TCOMP factor N, the larger the difference
between the NTC temperature and the temperature of the
current sense component.
25
FN9225.0
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ISL6307B
ISL6307B multiplexes the TCOMP factor N with the TM
digital signal to obtain the adjustment gain to compensate
the temperature impact on the sensed channel current. The
compensated channel current signal is used for droop and
overcurrent protection functions.
Design Procedure:
1. Properly choose the voltage divider for TM pin to match
the TM voltage Vs temperature curve with the
recommended curve in Figure 16.
COMP
FB
IDROOP
2. Run the actual board under the full load and the desired
cooling condition.
3. After the board reaches the thermal steady state, record
the temperature (TCSC) of the current sense component
(inductor or MOSFET) and the voltage at TM and Vcc
pins.
4. Use the following equation to calculate the resistance of
the TM NTC, and find out the corresponding NTC
temperature TNTC from the NTC datasheet.
V TM xR
TM1
R NTC ( T
= ------------------------------)
V CC – V
NTC
TM
(EQ. 21)
5. Use the following equation to calculate the TCOMP factor
N:
209x ( T CSC – T
)
NTC
N = -------------------------------------------------------+4
3xT NTC + 400
(EQ. 22)
6. Choose an integral number close to the above result for
the TCOMP factor. If this factor is higher than 15, use
N=15. If it is less than 1, use N = 1.
7. Choose the pull-up resistor RTC1 (typical 10kΩ).
8. If N = 15, do not need the pull-down resistor RTC2,
otherwise obtain RTC2 by the following equation:
NxR TC1
R TC2 = ---------------------15 – N
(EQ. 23)
9. Run the actual board under full load again with the proper
resistors to TCOMP pin.
10. Record the output voltage as V1 immediately after the
output voltage is stable with the full load; Record the
output voltage as V2 after the VR reaches the thermal
steady state.
11. If the output voltage increases over 2mV as the
temperature increases, i.e. V2-V1 > 2mV, reduce N and
redesign RTC2; if the output voltage decreases over 2mV
as the temperature increases, i.e. V1-V2 > 2mV, increase
N and redesign RTC2.
The design spreadsheet is available for those calculations.
External Temperature Compensation
By setting the voltage of TCOMP pin to 0, the integrated
temperature compensation function is disabled. And one
external temperature compensation network, shown in
Figure 18, can be used to cancel the temperature impact on
the droop (i.e. load line).
26
oc
VDIFF
FIGURE 19. VOLTAGE AT IDROOP PIN WITH A RESISTOR
PLACED FROM IDROOP PIN TO GND WHEN
LOAD CURRENT CHANGES
The sensed current will flow out of IDROOP pin and develop
the droop voltage across the resistor (RFB) between FB and
VDIFF pins. If RFB resistance reduces as the temperature
increases, the temperature impact on the droop can be
compensated. A NTC resistor can be placed close to the
power stage and used to form RFB. Due to the non-linear
temperature characteristics of the NTC, a resistor network is
needed to make the equivalent resistance between FB and
VDIFF pin is reverse proportional to the temperature.
The external temperature compensation network can only
compensate the temperature impact on the droop, while it
has no impact to the sensed current inside ISL6307B.
Therefore this network cannot compensate for the
temperature impact on the overcurrent protection function.
General Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to create a multiphase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced below. In
addition to this guide, Intersil provides complete reference
designs that include schematics, bills of materials, and
example board layouts for all common microprocessor
applications.
Power Stages
The first step in designing a multiphase converter is to
determine the number of phases. This determination
depends heavily on the cost analysis which in turn depends
on system constraints that differ from one design to the next.
Principally, the designer will be concerned with whether
components can be mounted on both sides of the circuit
board; whether through-hole components are permitted; and
the total board space available for power-supply circuitry.
Generally speaking, the most economical solutions are
those in which each phase handles between 15 and 20A. All
surface-mount designs will tend toward the lower end of this
current range. If through-hole MOSFETs and inductors can
FN9225.0
March 9, 2006
ISL6307B
be used, higher per-phase currents are possible. In cases
where board space is the limiting constraint, current can be
pushed as high as 40A per phase, but these designs require
heat sinks and forced air to cool the MOSFETs, inductors
and heat-dissipating surfaces.
the required time for this commutation is t1 and the
approximated associated power loss is PUP,1.
MOSFETS
At turn on, the upper MOSFET begins to conduct and this
transition occurs over a time t2. In Equation 27, the
approximate power loss is PUP,2.
The choice of MOSFETs depends on the current each
MOSFET will be required to conduct; the switching
frequency; the capability of the MOSFETs to dissipate heat;
and the availability and nature of heat sinking and air flow.
I M I P-P  t 1 
P UP,1 ≈ V IN  -----  ----  f
 N- + ---------2   2 S
I M I P-P  t 2 
P UP, 2 ≈ V IN  -----  ----  f
 N- – ---------2  2 S
(EQ. 26)
(EQ. 27)
LOWER MOSFET POWER CALCULATION
The calculation for heat dissipated in the lower MOSFET is
simple, since virtually all of the heat loss in the lower
MOSFET is due to current conducted through the channel
resistance (RDS(ON)). In Equation 24, IM is the maximum
continuous output current; IP-P is the peak-to-peak inductor
current (see Equation 1); d is the duty cycle (VOUT/VIN); and
L is the per-channel inductance.
P LOW, 1 = R DS ( ON )
I L, 2P-P ( 1 – d )
 I M 2
  ( 1 – d ) + --------------------------------------- N
(EQ. 24)
12
An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the
dead time when inductor current is flowing through the
lower-MOSFET body diode. This term is dependent on the
diode forward voltage at IM, VD(ON); the switching
frequency, fS; and the length of dead times, td1 and td2, at
the beginning and the end of the lower-MOSFET conduction
interval respectively.
I

I M I P-P
(EQ. 25)
M I P-P t
P LOW, 2 = V D ( ON ) f S  ----- t d1 +  ----- – ----------- d2
 N- + ---------2 
N
2 
Thus the total maximum power dissipated in each lower
MOSFET is approximated by the summation of PLOW,1 and
PLOW,2.
UPPER MOSFET POWER CALCULATION
In addition to RDS(ON) losses, a large portion of the upperMOSFET losses are due to currents conducted across the
input voltage (VIN) during switching. Since a substantially
higher portion of the upper-MOSFET losses are dependent
on switching frequency, the power calculation is more
complex. Upper MOSFET losses can be divided into
separate components involving the upper-MOSFET
switching times; the lower-MOSFET body-diode reverserecovery charge, Qrr; and the upper MOSFET RDS(ON)
conduction loss.
When the upper MOSFET turns off, the lower MOSFET does
not conduct any portion of the inductor current until the
voltage at the phase node falls below ground. Once the
lower MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
ramps up to assume the full inductor current. In Equation 26,
27
A third component involves the lower MOSFET’s reverserecovery charge, Qrr. Since the inductor current has fully
commutated to the upper MOSFET before the lowerMOSFET’s body diode can draw all of Qrr, it is conducted
through the upper MOSFET across VIN. The power
dissipated as a result is PUP,3 and is approximately
P UP,3 = V IN Q rr f S
(EQ. 28)
Finally, the resistive part of the upper MOSFET’s is given in
Equation 29 as PUP,4.
The total power dissipated by the upper MOSFET at full load
can now be approximated as the summation of the results
from Equations 26, 27, 28 and 29. Since the power
equations depend on MOSFET parameters, choosing the
correct MOSFETs can be an iterative process involving
repetitive solutions to the loss equations for different
MOSFETs and different switching frequencies.
2
2
I P-P
 I M
P UP,4 ≈ R DS ( ON )  ----- d + ----------- d
12
 N
(EQ. 29)
Current Sensing Resistor
The resistors connected between these ISEN+ pins and the
respective phase nodes or output side of the output inductor
determine the gains in the load-line regulation loop and the
channel-current balance loop as well as setting the
overcurrent trip point. Select values for these resistors based
on the room temperature RDS(ON) of the lower MOSFETs,
DCR of inductor or additional resistor; the full-load operating
current, IFL; and the number of phases, N using Equation 30.
RX
R ISEN = ---------------------50 ×10 – 6
I FL
------N
(EQ. 30)
In certain circumstances, it may be necessary to adjust the
value of one or more ISEN resistors. When the components
of one or more channels are inhibited from effectively
dissipating their heat so that the affected channels run hotter
than desired, choose new, smaller values of RISEN for the
affected phases (see the section entitled Channel-Current
Balance). Choose RISEN,2 in proportion to the desired
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March 9, 2006
ISL6307B
decrease in temperature rise in order to cause proportionally
less current to flow in the hotter phase.
(EQ. 31)
RC
In Equation 31, make sure that ∆T2 is the desired temperature
rise above the ambient temperature, and ∆T1 is the measured
temperature rise above the ambient temperature. While a
single adjustment according to Equation 31 is usually
sufficient, it may occasionally be necessary to adjust RISEN
two or more times to achieve optimal thermal balance
between all channels.
CC
COMP
FB
+
RFB
VDROOP
IDROOP
ISL6307B
∆T
R ISEN ,2 = R ISEN ----------2
∆T 1
C2 (OPTIONAL)
VDIFF
Load-Line Regulation Resistor
The load-line regulation resistor is labeled RFB in Figure 8.
Its value depends on the desired full-load droop voltage
(VDROOP in Figure 8). If Equation 30 is used to select each
ISEN resistor, the load-line regulation resistor is as shown in
Equation 32.
V DROOP
R FB = -----------------------–6
50 ×10
(EQ. 32)
If one or more of the ISEN resistors are adjusted for thermal
balance, as in Equation 31, the load-line regulation resistor
should be selected according to Equation 33 where IFL is the
full-load operating current and RISEN(n) is the ISEN resistor
connected to the nth ISEN pin.
V DROOP
R FB = --------------------------------I FL R DS ( ON )
∑ RISEN ( n )
(EQ. 33)
n
FIGURE 20. COMPENSATION CONFIGURATION FOR
LOAD-LINE REGULATED ISL6307B CIRCUIT
The feedback resistor, RFB, has already been chosen as
outlined in Load-Line Regulation Resistor. Select a target
bandwidth for the compensated system, f0. The target
bandwidth must be large enough to assure adequate
transient performance, but smaller than 1/3 of the perchannel switching frequency. The values of the
compensation components depend on the relationships of f0
to the L-C pole frequency and the ESR zero frequency. For
each of the three cases which follow, there are a separate
set of equations for the compensation components.
Case 1:
1
------------------- > f 0
2π LC
2πf 0 V P-P LC
R C = R FB -------------------------------------0.75V
Compensation
IN
The two opposing goals of compensating the voltage
regulator are stability and speed. Depending on whether the
regulator employs the optional load-line regulation as
described in Load-Line Regulation, there are two distinct
methods for achieving these goals.
COMPENSATING LOAD-LINE REGULATED CONVERTER
0.75V IN
C C = ------------------------------------2πV P-P R FB f 0
Case 2:
The load-line regulated converter behaves in a similar
manner to a peak-current mode controller because the two
poles at the output-filter L-C resonant frequency split with
the introduction of current information into the control loop.
The final location of these poles is determined by the system
function, the gain of the current signal, and the value of the
compensation components, RC and CC.
Since the system poles and zero are affected by the values
of the components that are meant to compensate them, the
solution to the system equation becomes fairly complicated.
Fortunately there is a simple approximation that comes very
close to an optimal solution. Treating the system as though it
were a voltage-mode regulator by compensating the L-C
poles and the ESR zero of the voltage-mode approximation
yields a solution that is always stable with very close to ideal
transient performance.
28
1
1
------------------- ≤ f 0 < ----------------------------2πC ( ESR )
2π LC
V P-P ( 2π ) 2 f 02 LC
R C = R FB ---------------------------------------------0.75 V
(EQ. 34)
IN
0.75V IN
C C = -------------------------------------------------------------2
( 2π ) f 02 V P-P R FB LC
Case 3:
1
f 0 > -----------------------------2πC ( ESR )
2π f 0 V P-P L
R C = R FB ----------------------------------------0.75 V IN ( ESR )
0.75V IN ( ESR ) C
C C = -----------------------------------------------2πV P-P R FB f 0 L
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ISL6307B
In the solutions to the compensation equations, there is a
single degree of freedom. For the solutions presented in
Equation 35, RFB is selected arbitrarily. The remaining
compensation components are then selected according to
Equation 35.
C2
CC
COMP
FB
C1
R1
IDROOP
RFB
ISL6307B
RC
C ( ESR )
R 1 = R FB ----------------------------------------LC – C ( ESR )
LC – C ( ESR )
C 1 = ----------------------------------------R FB
VDIFF
FIGURE 21. COMPENSATION CIRCUIT FOR ISL6307B BASED
CONVERTER WITHOUT LOAD-LINE
REGULATION
In Equation 34, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent-series resistance of
the bulk output-filter capacitance; and VP-P is the peak-topeak sawtooth signal amplitude as described in Figure 7 and
Electrical Specifications.
The optional capacitor C2, is sometimes needed to bypass
noise away from the PWM comparator (see Figure 20). Keep
a position available for C2, and be prepared to install a highfrequency capacitor of between 22pF and 150pF in case any
leading-edge jitter problem is noted.
Once selected, the compensation values in Equation 34
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to RC. Slowly increase the
value of RC while observing the transient performance on an
oscilloscope until no further improvement is noted. Normally,
CC will not need adjustment. Keep the value of CC from
Equation 34 unless some performance issue is noted.
COMPENSATION WITHOUT LOAD-LINE REGULATION
The non load-line regulated converter is accurately modeled
as a voltage-mode regulator with two poles at the L-C
resonant frequency and a zero at the ESR frequency. A
type III controller, as shown in Figure 21, provides the
necessary compensation.
The first step is to choose the desired bandwidth, f0, of the
compensated system. Choose a frequency high enough to
assure adequate transient performance but not higher than
1/3 of the switching frequency. The type-III compensator has
an extra high-frequency pole, fHF. This pole can be used for
added noise rejection or to assure adequate attenuation at
the error-amplifier high-order pole and zero frequencies. A
good general rule is to choose fHF = 10f0, but it can be
higher if desired. Choosing fHF to be lower than 10f0 can
cause problems with too much phase shift below the system
bandwidth.
29
0.75V IN
C 2 = -------------------------------------------------------------------( 2π ) 2 f 0 f HF LCR FB V P-P
2
V PP  2π f 0 f HF LCR FB
 
R C = ----------------------------------------------------------------------2πf

- 0.75 V
HF LC – 1
IN 

0.75V IN 2πf
 HF LC – 1
C C = --------------------------------------------------------------------( 2π ) 2 f 0 f HF LCR FB V P-P
(EQ. 35)
In Equation 35, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent-series resistance of
the bulk output-filter capacitance; and VP-P is the peak-topeak sawtooth signal amplitude as described in Figure 7 and
Electrical Specifications.
Output Filter Design
The output inductors and the output capacitor bank together
to form a low-pass filter responsible for smoothing the
pulsating voltage at the phase nodes. The output filter also
must provide the transient energy until the regulator can
respond. Because it has a low bandwidth compared to the
switching frequency, the output filter necessarily limits the
system transient response. The output capacitor must
supply or sink load current while the current in the output
inductors increases or decreases to meet the demand.
In high-speed converters, the output capacitor bank is
usually the most costly (and often the largest) part of the
circuit. Output filter design begins with minimizing the cost of
this part of the circuit. The critical load parameters in
choosing the output capacitors are the maximum size of the
load step, ∆I; the load-current slew rate, di/dt; and the
maximum allowable output-voltage deviation under transient
loading, ∆VMAX. Capacitors are characterized according to
their capacitance, ESR, and ESL (equivalent series
inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
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March 9, 2006
ISL6307B
di
∆V ≈ ( ESL ) ----- + ( ESR ) ∆I
dt
(EQ. 36)
The filter capacitor must have sufficiently low ESL and ESR
so that ∆V < ∆VMAX.
Most capacitor solutions rely on a mixture of high-frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
The ESR of the bulk capacitors also creates the majority of
the output-voltage ripple. As the bulk capacitors sink and
source the inductor ac ripple current (see Interleaving and
Equation 2), a voltage develops across the bulk-capacitor
ESR equal to IC,P-P(ESR). Thus, once the output capacitors
are selected, the maximum allowable ripple voltage,
VP-P(MAX), determines the lower limit on the inductance.
V – N V

OUT V OUT
 IN
L ≥ ( ESR ) -----------------------------------------------------------f S V IN V P-P( MAX )
(EQ. 37)
Since the capacitors are supplying a decreasing portion of
the load current while the regulator recovers from the
transient, the capacitor voltage becomes slightly depleted.
The output inductors must be capable of assuming the entire
load current before the output voltage decreases more than
∆VMAX. This places an upper limit on inductance.
Equation 38 gives the upper limit on L for the cases when
the trailing edge of the current transient causes a greater
output-voltage deviation than the leading edge. Equation 39
addresses the leading edge. Normally, the trailing edge
dictates the selection of L because duty cycles are usually
less than 50%. Nevertheless, both inequalities should be
evaluated, and L should be selected based on the lower of
the two results. In each equation, L is the per-channel
inductance, C is the total output capacitance, and N is the
number of active channels.
2NCVO
- ∆V MAX – ∆I ( ESR )
L ≤ -------------------( ∆I ) 2
(EQ. 38)
( 1.25 ) NC
L ≤ -------------------------- ∆V MAX – ∆I ( ESR )  V IN – V O


( ∆I ) 2
(EQ. 39)
30
Input Supply Voltage
The VCC input of SL6307B needs to be connected to +12V
through a 300Ω resistor with one 1µF cap be connected from
VCC to GND.
Switching Frequency
There are a number of variables to consider when choosing
the switching frequency, as there are considerable effects on
the upper-MOSFET loss calculation. These effects are
outlined in MOSFETs, and they establish the upper limit for
the switching frequency. The lower limit is established by the
requirement for fast transient response and small outputvoltage ripple as outlined in Output Filter Design. Choose the
lowest switching frequency that allows the regulator to meet
the transient-response requirements.
Switching frequency is determined by the selection of the
frequency-setting resistor, RT (see the figures labeled
Typical Application on pages 4, 5, 6 and 7). Equation 40 is
provided to assist in selecting the correct value for RT.
10
2.5X10
R T = -------------------------F SW
(EQ. 40)
Input Capacitor Selection
The input capacitors are responsible for sourcing the AC
component of the input current flowing into the upper
MOSFETs. Their RMS current capacity must be sufficient to
handle the AC component of the current drawn by the upper
MOSFETs that is related to duty cycle and the number of
active phases.
0.3
INPUT-CAPACITOR CURRENT (IRMS/IO)
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total outputvoltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates by an amount
0.2
0.1
IL,P-P = 0
IL,P-P = 0.5 IO
IL,P-P = 0.75 IO
0
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (VO/VIN)
FIGURE 22. NORMALIZED INPUT-CAPACITOR RMS CURRENT
vs DUTY CYCLE FOR 2-PHASE CONVERTER
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ISL6307B
IL,P-P = 0
IL,P-P = 0.5 IO
IL,P-P = 0.25 IO
IL,P-P = 0.75 IO
0.3
INPUT-CAPACITOR CURRENT (IRMS/IO)
INPUT-CAPACITOR CURRENT (IRMS/IO)
0.3
0.2
0.1
0
0
0.2
0.4
0.6
0.8
0.1
0
0.2
Figures 23 and 24 provide the same input RMS current
information for three and four phase designs respectively.
Use the same approach to selecting the bulk capacitor type
and number as described above.
Low capacitance, high-frequency ceramic capacitors are
needed in addition to the bulk capacitors to suppress leading
and falling edge voltage spikes. The result from the high
current slew rates produced by the upper MOSFETs turning
on and off. Select low ESL ceramic capacitors and place one
as close as possible to each upper MOSFET drain to
minimize board parasitic impedances and maximize
suppression.
0.6
0.8
1.0
FIGURE 24. NORMALIZED INPUT-CAPACITOR RMS CURRENT
vs DUTY CYCLE FOR 4-PHASE CONVERTER
MULTIPHASE RMS IMPROVEMENT
Figure 25 is provided as a reference to demonstrate the
dramatic reductions in input-capacitor RMS current upon the
implementation of the multiphase topology. For example,
compare the input RMS current requirements of a two-phase
converter versus that of a single phase. Assume both
converters have a duty cycle of 0.25, maximum sustained
output current of 40A, and a ratio of IL,P-P to IO of 0.5. The
single phase converter would require 17.3Arms current
capacity while the two-phase converter would only require
10.9Arms. The advantages become even more pronounced
when output current is increased and additional phases are
added to keep the component cost down relative to the
single phase approach.
0.6
INPUT-CAPACITOR CURRENT (IRMS/IO)
For a two phase design, use Figure 22 to determine the
input-capacitor RMS current requirement given the duty
cycle, maximum sustained output current (IO), and the ratio
of the per-phase peak-to-peak inductor current (IL,P-P) to IO.
Select a bulk capacitor with a ripple current rating which will
minimize the total number of input capacitors required to
support the RMS current calculated. The voltage rating of
the capacitors should also be at least 1.25 times greater
than the maximum input voltage.
0.4
DUTY CYCLE (VO/VIN)
DUTY CYCLE (VO/VIN)
FIGURE 23. NORMALIZED INPUT-CAPACITOR RMS CURRENT
vs DUTY CYCLE FOR 3-PHASE CONVERTER
IL,P-P = 0.5 IO
IL,P-P = 0.75 IO
0.2
0
1.0
IL,P-P = 0
IL,P-P = 0.25 IO
0.4
0.2
IL,P-P = 0
IL,P-P = 0.5 IO
IL,P-P = 0.75 IO
0
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (VO/VIN)
FIGURE 25. NORMALIZED INPUT-CAPACITOR RMS
CURRENT vs DUTY CYCLE FOR SINGLE-PHASE
CONVERTER
31
FN9225.0
March 9, 2006
ISL6307B
Layout Considerations
Plane Allocation and Routing
The following layout strategies are intended to minimize the
impact of board parasitic impedances on converter
performance and to optimize the heat-dissipating capabilities
of the printed-circuit board. These sections highlight some
important practices which should not be overlooked during the
layout process.
Dedicate one solid layer, usually a middle layer, for a ground
plane. Make all critical component ground connections with
vias to this plane. Dedicate one additional layer for power
planes; breaking the plane up into smaller islands of
common voltage. Use the remaining layers for signal wiring.
Component Placement
Within the allotted implementation area, orient the switching
components first. The switching components are the most
critical because they carry large amounts of energy and tend
to generate high levels of noise. Switching component
placement should take into account power dissipation. Align
the output inductors and MOSFETs such that spaces
between the components are minimized while creating the
PHASE plane. Place the Intersil MOSFET driver IC as close
as possible to the MOSFETs they control to reduce the
parasitic impedances due to trace length between critical
driver input and output signals. If possible, duplicate the
same placement of these components for each phase.
Route phase planes of copper filled polygons on the top and
bottom once the switching component placement is set. Size
the trace width between the driver gate pins and the
MOSFET gates to carry 4A of current. When routing
components in the switching path, use short wide traces to
reduce the associated parasitic impedances.
Next, place the input and output capacitors. Position one
high-frequency ceramic input capacitor next to each upper
MOSFET drain. Place the bulk input capacitors as close to
the upper MOSFET drains as dictated by the component
size and dimensions. Long distances between input
capacitors and MOSFET drains result in too much trace
inductance and a reduction in capacitor performance. Locate
the output capacitors between the inductors and the load,
while keeping them in close proximity to the microprocessor
socket.
The ISL6307B can be placed off to one side or centered
relative to the individual phase switching components.
Routing of sense lines and PWM signals will guide final
placement. Critical small signal components to place close
to the controller include the ISEN resistors, RT resistor,
feedback resistor, and compensation components.
Bypass capacitors for the ISL6307B and ISL66XX driver
bias supplies must be placed next to their respective pins.
Trace parasitic impedances will reduce their effectiveness.
32
FN9225.0
March 9, 2006
ISL6307B
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L48.7x7
48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VKKD-2 ISSUE C)
MILLIMETERS
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
0.80
0.90
1.00
-
A1
-
-
0.05
-
A2
-
-
1.00
A3
b
0.18
D
0.23
9
0.30
5, 8
7.00 BSC
D1
D2
9
0.20 REF
-
6.75 BSC
4.15
4.30
9
4.45
7, 8
E
7.00 BSC
-
E1
6.75 BSC
9
E2
4.15
e
4.30
4.45
7, 8
0.50 BSC
-
k
0.25
-
-
-
L
0.30
0.40
0.50
8
L1
-
-
0.15
10
N
48
2
Nd
12
3
Ne
12
3
P
-
-
0.60
9
θ
-
-
12
9
Rev. 1 10/02
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
33
FN9225.0
March 9, 2006
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