DATASHEET

PRODUCT
OBSOLETE
T PART
EPLACEMEN
R
D
E
D
N
E
M
R E C OM
6334A
ISL6334, ISL
Data Sheet
VR11.1, 4-Phase PWM Controller with
Light Load Efficiency Enhancement and
Load Current Monitoring Features
The ISL6334B, ISL6334C control microprocessor core
voltage regulation by driving up to 4 interleaved
synchronous-rectified buck channels in parallel. This
multiphase architecture results in multiplying channel ripple
frequency and reducing input and output ripple currents.
Lower ripple results in fewer components, lower cost, reduced
power dissipation, and smaller implementation area.
Microprocessor loads can generate load transients with
extremely fast edge rates and require high efficiency at light
load. The ISL6334B, ISL6334C utilizes Intersil’s proprietary
Active Pulse Positioning (APP), Adaptive Phase Alignment
(APA) modulation scheme, active phase adding and
dropping to achieve and maintain the extremely fast
transient response with fewer output capacitors and high
efficiency from light to full load.
The ISL6334B, ISL6334C is designed to be compliant to
Intel VR11.1 specifications. It accurately reports the load
current via IMON pin to the microprocessor, which sends an
active low PSI# signal to the controller at low power mode.
The controller then enters 1- or 2-phase operation with diode
emulation option to reduce magnetic core and switching
losses, yielding high efficiency at light load. After the PSI#
signal is de-asserted, the dropped phase(s) are added back
to sustain heavy load transient response and efficiency.
Today’s microprocessors require a tightly regulated output
voltage position versus load current (droop). The ISL6334B,
ISL6334C senses the output current continuously by utilizing
patented techniques to measure the voltage across the
dedicated current sense resistor or the DCR of the output
inductor. The sensed current flows out of FB pin to develop the
precision voltage drop across the feedback resistor for droop
control. Current sensing circuits also provide the needed
signals for channel-current balancing, average overcurrent
protection and individual phase current limiting. A NTC
thermistor’s temperature is sensed via TM pin and internally
digitized for thermal monitoring and for integrated thermal
compensation of the current sense elements.
ISL6334B, ISL6334C
May 5, 2016
FN6689.3
Features
• Intel VR11.1 Compliant
• H_CPURST_N Input to Eliminate Required Extensive
External Circuitry for Proper PSI# Operation of Intel’s
Eaglelake Chipset Platforms
• Proprietary Active Pulse Positioning (APP) and Adaptive
Phase Alignment (APA) Modulation Scheme
• Proprietary Active Phase Adding and Dropping with Diode
Emulation Scheme For Enhanced Light Load Efficiency
• Precision Multiphase Core Voltage Regulation
- Differential Remote Voltage Sensing
- ±0.5% Closed-loop System Accuracy Over Load, Line
and Temperature
- Bi-directional, Adjustable Reference-Voltage Offset
• Precision Resistor or DCR Differential Current Sensing
- Accurate Load-Line (Droop) Programming
- Accurate Channel-Current Balancing
- Accurate Load Current Monitoring via IMON Pin
• Microprocessor Voltage Identification Input
- Dynamic VID™ Technology for VR11.1 Requirement
- 8-Bit VID, VR11 Compatible
• Average Overcurrent Protection and Channel Current Limit
• Precision Overcurrent Protection on IMON Pin
• Thermal Monitoring and Overvoltage Protection
• Integrated Programmable Temperature Compensation
• Integrated Open Sense Line Protection
• 1 to 4-Phase Operation, Coupled Inductor Compatibility
• Adjustable Switching Frequency up to 1MHz Per Phase
• Package Option
- QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad
Flat No Leads - Product Outline
• Pb-Free (RoHS Compliant)
A unity gain, differential amplifier is provided for remote voltage
sensing and completely eliminates any potential difference
between remote and local grounds. This improves regulation
and protection accuracy. The threshold-sensitive enable input is
available to accurately coordinate the start-up of the ISL6334B,
ISL6334C with any other voltage rail. Dynamic-VID™
technology allows seamless on-the-fly VID changes. The
offset pin allows accurate voltage offset settings that are
independent of VID setting.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2008-2010, 2016. All Rights Reserved
Intersil (and design) and Dynamic VID are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL6334B, ISL6334C
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
ISL6334BIRZ
TEMP.
(°C)
PACKAGE
(Pb-Free)
40 Ld 6x6 QFN
PKG.
DWG. #
6334B IRZ
-40 to +85
L40.6x6
ISL6334CIRZ
6334C IRZ
-40 to +85
40 Ld 6x6 QFN
L40.6x6
ISL6334BCRZ
6334B CRZ
0 to +70
40 Ld 6x6 QFN
L40.6x6
ISL6334CCRZ
6334C CRZ
0 to +70
40 Ld 6x6 QFN
L40.6x6
NOTES:
1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6334B, ISL6334C. For more information on MSL please see
techbrief TB363.
Pinout
2
VID7
TM
VR_HOT
H_CPURST_N
VR_RDY
SS
FS
EN_VTT
EN_PWR
PWM3
ISL6334B, ISL6334C
(40 LD QFN)
TOP VIEW
40
39
38
37
36
35
34
33
32
31
VID6
1
30 ISEN3-
VID5
2
29 ISEN3+
VID4
3
28 ISEN1+
VID3
4
27 ISEN1-
VID2
5
26 PWM1
GND
9
22 ISEN2+
IMON 10
21 ISEN211
12
13
14
15
16
17
18
19
20
PWM2
OFS
VCC
23 ISEN4+
TCOMP
8
VSEN
PSI#
RGND
24 ISEN4-
VDIFF
7
FB
VID0
COMP
25 PWM4
REF
6
DAC
VID1
FN6689.3
May 5, 2016
ISL6334B, ISL6334C
Controller and Driver Recommendation
CONTROLLER
COMMENTS
ISL6334B
When PSI# is asserted low, the operating channels send a special PWM protocol that can be recognized only by the dedicated
VR11.1 drivers ISL6622/ISL6620 for Diode Emulation (DCM) operation. The disabled channels remain in tri-state.
ISL6334C
When PSI# is asserted low, the operating channels send normal CCM PWM that can be recognized by any Intersil driver,
such as ISL6612/ISL6614, ISL6596, ISL6609, ISL6610, and even ISL6622/ISL6620. The disabled channels remain in
tri-state.
GATE
DRIVE
VOLTAGE
# OF
GATE
DRIVES
DIODE
EMULATION
(DE)
GATE DRIVE
DROP
(GVOT)
ISL6622
12V
Dual
Yes
Yes
For PSI# channel and its coupled channel in coupled
inductor applications or all channels
ISL6622A
12V
Dual
Yes
No
For PSI# channel and its coupled channel in coupled
inductor applications or all channels.
ISL6620, ISL6620A
5V
Dual
Yes
No
For PSI# channel and its coupled channel in coupled
inductor applications or all channels
ISL6612, ISL6612A
12V
Dual
No
No
For dropped phases or all channels with ISL6334C
ISL6596, ISL6609
5V
Dual
No
No
For dropped phases or all channels with ISL6334C
ISL6614, ISL6614A
12V
Quad
No
No
For dropped phases or all channels with ISL6334C
ISL6610
5V
Quad
No
No
For dropped phases or all channels with ISL6334C
DRIVER
COMMENTS
NOTE: Intersil 5V and 12V drivers are mostly pin-to-pin compatible and allow for dual footprint layout implementation to optimize MOSFET selection
and efficiency. Dual = One Synchronous Channel; Quad = Two Synchronous Channels.
3
FN6689.3
May 5, 2016
ISL6334B, ISL6334C
ISL6334B and ISL6334C Block Diagram
VDIFF VR_RDY
RGND
-
VSEN
+
FS
PSI#
0.870
CLOCK AND
RAMP GENERATOR
X1
-
POW ER-ON
RESET (POR)
+
EN_VTT
N
OVP
0.870
+
SOFT-START
AND
FAULT LOGIC
+
-
0.870
+175mV
APP and APA
MODULATOR
EN_PWR
PWM1
SS
APP and APA
MODULATOR
VID7
PWM2
VID6
VID5
DYNAMIC
VID
D/A
VID4
VID3
APP and APA
MODULATOR
VID2
PWM3
VID1
VID0
DAC
OFS
APP and APA
MODULATOR
PWM4
OFFSET
REF
+
FB
-
CHANNEL
CURRENT
BALANCE
AND PEAK
CURRENT LIMIT
E/A
COMP
1.11V
+
-
+
OCP
OCP
CHANNEL
DETECT
N
ISEN1+
I_TRIP
ISEN1-
-
ISEN2+
1
N
IMON
TEMPERATURE
COMPENSATION
ISEN2ISEN3+
ISEN3-
1.11V
VR_HOT
CHANNEL
CURRENT
SENSE
ISEN4+
ISEN4THERMAL
MONITOR
TEMPERATURE
COMPENSATION
GAIN ADJUST
H_CPURST_N
TCOMP
TM
4
GND
FN6689.3
May 5, 2016
ISL6334B, ISL6334C
Typical Application: 4-Phase VR with Thermal Compensation, 1-Phase PSI#, DE, and GVOT
+12V
BOOT
PVCC
+5V
VCC
VIN
UGATE
PHASE
ISL6622
DRIVER
DAC
COMP VCC
FB
LGATE
GND
PWM
REF
VDIFF
VSEN
PWM1
RGND
VTT
ISEN1-
EN_VTT
+12V
BOOT
PVCC
VIN
ISEN1+
VR_RDY
VCC
VID7
PHASE
ISL6334B
ISL6334
VID6
UGATE
ISL6612
DRIVER
VID5
VID4
PWM2
VID3
VID2
LGATE
GND
PWM
ISEN2-
VID1
ISEN2+
VID0
+12V
PSI#
H_CPURST_N
PWM3
VR_HOT
ISEN3ISEN3+
VIN
BOOT
PVCC
VIN
µP
LOAD
VCC
UGATE
PHASE
ISL6612
DRIVER
EN_PWR
+5V
GND
LGATE
GND
PWM
PWM4
IMON
ISEN4ISEN4+
TCOMP
TM
+5V
OFS
FS
+5V
SS
+12V
BOOT
PVCC
VCC
VIN
UGATE
PHASE
ISL6612
DRIVER
NTC
NTC: NTHS0805N02N6801,
6.8k, VISHAY
5
PWM
LGATE
GND
FN6689.3
May 5, 2016
ISL6334B, ISL6334C
Typical Application - 4-Phase VR with 1-Phase PSI#; without DE and GVOT
+12V
BOOT
PVCC
+5V
VCC
VIN
UGATE
PHASE
ISL6612
DRIVER
COMP VCC
FB
DAC
LGATE
GND
PWM
REF
VDIFF
VSEN
PWM1
RGND
VTT
ISEN1-
EN_VTT
+12V
BOOT
PVCC
VIN
ISEN1+
VR_RDY
VCC
VID7
PHASE
ISL6334C
ISL6334
VID6
UGATE
ISL6612
DRIVER
VID5
VID4
PWM2
VID3
VID2
LGATE
GND
PWM
ISEN2-
VID1
ISEN2+
VID0
+12V
PSI#
H_CPURST_N
PWM3
VR_HOT
ISEN3ISEN3+
VIN
BOOT
PVCC
VIN
µP
LOAD
VCC
UGATE
PHASE
ISL6612
DRIVER
EN_PWR
+5V
GND
LGATE
GND
PWM
PWM4
IMON
ISEN4ISEN4+
TCOMP
TM
+5V
OFS
FS
+5V
SS
+12V
BOOT
PVCC
VCC
VIN
UGATE
PHASE
ISL6612
DRIVER
NTC
NTC: NTHS0805N02N6801,
6.8k, VISHAY
6
PWM
LGATE
GND
FN6689.3
May 5, 2016
ISL6334B, ISL6334C
Typical Application - CI VR with External Thermal Compensation, 2-Phase PSI# (no DE and GVOT)
NTC
+12V
+5V
C
o
VIN
BOOT1
VCC
UGATE1
PHASE1
FB
COMP VCC
DAC
REF
GND
LGATE1
VDIFF
VSEN
RGND
VTT
ISL6614
DRIVER
ISEN1+
EN_VTT
PVCC
12V
BOOT2
VIN
ISEN1-
VR_RDY
PWM1
VID7
PWM1
UGATE2
PHASE2
VID6
ISL6334
ISL6334C
VID5
LGATE2
VID4
VID3
PWM3
VID2
PGND
PWM2
ISEN3-
VID1
ISEN3+
VID0
PSI#
ISEN2+
VR_FAN
ISEN2-
H_CPURST_N
PWM2
VIN
+12V
VIN
BOOT1
VCC
µP
LOAD
UGATE1
EN_PWR
PHASE1
+5V
PWM4
GND
GND
ISEN4-
LGATE1
ISEN4+
IMON
ISL6614
DRIVER
TCOMP
TM
OFS
FS
SS
+5V
PWM1
PVCC
BOOT2
12V
VIN
UGATE2
PHASE2
NTC
5V
5V
LGATE2
NTC: NTHS0805N02N6801,
6.8k, VISHAY
7
PWM2
PGND
FN6689.3
May 5, 2016
ISL6334B, ISL6334C
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+6V
All Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to VCC + 0.3V
Thermal Resistance (Notes 4, 5)
Recommended Operating Conditions
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Ambient Temperature
ISL6334BCRZ, ISL6334CCRZ. . . . . . . . . . . . . . . . . 0°C to +70°C
ISL6334BIRZ, ISL6334CIRZ . . . . . . . . . . . . . . . . .-40°C to +85°C
JA (°C/W)
JC (°C/W)
40 Ld 6x6 QFN Package . . . . . . . . . . .
32
2
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Recommended Operating Conditions; VCC = 5V, Unless Otherwise Specified. Boldface limits apply over the
operating temperature ranges, -40°C to +85°C or 0°C to +70°C.
PARAMETER
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
VCC SUPPLY CURRENT
Nominal Supply
VCC = 5VDC; EN_PWR = 5VDC; RT = 100k
ISEN1 = ISEN2 = ISEN3 = ISEN4 = 80µA
-
16
20
mA
Shutdown Supply
VCC = 5VDC; EN_PWR = 0VDC; RT = 100k
-
14
17
mA
VCC Rising POR Threshold
4.3
4.4
4.5
V
VCC Falling POR Threshold
3.75
3.88
4.0
V
EN_PWR Rising Threshold
0.830
0.850
0.870
V
EN_PWR Falling Threshold
0.735
0.752
0.770
V
EN_VTT Rising Threshold
0.830
0.850
0.870
V
EN_VTT Falling Threshold
0.735
0.752
0.770
V
POWER-ON RESET AND ENABLE
REFERENCE VOLTAGE AND DAC
System Accuracy of ISL6334BCRZ, ISL6334CCRZ
(VID = 1V to 1.6V, TJ = 0°C to +70°C)
(Note 7, Closed-Loop)
-0.5
-
0.5
%VID
System Accuracy of ISL6334BCRZ, ISL6334CCRZ
(VID = 0.5V to 1V, TJ = 0°C to +70°C)
(Note 7, Closed-Loop)
-5
-
5
mV
System Accuracy of ISL6334BIRZ, ISL6334CIRZ
(VID = 1V to 1.6V, TJ = -40°C to +85°C)
(Notes 7, 8; Closed-Loop)
-0.6
-
0.6
%VID
System Accuracy of ISL6334BIRZ, ISL6334CIRZ
(VID = 0.8V to 1V, TJ = -40°C to +85°C)
(Notes 7, 8; Closed-Loop)
-6
-
6
mV
System Accuracy of ISL6334BIRZ, ISL6334CIRZ
(VID = 0.5V to 0.8V, TJ = -40°C to +85°C)
(Notes 7, 8; Closed-Loop)
-7
-
7
mV
VID Pull-up
After tD3
30
40
50
µA
VID Input Low Level
-
-
0.4
V
VID Input High Level
0.8
-
-
V
Max DAC Source Current
3.5
-
-
mA
Max DAC Sink Current
100
-
-
µA
50
-
-
µA
Max REF Source/Sink Current
(Note 8)
8
FN6689.3
May 5, 2016
ISL6334B, ISL6334C
Electrical Specifications
Recommended Operating Conditions; VCC = 5V, Unless Otherwise Specified. Boldface limits apply over the
operating temperature ranges, -40°C to +85°C or 0°C to +70°C. (Continued)
PARAMETER
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
390
400
415
mV
1.574
1.60
1.635
V
PIN-ADJUSTABLE OFFSET
Voltage at OFS Pin
Offset resistor connected to ground
Voltage below VCC, offset resistor connected to
VCC
OSCILLATORS
Accuracy of Switching Frequency Setting
RT = 100k
225
250
275
kHz
Adjustment Range of Switching Frequency
(Note 8)
0.08
-
1.0
MHz
Soft-start Ramp Rate
RSS = 100k(Notes 9, 10)
-
1.563
-
mV/µs
Adjustment Range of Soft-Start Ramp Rate
(Note 8)
0.625
-
6.25
mV/µs
-
1.5
-
V
-
96
-
dB
Open-Loop Bandwidth
-
80
-
MHz
Slew Rate
-
25
-
V/µs
Maximum Output Voltage
3.8
4.4
4.9
V
Output High Voltage @ 2mA
3.6
-
-
V
Output Low Voltage @ 2mA
-
-
1.6
V
-
20
-
MHz
PWM GENERATOR
Sawtooth Amplitude
ERROR AMPLIFIER
Open-Loop Gain
RL = 10k to ground
REMOTE-SENSE AMPLIFIER
Bandwidth
Output High Current
VSEN - RGND = 2.5V (Note 8)
-500
-
500
µA
Output High Current
VSEN - RGND = 0.6 (Note 8)
-500
-
500
µA
Sink Impedance
PWM = Low with 1mA Load
100
220
300

Source Impedance
PWM = High, Forced to 3.7V
200
320
400

High Signal Threshold
-
-
0.8
V
Low Signal Threshold
0.4
-
-
V
38
-
60
ms
-
-
0.8
V
0.4
-
-
V
ISEN1 = ISEN2 = ISEN3 = ISEN4 = 40µA;
CS Offset and Mirror Error Included, RISENx = 200
36.5
-
42
µA
ISEN1 = ISEN2 = ISEN3 = ISEN4 = 80µA;
CS Offset and Mirror Error Included, RISENx = 200
74
-
83
µA
Overcurrent Trip Level for Average Current at Normal
CCM PWM Mode
CS Offset and Mirror Error Included, RISENx = 200
96
105
117
µA
Overcurrent Trip Level for Average Current at PSI#
Mode
N = 4, Drop to 1-Phase
-
121
-
µA
PWM OUTPUT
PSI# INPUT
H_CPURST_N INPUT
PSI# Time Out
With Respect to H_CPURST_N Rising Edge
High Signal Threshold
Low Signal Threshold (PSI# Signal Lockout)
CURRENT SENSE AND OVERCURRENT PROTECTION
Sensed Current Tolerance
9
FN6689.3
May 5, 2016
ISL6334B, ISL6334C
Electrical Specifications
Recommended Operating Conditions; VCC = 5V, Unless Otherwise Specified. Boldface limits apply over the
operating temperature ranges, -40°C to +85°C or 0°C to +70°C. (Continued)
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
115
129
146
µA
1.085
1.11
1.14
V
TM Input Voltage for VR_HOT Trip
32.9
33.3
33.7
%VCC
TM Input Voltage for VR_HOT Reset
38.7
39.1
39.6
%VCC
PARAMETER
TEST CONDITIONS
Peak Current Limit for Individual Channel
IMON Clamped and OCP Trip Level
THERMAL MONITORING AND FAN CONTROL
Leakage Current of VR_HOT
With external pull-up resistor connected to VCC
-
-
5
µA
VR_HOT Low Voltage
With 1.24k resistor pull-up to VCC, IVR_HOT = 4mA
-
-
0.3
V
Leakage Current of VR_RDY
With pull-up resistor externally connected to VCC
-
-
5
µA
VR_RDY Low Voltage
IVR_RDY = 4mA
-
-
0.3
V
Undervoltage Threshold
VDIFF Falling
48
50
52
%VID
VR_RDY Reset Voltage
VDIFF Rising
57
59.6
62
%VID
Overvoltage Protection Threshold
Before valid VID
1.250
1.273
1.300
V
158
175
190
mV
-
100
-
mV
VR READY AND PROTECTION MONITORS
After valid VID, the voltage above VID
Overvoltage Protection Reset Hysteresis
NOTES:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
7. These parts are designed and adjusted for accuracy with all errors in the voltage loop included.
8. Limits established by characterization and are not production tested.
9. During soft-start, VDAC rises from 0V to 1.1V first and then ramp to VID voltage after receiving valid VID.
10. Soft-start ramp rate is determined by the adjustable soft-start oscillator frequency at the speed of 6.25mV per cycle.
10
FN6689.3
May 5, 2016
ISL6334B, ISL6334C
Functional Pin Description
VCC - Supplies the power necessary to operate the chip.
The controller starts to operate when the voltage on this pin
exceeds the rising POR threshold and shuts down when the
voltage on this pin drops below the falling POR threshold.
Connect this pin directly to a +5V supply.
GND - Bias and reference ground for the IC. The bottom
metal base of ISL6334B, ISL6334C is the GND.
EN_PWR - This pin is a threshold-sensitive enable input for
the controller. Connecting the 12V supply to EN_PWR
through an appropriate resistor divider provides a means to
synchronize power-up of the controller and the MOSFET
driver ICs. When EN_PWR is driven above 0.870V, the
ISL6334B, ISL6334C is active depending on status of the
EN_VTT, the internal POR, and pending fault states. Driving
EN_PWR below 0.735V will clear all fault states and prime
the ISL6334B, ISL6334C to soft-start when re-enabled.
EN_VTT - This pin is another threshold-sensitive enable
input for the controller. It’s typically connected to VTT output
of VTT voltage regulator in the computer mother board.
When EN_VTT is driven above 0.870V, the ISL6334B,
ISL6334C is active depending on status of the EN_PWR, the
internal POR, and pending fault states. Driving EN_VTT
below 0.735V will clear all fault states and prime the
ISL6334B, ISL6334C to soft-start when re-enabled.
VDIFF, VSEN and RGND - VSEN and RGND form the
precision differential remote-sense amplifier. This amplifier
converts the differential voltage of the remote output to a
single-ended voltage referenced to local ground. VDIFF is
the amplifier’s output and the input to the regulation and
protection circuitry. Connect VSEN and RGND to the sense
pins of the remote load.
FB and COMP - Inverting input and output of the error
amplifier respectively. FB can be connected to VDIFF
through a resistor. A properly chosen resistor between
VDIFF and FB can set the load line (droop), because the
sensed current will flow out of FB pin. The droop scale factor
is set by the ratio of the ISEN resistors and the inductor DCR
or the dedicated current sense resistor. COMP is tied back to
FB through an external R-C network to compensate the
regulator.
DAC and REF - The DAC pin is the output of the precision
internal DAC reference. The REF pin is the positive input of
the Error Amplifier. In typical applications, a 1k, 1% resistor
is used between DAC and REF to generate a precision
offset voltage. This voltage is proportional to the offset
current determined by the offset resistor from OFS to ground
or VCC. A capacitor is used between REF and ground to
smooth the voltage transition during Dynamic VID™
operations.
VR_RDY - VR_RDY indicates that soft-start has completed
and the output voltage is within the regulated range around
11
VID setting. It is an open-drain logic output. When OCP or
OVP occurs, VR_RDY will be pulled to low. It will also be
pulled low if the output voltage is below the undervoltage
threshold.
OFS - The OFS pin can be used to program a DC offset
current, which will generate a DC offset voltage between the
REF and DAC pins. The offset current is generated via an
external resistor and precision internal voltage references.
The polarity of the offset is selected by connecting the
resistor to GND or VCC. For no offset, the OFS pin should
be left unterminated.
TCOMP - Temperature compensation scaling input. The
voltage sensed on the TM pin is utilized as the temperature
input to adjust IDROOP and the overcurrent protection limit to
effectively compensate for the temperature coefficient of the
current sense element. To implement the integrated
temperature compensation, a resistor divider circuit is needed
with one resistor being connected from TCOMP to VCC of the
controller and another resistor being connected from TCOMP
to GND. Changing the ratio of the resistor values will set the
gain of the integrated thermal compensation. When integrated
temperature compensation function is not used, connect
TCOMP to GND.
TM - TM is an input pin for the VR temperature measurement.
Connect this pin through an NTC thermistor to GND and a
resistor to VCC of the controller. The voltage at this pin is
reverse proportional to the VR temperature. The ISL6334B,
ISL6334C monitors the VR temperature based on the voltage
at the TM pin and outputs VR_HOT and VR_FAN signals.
VR_HOT - VR_HOT is used as an indication of high VR
temperature. It is an open-drain logic output. It will be pulled
low if the measured VR temperature is less than a certain
level, and open when the measured VR temperature
reaches a certain level. A external pull-up resistor is needed.
H_CPURST_N - This pin determines whether the PSI# input
is recognized and the IC enters the low-power, phase
shedding state. While in a logic low state and for 45ms
(typically) after returning high, it prevents the chip from
entering lower power mode operation by locking out the
PSI# input. Left open at start-up, this pin is pulled to about
1.2V by an internal current source, and it enables the 45ms
PSI# lockout. To disable this functionality at all times,
connect this pin to VCC. See “PWM and PSI# Operation” on
page 13 for details.
PWM1-4 - Pulse width modulation outputs. Connect these
pins to the PWM input pins of the Intersil driver IC. The
number of active channels is determined by the state of
PWM2, PWM3 and PWM4. Tie PWM2 to VCC to configure
for 1-phase operation. Tie PWM3 to VCC to configure for 2phase operation. Tie PWM4 to VCC to configure for 3-phase
operation. In addition, tie PSI# to GND to configure for single
phase operation with diode emulation.
FN6689.3
May 5, 2016
ISL6334B, ISL6334C
ISEN1-4+, ISEN1-4- - The ISEN+ and ISEN- pins are
current sense inputs to individual differential amplifiers. The
sensed current is used for channel current balancing,
overcurrent protection, and droop regulation. Inactive
channels should have their respective current sense inputs
left open (for example, open ISEN4+ and ISEN4- for
3-phase operation).
For DCR sensing, connect each ISEN- pin to the node
between the RC sense elements. Tie the ISEN+ pin to the
other end of the sense capacitor through a resistor, RISEN.
The voltage across the sense capacitor is proportional to the
inductor current. Therefore, the sense current is proportional
to the inductor current and scaled by the DCR of the inductor
and RISEN.
To match the time delay of the internal circuit, a capacitor is
needed between each ISEN+ pin and GND, as described in
“Current Sensing” on page 14.
IMON - IMON is the output pin of sensed, thermally
compensated (if internal thermal compensation is used)
average current. The voltage at IMON pin is proportional to
the load current and the resistor value, and internally clamped
to 1.11V plus the remote ground potential difference. If the
clamped voltage (1.11V) is triggered, it will initiate the
overcurrent shutdown. By choosing the proper value for the
resistor at IMON pin, the overcurrent trip level can be set to be
lower than the fixed internal overcurrent threshold. During the
dynamic VID, the OCP function of this pin is disable to avoid
falsely triggering. Tie it to GND if not used.
FS - Use this pin to set up the desired switching frequency. A
resistor, placed from FS to ground/VCC will set the switching
frequency. The relationship between the value of the resistor
and the switching frequency will be approximated by
Equation 3. This pin is also used with SS and PSI# pins for
phase dropping decoding. See Table 1.
SS - Use this pin to set up the desired start-up oscillator
frequency. A resistor placed from SS to ground/VCC will set
up the soft-start ramp rate. The relationship between the
value of the resistor and the soft-start ramp up time will be
approximated by Equations 15 and 16. This pin is also used
with FS and PSI# pins for phase dropping decoding. See
Table 1.
VID0-7 - These are the inputs to the internal DAC that
generates the reference voltage for output regulation. All VID
pins have no internal pull-up current sources until after TD3.
Connect these pins either to open-drain outputs with
external pull-up resistors or to active-pull-up outputs, as high
as VCC plus 0.3V.
PSI# - A low input signal indicates the low power mode
operation of the processor. The controller drops the number
of active phases to single or 2-phase operation, according to
the logic on Table 1 on page 14. The PSI# pin, SS, and FS
pins are used to program the controller in operation of
12
non-coupled, 2-phase coupled, or (n-x)-Phase coupled
inductors when PSI# is asserted (active low). Different cases
yield different PWM output behavior on both dropped
phase(s) and remained phase(s) as PSI# is asserted and
de-asserted. A high input signal pulls the controller back to
normal operation.
Operation
Multiphase Power Conversion
Microprocessor load current profiles have changed to the
point that the advantages of multiphase power conversion
are impossible to ignore. The technical challenges
associated with producing a single-phase converter (which
are both cost-effective and thermally viable), have forced a
change to the cost-saving approach of multiphase. The
ISL6334B, ISL6334C controller helps reduce the complexity
of implementation by integrating vital functions and requiring
minimal output components. The block diagrams on pages
5, 6 and 7 provide top level views of multiphase power
conversion using the ISL6334B, ISL6334C controller.
Interleaving
The switching of each channel in a multiphase converter is
timed to be symmetrically out-of-phase with each of the
other channels. In a 3-phase converter, each channel
switches 1/3 cycle after the previous channel and 1/3 cycle
before the following channel. As a result, the 3-phase
converter has a combined ripple frequency 3x greater than
the ripple frequency of any one phase. In addition, the
peak-to-peak amplitude of the combined inductor currents is
reduced in proportion to the number of phases (Equations 1
and 2). Increased ripple frequency and lower ripple
amplitude mean that the designer can use less per-channel
inductance and lower total output capacitance for any
performance specification.
IL1 + IL2 + IL3, 7A/DIV
IL1, 7A/DIV
PWM1, 5V/DIV
IL2, 7A/DIV
PWM2, 5V/DIV
IL3, 7A/DIV
PWM3, 5V/DIV
1µs/DIV
FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS
FOR 3-PHASE CONVERTER
Figure 1 illustrates the multiplicative effect on output ripple
frequency. The three channel currents (IL1, IL2, and IL3)
combine to form the AC ripple current and the DC load
current. The ripple component has 3x the ripple frequency of
FN6689.3
May 5, 2016
ISL6334B, ISL6334C
each individual channel current. Each PWM pulse is
terminated 1/3 of a cycle after the PWM pulse of the previous
phase. The DC components of the inductor currents combine
to feed the load.
To understand the reduction of ripple current amplitude in the
multiphase circuit, examine Equation 1, which represents an
individual channel’s peak-to-peak inductor current.
 V IN – V OUT   V OUT
I PP = --------------------------------------------------------L  F SW  V
(EQ. 1)
IN
In Equation 1, VIN and VOUT are the input and output
voltages respectively, L is the single-channel inductor value,
and FSW is the switching frequency.
INPUT-CAPACITOR CURRENT, 10A/DIV
CHANNEL 2
INPUT CURRENT
10A/DIV
CHANNEL 3
INPUT CURRENT
10A/DIV
1µs/DIV
FIGURE 2. CHANNEL INPUT CURRENTS AND INPUTCAPACITOR RMS CURRENT FOR 3-PHASE
CONVERTER
The output capacitors conduct the ripple component of the
inductor current. In the case of multiphase converters, the
capacitor current is the sum of the ripple currents from each
of the individual channels. Compare Equation 1 to the
expression for the peak-to-peak current after the summation
of N symmetrically phase-shifted inductor currents in
Equation 2. Peak-to-peak ripple current decreases by an
amount proportional to the number of channels. Output
voltage ripple is a function of capacitance, capacitor
equivalent series resistance (ESR), and inductor ripple
current. Reducing the inductor ripple current allows the
designer to use fewer or less costly output capacitors.
(EQ. 2)
IN
Another benefit of interleaving is to reduce input ripple
current. Input capacitance is determined in part by the
maximum input ripple current. Multiphase topologies can
improve overall system cost and size by lowering input ripple
current and allowing the designer to reduce the cost of input
capacitance. The example in Figure 2 illustrates input
currents from a three-phase converter combining to reduce
the total input ripple current.
13
Figures 18, 19 and 20 can be used to determine the input
capacitor RMS current based on load current, duty cycle,
and the number of channels. They are provided as aids in
determining the optimal input capacitor solution. Figure 21
shows the single phase input-capacitor RMS current for
comparison.
PWM Modulation Scheme
CHANNEL 1
INPUT CURRENT
10A/DIV
 V IN – N  V OUT   V OUT
I C, PP = ------------------------------------------------------------------L  fS  V
The converter depicted in Figure 2 delivers 36A to a 1.5V load
from a 12V input. The RMS input capacitor current is 5.9A.
Compare this to a single-phase converter also stepping down
12V to 1.5V at 36A. The single-phase converter has 11.9ARMS
input capacitor current. The single-phase converter must use
an input capacitor bank with twice the RMS current capacity as
the equivalent three-phase converter.
The ISL6334B, ISL6334C adopts Intersil's proprietary Active
Pulse Positioning (APP) modulation scheme to improve
transient performance. APP control is a unique dual-edge
PWM modulation scheme with both PWM leading and
trailing edges being independently moved to give the best
response to transient loads. The PWM frequency, however,
is constant and set by the external resistor between the FS
pin and GND. To further improve the transient response, the
ISL6334B, ISL6334C also implements Intersil's proprietary
Adaptive Phase Alignment (APA) technique. APA, with
sufficiently large load step currents, can turn on all phases
together. With both APP and APA control, ISL6334B,
ISL6334C can achieve excellent transient performance and
reduce demand on the output capacitors.
Under steady state conditions, the operation of the
ISL6334B, ISL6334C PWM modulators appear to be that of
a conventional trailing edge modulator. Conventional
analysis and design methods can therefore be used for
steady state and small signal operation.
PWM and PSI# Operation
The timing of each channel is set by the number of active
channels. The default channel setting for the ISL6334B,
ISL6334C is four. The switching cycle is defined as the time
between PWM pulse termination signals of each channel.
The cycle time of the pulse signal is the inverse of the
switching frequency set by the resistor between the FS pin
and ground. The PWM signals command the MOSFET
driver to turn on/off the channel MOSFETs.
For 4-channel operation, the channel firing order is 1-2-3-4:
PWM3 pulse happens 1/4 of a cycle after PWM4, PWM2
output follows another 1/4 of a cycle after PWM3, and
PWM1 delays another 1/4 of a cycle after PWM2. For
3-channel operation, the channel firing order is 1-2-3.
Connecting PWM4 to VCC selects three channel operation
and the pulse times are spaced in 1/3 cycle increments. If
PWM3 is connected to VCC, two channel operation is
selected and the PWM2 pulse happens 1/2 of a cycle after
PWM1 pulse. If PWM2 is connected to VCC, only Channel 1
FN6689.3
May 5, 2016
ISL6334B, ISL6334C
operation is selected. In addition, tie PSI# to GND to
configure for single or 2-phase operation with diode
emulation on remaining channel(s), Channel 1 or Channels
1 and 3.
When PSI# is asserted low, it indicates the low power mode
operation of the processor. While in PSI# state, the controller
reduces the number of active phases according to the logic in
Table 1, improving light load efficiency. SS and FS pins are
used to program the controller in operation of non-coupled,
2-phase coupled, or (n-x)-Phase coupled inductors. Different
cases yield different PWM output behaviors on both dropped
phase(s) and remained phase(s) as PSI# is asserted and
de-asserted. A high PSI# input signal pulls the controller back
to normal CCM PWM operation to sustain an immediate heavy
transient load and high efficiency. Note that “n-x” means n-x
phases coupled and x phase(s) are uncoupled.
TABLE 1. PSI# OPERATION DECODING
Switching Frequency
Switching frequency is determined by the selection of the
frequency-setting resistor, RT, which is connected from FS
pin to GND or VCC. Equation 3 and Figure 3 are provided to
assist in selecting the correct resistor value.
10
FS
SS
Non CI or (n-1) CI Drops to 1-phase
0
0
0
Non CI or (n-2) CI Drops to 2-phase
0
0
1
2-phase CI Drops to 1-phase
0
1
0
2-phase CI Drops to 2-phase
0
1
1
Normal CCM PWM Mode
1
x
x
Prior to VR_RDY going high (end of soft-start), the low power
mode operation (PSI# low) is disabled. In addition, a low on
H_CPURST_N disables PSI# mode, and low power mode is
not enabled until approximately 45ms (see “Electrical
Specifications” table on page 9 for expected timing range) after
H_CPURST_N returns to a logic high state. The low and high
thresholds on H_CPURST_N are approximately 0.4V and 0.8V,
as specified in the “Electrical Specifications” table on page 9. A
logic low can be obtained by pulling this pin to ground with a
suitable small signal device, while a logic high can be obtained
by leaving the pin open or connecting to processor VTT (~1.1V)
via a suitable pull-up. If the PSI# lockout is not desired at any
time during the operation of the IC, then H_CPURST_N should
be connected to VCC. This unique function of ISL6334B,
ISL6334C eliminates the required external circuitry for proper
PSI# operation of Intel’s Eaglelake chipset platforms, reducing
cost and PCB space. This function can be permanently
disabled, making the ISL6334B and ISL6334C compatible with
ISL6334 and ISL6334A, for other platform implementations.
The dropped PWM is forced low for 200ns (uncoupled case)
or until falling edge of coupled PWM (coupled case) then
pulled to VCC/2, while the remained PWM(s) sends out a
special 3-level PWM protocol that the dedicated VR11.1
drivers can decode and then enter diode emulation mode
with gate drive voltage optimization.
The ISL6334C only generates 2-level normal CCM PWM
except for faults. No dedicated VR11.1 driver is required.
See “Controller and Driver Recommendation” on page 3.
2.5X10
R T = -------------------------F SW
(EQ. 3)
where FSW is the switching frequency of each phase.
FREQUENCY-SETTING RESISTOR VALUE (RT)
PSI#
14
While the controller is operational (VCC above POR,
EN_VTT and EN_PWR are both high, valid VID inputs), it
can pull the PWM pins to ~40% of VCC (~2V for 5V VCC
bias) during various stages, such as soft-start delay, phase
shedding operation, or fault conditions (OC or OV events).
The matching driver's internal PWM resistor divider can
further raise the PWM potential, but not lower it below the
level set by the controller IC. Therefore, the controller's
PWM outputs are directly compatible with Intersil drivers that
require 5V PWM signal amplitudes. Drivers requiring 3.3V
PWM signal amplitudes are generally incompatible.
250
200
150
100
50
0
100k 200k 300k 400k 500k 600k 700k 800k 900k
1M
SWITCHING FREQUENCY (Hz)
FIGURE 3. SWITCHING FREQUENCY vs RT
Current Sensing
The ISL6334B, ISL6334C senses current continuously for
fast response. The ISL6334B, ISL6334C supports inductor
DCR sensing, or resistive sensing techniques. The
associated channel current sense amplifier uses the ISEN
inputs to reproduce a signal proportional to the inductor
current, IL. The sense current, ISEN, is proportional to the
inductor current. The sensed current is used for current
balance, load-line regulation, and overcurrent protection.
The internal circuitry, shown in Figures 4 and 5, represents
one channel of an N-channel converter. This circuitry is
repeated for each channel in the converter, but may not be
active depending on the status of the PWM2, PWM3 and
PWM4 pins, as described in “PWM and PSI# Operation” on
page 13. The input bias current of the current sensing
amplifier is typically 60nA; less than 5k input impedance is
preferred to minimized the offset error.
FN6689.3
May 5, 2016
ISL6334B, ISL6334C
INDUCTOR DCR SENSING
An inductor’s winding is characteristic of a distributed
resistance, as measured by the DCR (Direct Current
Resistance) parameter. Consider the inductor DCR as a
separate lumped quantity, as shown in Figure 4. The
channel current IL, flowing through the inductor, will also
pass through the DCR. Equation 4 shows the s-domain
equivalent voltage across the inductor VL.
V L  s  = I L   s  L + DCR 
(EQ. 4)
A simple R-C network across the inductor extracts the DCR
voltage, as shown in Figure 4.
VIN
I s
L
L
ISL6596
DCR
VOUT
INDUCTOR
+
+
R
Equation 6 shows that the ratio of the channel current to the
sensed current, ISEN, is driven by the value of the sense
resistor and the DCR of the inductor.
DCR
I SEN = I L  -----------------R
(EQ. 6)
ISEN
RESISTIVE SENSING
For accurate current sense, a dedicated current-sense resistor
RSENSE in series with each output inductor can serve as the
current sense element (see Figure 5). This technique is more
accurate, but reduces overall converter efficiency due to the
additional power loss on the current sense element RSENSE.
The same capacitor CT is needed to match the time delay
between ISEN- and ISEN+ signals. Select the proper CT to
keep the time constant of RISEN and CT (RISEN x CT) close to
27ns.
Equation 7 shows the ratio of the channel current to the
sensed current ISEN.
-
VC(s)
PWM(n)
COUT
-
VL
ISEN+ signals. Select the proper CT to keep the time
constant of RISEN and CT (RISEN x CT) close to 27ns.
C
R SENSE
I SEN = I L  ----------------------R
(EQ. 7)
ISEN
ISL6334B, ISL6334C
The inductor DCR value will increase as the temperature
increases. Therefore, the sensed current will increase as the
temperature of the current sense element increases. In order
to compensate the temperature effect on the sensed current
signal, a Positive Temperature Coefficient (PTC) resistor can
be selected for the sense resistor RISEN, or the integrated
temperature compensation function of ISL6334B, ISL6334C
should be utilized. The integrated temperature compensation
function is described in “External Temperature Compensation”
on page 24.
RISEN(n)
In
CURRENT
SENSE
ISEN-(n)
+
-
ISEN+(n)
CT
DCR
I SEN = I ----------------LR
ISEN
L
FIGURE 4. DCR SENSING CONFIGURATION
The voltage on the capacitor VC, can be shown to be
proportional to the channel current IL. See Equation 5.
L
 s  ------------+ 1   DCR  I L 
 DCR

V C  s  = -------------------------------------------------------------------- s  RC + 1 
(EQ. 5)
If the R-C network components are selected such that the
RC time constant (= R*C) matches the inductor time
constant (= L/DCR), the voltage across the capacitor VC is
equal to the voltage drop across the DCR, i.e., proportional
to the channel current.
With the internal low-offset current amplifier, the capacitor
voltage VC is replicated across the sense resistor RISEN.
Therefore, the current out of ISEN+ pin, ISEN, is proportional
to the inductor current.
Because of the internal filter at ISEN- pin, one capacitor, CT,
is needed to match the time delay between the ISEN- and
15
IL
RSENSE VOUT
COUT
ISL6334B, ISL6334C
RISEN(n)
In
CURRENT
ISEN-(n)
SENSE
+
-
ISEN+(n)
CT
R SENSE
I SEN = I ------------------------L R
ISEN
FIGURE 5. SENSE RESISTOR IN SERIES WITH INDUCTORS
Channel-Current Balance
The sensed current In from each active channel is summed
together and divided by the number of active channels. The
resulting average current IAVG provides a measure of the
FN6689.3
May 5, 2016
ISL6334B, ISL6334C
total load current. Channel current balance is achieved by
comparing the sensed current of each channel to the
average current to make an appropriate adjustment to the
PWM duty cycle of each channel with Intersil’s patented
current-balance method.
Channel current balance is essential in achieving the
thermal advantage of multiphase operation. With good
current balance, the power loss is equally dissipated over
multiple devices and a greater area.
Voltage Regulation
The compensation network shown in Figure 6 assures that
the steady-state error in the output voltage is limited only to
the error in the reference voltage (output of the DAC) and
offset errors in the OFS current source, remote-sense and
error amplifiers. Intersil specifies the guaranteed tolerance of
the ISL6334B, ISL6334C to include the combined tolerances
of each of these elements.
The sensed average current IAVG is tied to FB internally.
This current will develop voltage drop across the resistor
between FB and VDIFF pins for droop control. ISL6334B,
ISL6334C can not be used for non-droop applications.
The output of the error amplifier, VCOMP, is compared to
sawtooth waveforms to generate the PWM signals. The
PWM signals control the timing of the Intersil MOSFET
drivers and regulate the converter output to the specified
reference voltage. The internal and external circuitry, which
control voltage regulation, are illustrated in Figure 6.
EXTERNAL CIRCUIT ISL6334B, ISL6334C
RC CC
COMP
DAC
RREF
REF
CREF
+
-
FB
RFB
+
VDROOP
-
VOUT+
VOUT-
VCOMP
ERROR AMPLIFIER
IAVG
VDIFF
TABLE 2. VR11 VID 8-BIT
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE
0
0
0
0
0
0
0
0
OFF
0
0
0
0
0
0
0
1
OFF
0
0
0
0
0
0
1
0
1.60000
0
0
0
0
0
0
1
1
1.59375
0
0
0
0
0
1
0
0
1.58750
0
0
0
0
0
1
0
1
1.58125
0
0
0
0
0
1
1
0
1.57500
0
0
0
0
0
1
1
1
1.56875
0
0
0
0
1
0
0
0
1.56250
0
0
0
0
1
0
0
1
1.55625
0
0
0
0
1
0
1
0
1.55000
0
0
0
0
1
0
1
1
1.54375
0
0
0
0
1
1
0
0
1.53750
0
0
0
0
1
1
0
1
1.53125
0
0
0
0
1
1
1
0
1.52500
0
0
0
0
1
1
1
1
1.51875
0
0
0
1
0
0
0
0
1.51250
0
0
0
1
0
0
0
1
1.50625
-
0
0
0
1
0
0
1
0
1.50000
0
0
0
1
0
0
1
1
1.49375
0
0
0
1
0
1
0
0
1.48750
0
0
0
1
0
1
0
1
1.48125
0
0
0
1
0
1
1
0
1.47500
0
0
0
1
0
1
1
1
1.46875
0
0
0
1
1
0
0
0
1.46250
0
0
0
1
1
0
0
1
1.45625
DIFFERENTIAL
REMOTE-SENSE
AMPLIFIER
FIGURE 6. OUTPUT VOLTAGE AND LOAD-LINE
REGULATION WITH OFFSET ADJUSTMENT
The ISL6334B, ISL6334C incorporates an internal
differential remote-sense amplifier in the feedback path. The
amplifier removes the voltage error encountered when
measuring the output voltage relative to the local controller
16
A digital-to-analog converter (DAC) generates a reference
voltage based on the state of logic signals at pins VID7
through VID0. The DAC decodes the eight 6-bit logic signal
(VID) into one of the discrete voltages shown in Table 2. All
VID pins have no internal pull-up current sources until after
tD3. After tD3, each VID input offers a minimum 30µA pull-up
to an internal 2.5V source for use with open-drain outputs.
The pull-up current diminishes to zero above the logic
threshold to protect voltage-sensitive output devices.
External pull-up resistors can augment the pull-up current
sources in case leakage into the driving device is greater
than 30µA.
+
VSEN
RGND
ground reference point, resulting in a more accurate means
of sensing output voltage. Connect the microprocessor
sense pins to the non-inverting input, VSEN, and inverting
input, RGND, of the remote-sense amplifier. The
remote-sense output, VDIFF, is connected to the inverting
input of the error amplifier through an external resistor.
FN6689.3
May 5, 2016
ISL6334B, ISL6334C
TABLE 2. VR11 VID 8-BIT (Continued)
TABLE 2. VR11 VID 8-BIT (Continued)
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE
0
0
0
1
1
0
1
0
1.45000
0
1
0
0
0
0
1
0
1.20000
0
0
0
1
1
0
1
1
1.44375
0
1
0
0
0
0
1
1
1.19375
0
0
0
1
1
1
0
0
1.43750
0
1
0
0
0
1
0
0
1.18750
0
0
0
1
1
1
0
1
1.43125
0
1
0
0
0
1
0
1
1.18125
0
0
0
1
1
1
1
0
1.42500
0
1
0
0
0
1
1
0
1.17500
0
0
0
1
1
1
1
1
1.41875
0
1
0
0
0
1
1
1
1.16875
0
0
1
0
0
0
0
0
1.41250
0
1
0
0
1
0
0
0
1.16250
0
0
1
0
0
0
0
1
1.40625
0
1
0
0
1
0
0
1
1.15625
0
0
1
0
0
0
1
0
1.40000
0
1
0
0
1
0
1
0
1.15000
0
0
1
0
0
0
1
1
1.39375
0
1
0
0
1
0
1
1
1.14375
0
0
1
0
0
1
0
0
1.38750
0
1
0
0
1
1
0
0
1.13750
0
0
1
0
0
1
0
1
1.38125
0
1
0
0
1
1
0
1
1.13125
0
0
1
0
0
1
1
0
1.37500
0
1
0
0
1
1
1
0
1.12500
0
0
1
0
0
1
1
1
1.36875
0
1
0
0
1
1
1
1
1.11875
0
0
1
0
1
0
0
0
1.36250
0
1
0
1
0
0
0
0
1.11250
0
0
1
0
1
0
0
1
1.35625
0
1
0
1
0
0
0
1
1.10625
0
0
1
0
1
0
1
0
1.35000
0
1
0
1
0
0
1
0
1.10000
0
0
1
0
1
0
1
1
1.34375
0
1
0
1
0
0
1
1
1.09375
0
0
1
0
1
1
0
0
1.33750
0
1
0
1
0
1
0
0
1.08750
0
0
1
0
1
1
0
1
1.33125
0
1
0
1
0
1
0
1
1.08125
0
0
1
0
1
1
1
0
1.32500
0
1
0
1
0
1
1
0
1.07500
0
0
1
0
1
1
1
1
1.31875
0
1
0
1
0
1
1
1
1.06875
0
0
1
1
0
0
0
0
1.31250
0
1
0
1
1
0
0
0
1.06250
0
0
1
1
0
0
0
1
1.30625
0
1
0
1
1
0
0
1
1.05625
0
0
1
1
0
0
1
0
1.30000
0
1
0
1
1
0
1
0
1.05000
0
0
1
1
0
0
1
1
1.29375
0
1
0
1
1
0
1
1
1.04375
0
0
1
1
0
1
0
0
1.28750
0
1
0
1
1
1
0
0
1.03750
0
0
1
1
0
1
0
1
1.28125
0
1
0
1
1
1
0
1
1.03125
0
0
1
1
0
1
1
0
1.27500
0
1
0
1
1
1
1
0
1.02500
0
0
1
1
0
1
1
1
1.26875
0
1
0
1
1
1
1
1
1.01875
0
0
1
1
1
0
0
0
1.26250
0
1
1
0
0
0
0
0
1.01250
0
0
1
1
1
0
0
1
1.25625
0
1
1
0
0
0
0
1
1.00625
0
0
1
1
1
0
1
0
1.25000
0
1
1
0
0
0
1
0
1.00000
0
0
1
1
1
0
1
1
1.24375
0
1
1
0
0
0
1
1
0.99375
0
0
1
1
1
1
0
0
1.23750
0
1
1
0
0
1
0
0
0.98750
0
0
1
1
1
1
0
1
1.23125
0
1
1
0
0
1
0
1
0.98125
0
0
1
1
1
1
1
0
1.22500
0
1
1
0
0
1
1
0
0.97500
0
0
1
1
1
1
1
1
1.21875
0
1
1
0
0
1
1
1
0.96875
0
1
0
0
0
0
0
0
1.21250
0
1
1
0
1
0
0
0
0.96250
0
1
0
0
0
0
0
1
1.20625
0
1
1
0
1
0
0
1
0.95625
17
FN6689.3
May 5, 2016
ISL6334B, ISL6334C
TABLE 2. VR11 VID 8-BIT (Continued)
TABLE 2. VR11 VID 8-BIT (Continued)
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE
0
1
1
0
1
0
1
0
0.95000
1
0
0
1
0
0
1
0
0.70000
0
1
1
0
1
0
1
1
0.94375
1
0
0
1
0
0
1
1
0.69375
0
1
1
0
1
1
0
0
0.93750
1
0
0
1
0
1
0
0
0.68750
0
1
1
0
1
1
0
1
0.93125
1
0
0
1
0
1
0
1
0.68125
0
1
1
0
1
1
1
0
0.92500
1
0
0
1
0
1
1
0
0.67500
0
1
1
0
1
1
1
1
0.91875
1
0
0
1
0
1
1
1
0.66875
0
1
1
1
0
0
0
0
0.91250
1
0
0
1
1
0
0
0
0.66250
0
1
1
1
0
0
0
1
0.90625
1
0
0
1
1
0
0
1
0.65625
0
1
1
1
0
0
1
0
0.90000
1
0
0
1
1
0
1
0
0.65000
0
1
1
1
0
0
1
1
0.89375
1
0
0
1
1
0
1
1
0.64375
0
1
1
1
0
1
0
0
0.88750
1
0
0
1
1
1
0
0
0.63750
0
1
1
1
0
1
0
1
0.88125
1
0
0
1
1
1
0
1
0.63125
0
1
1
1
0
1
1
0
0.87500
1
0
0
1
1
1
1
0
0.62500
0
1
1
1
0
1
1
1
0.86875
1
0
0
1
1
1
1
1
0.61875
0
1
1
1
1
0
0
0
0.86250
1
0
1
0
0
0
0
0
0.61250
0
1
1
1
1
0
0
1
0.85625
1
0
1
0
0
0
0
1
0.60625
0
1
1
1
1
0
1
0
0.85000
1
0
1
0
0
0
1
0
0.60000
0
1
1
1
1
0
1
1
0.84375
1
0
1
0
0
0
1
1
0.59375
0
1
1
1
1
1
0
0
0.83750
1
0
1
0
0
1
0
0
0.58750
0
1
1
1
1
1
0
1
0.83125
1
0
1
0
0
1
0
1
0.58125
0
1
1
1
1
1
1
0
0.82500
1
0
1
0
0
1
1
0
0.57500
0
1
1
1
1
1
1
1
0.81875
1
0
1
0
0
1
1
1
0.56875
1
0
0
0
0
0
0
0
0.81250
1
0
1
0
1
0
0
0
0.56250
1
0
0
0
0
0
0
1
0.80625
1
0
1
0
1
0
0
1
0.55625
1
0
0
0
0
0
1
0
0.80000
1
0
1
0
1
0
1
0
0.55000
1
0
0
0
0
0
1
1
0.79375
1
0
1
0
1
0
1
1
0.54375
1
0
0
0
0
1
0
0
0.78750
1
0
1
0
1
1
0
0
0.53750
1
0
0
0
0
1
0
1
0.78125
1
0
1
0
1
1
0
1
0.53125
1
0
0
0
0
1
1
0
0.77500
1
0
1
0
1
1
1
0
0.52500
1
0
0
0
0
1
1
1
0.76875
1
0
1
0
1
1
1
1
0.51875
1
0
0
0
1
0
0
0
0.76250
1
0
1
1
0
0
0
0
0.51250
1
0
0
0
1
0
0
1
0.75625
1
0
1
1
0
0
0
1
0.50625
1
0
0
0
1
0
1
0
0.75000
1
0
1
1
0
0
1
0
0.50000
1
0
0
0
1
0
1
1
0.74375
1
1
1
1
1
1
1
0
OFF
1
0
0
0
1
1
0
0
0.73750
1
1
1
1
1
1
1
1
OFF
1
0
0
0
1
1
0
1
0.73125
1
0
0
0
1
1
1
0
0.72500
1
0
0
0
1
1
1
1
0.71875
1
0
0
1
0
0
0
0
0.71250
1
0
0
1
0
0
0
1
0.70625
18
Load-Line Regulation
Some microprocessor manufacturers require a precisely
controlled output resistance. This dependence of output
voltage on load current is often termed “droop” or “load line”
regulation. By adding a well controlled output impedance,
the output voltage can effectively be level shifted in a
FN6689.3
May 5, 2016
ISL6334B, ISL6334C
direction, which works to achieve the load-line regulation
required by these manufacturers.
In other cases, the designer may determine that a more
cost-effective solution can be achieved by adding droop.
Droop can help to reduce the output-voltage spike that
results from fast load-current demand changes.
The magnitude of the spike is dictated by the ESR and ESL
of the output capacitors selected. By positioning the no-load
voltage level near the upper specification limit, a larger
negative spike can be sustained without crossing the lower
limit. By adding a well controlled output impedance, the
output voltage under load can effectively be level shifted
down so that a larger positive spike can be sustained without
crossing the upper specification limit.
For Positive Offset (connect ROFS to VCC):
1.6  R REF
R OFS = ---------------------------V OFFSET
For Negative Offset (connect ROFS to GND):
0.4  R REF
R OFS = ---------------------------V OFFSET
(EQ. 12)
FB
DYNAMIC
VID D/A
E/A
REF
CREF
(EQ. 8)
The regulated output voltage is reduced by the droop voltage
VDROOP. The output voltage as a function of load current is
derived by combining Equation 8 with the appropriate
sample current expression defined by the current sense
method employed, as shown in Equation 9:
 I LOAD R X

- ------------------ R FB
V OUT = V REF – V OFS –  ---------------N
R


ISEN
(EQ. 10)
Output-Voltage Offset Programming
The ISL6334B, ISL6334C allows the designer to accurately
adjust the offset voltage. When a resistor, ROFS, is
connected between OFS to VCC, the voltage across it is
regulated to 1.6V. This causes a proportional current (IOFS)
to flow into OFS. If ROFS is connected to ground, the voltage
across it is regulated to 0.4V, and IOFS flows out of OFS. A
resistor between DAC and REF, RREF, is selected so that
the product (IOFS x ROFS) is equal to the desired offset
voltage. These functions are shown in Figure 7.
Once the desired output offset voltage has been determined,
use Equations 11 and 12 to calculate ROFS:
19
1.6V
-
ROFS
+
+
0.4V
VCC
Therefore, the equivalent loadline impedance, i.e. Droop
impedance, is equal to Equation 10:
R FB R X
R LL = ----------------------------N R ISEN
VCC
OR
GND
(EQ. 9)
where VREF is the reference voltage, VOFS is the
programmed offset voltage, ILOAD is the total output current
of the converter, RISEN is the sense resistor connected to
the ISEN+ pin, and RFB is the feedback resistor, N is the
active channel number, and RX is the DCR, or RSENSE
depending on the sensing method.
DAC
RREF
As shown in Figure 6, a current proportional to the average
current of all active channels, IAVG, flows from FB through a
load-line regulation resistor RFB. The resulting voltage drop
across RFB is proportional to the output current, effectively
creating an output voltage droop with a steady-state value
defined as shown in Equation 8:
V DROOP = I AVG  R
FB
(EQ. 11)
-
ISL6334B, ISL6334C
OFS
GND
FIGURE 7. OUTPUT VOLTAGE OFFSET PROGRAMMING
Dynamic VID
Modern microprocessors need to make changes to their
core voltage as part of normal operation. They direct the
core-voltage regulator to do this by making changes to the
VID inputs during regulator operation. The power
management solution is required to monitor the DAC inputs
and respond to on-the-fly VID changes in a controlled
manner. Supervising the safe output voltage transition within
the DAC range of the processor without discontinuity or
disruption is a necessary function of the core-voltage
regulator.
In order to ensure the smooth transition of output voltage
during VID change, a VID step change smoothing network,
composed of RREF and CREF, as shown in Figure 7, can be
used. The selection of RREF is based on the desired offset
voltage as detailed in “Output-Voltage Offset Programming”
on page 19. The selection of CREF is based on the time
duration for 1-bit VID change and the allowable delay time.
Assuming the microprocessor controls the VID change at
1-bit every tVID, the relationship between the time constant
of RREF and CREF network and tVID is given by Equation 13.
FN6689.3
May 5, 2016
ISL6334B, ISL6334C
C REF  R
(EQ. 13)
= t VID
REF
During dynamic VID transition and VID steps up, the
overcurrent trip point increases by 140% to avoid falsely
triggering OCP circuits, while the overvoltage trip point is set
to its maximum VID OVP trip level. If the dynamic VID occurs
at PSI# asserted, the system should exit PSI# and complete
the transition, and then resume PSI# operation 50µs after
the transition.
Operation Initialization
Prior to converter initialization, proper conditions must exist
on the enable inputs and VCC. When the conditions are met,
the controller begins soft-start. Once the output voltage is
within the proper window of operation, VR_RDY asserts
logic high.
Enable and Disable
While in shutdown mode, the PWM outputs are held in a
high-impedance state to assure the drivers remain off. The
following input conditions must be met before the ISL6334B,
ISL6334C is released from shutdown mode.
ISL6334B, ISL6334C
EXTERNAL CIRCUIT
+12V
VCC
POR
CIRCUIT
ENABLE
COMPARATOR
+
-
100k
EN_PWR
9.1k
0.870V
+
2. The ISL6334B, ISL6334C features an enable input
(EN_PWR) for power sequencing between the controller
bias voltage and another voltage rail. The enable
comparator holds the ISL6334B, ISL6334C in shutdown
until the voltage at EN_PWR rises above 0.870V. The
enable comparator has about 130mV of hysteresis to
prevent bounce. It is important that the driver reach their
POR level before the ISL6334B, ISL6334C becomes
enabled. The schematic in Figure 8 demonstrates
sequencing the ISL6334B, ISL6334C with the ISL66xx
family of Intersil MOSFET drivers, which require 12V
bias.
3. The voltage on EN_VTT must be higher than 0.870V to
enable the controller. This pin is typically connected to the
output of VTT VR.
When all conditions previously mentioned are satisfied,
ISL6334B, ISL6334C begins the soft-start and ramps the
output voltage to 1.1V first. After remaining at 1.1V for some
time, ISL6334B, ISL6334C reads the VID code at VID input
pins. If the VID code is valid, ISL6334B, ISL6334C will
regulate the output to the final VID setting. If the VID code is
OFF code, ISL6334B, ISL6334C will shut down, and cycling
VCC, EN_PWR or EN_VTT is needed to restart.
Soft-Start
ISL6334B, ISL6334C based VR has 4 periods during soft-start,
as shown in Figure 9. After VCC, EN_VTT and EN_PWR reach
their POR/enable thresholds, the controller will have a fixed
delay period tD1. After this delay period, the VR will begin first
soft-start ramp until the output voltage reaches 1.1V VBOOT
voltage. Then, the controller will regulate the VR voltage at 1.1V
for another fixed period tD3. At the end of tD3 period, ISL6334B,
ISL6334C reads the VID signals. If the VID code is valid,
ISL6334B, ISL6334C will initiate the second soft-start ramp until
the voltage reaches the VID voltage minus offset voltage.
EN_VTT
-
VOUT, 500mV/DIV
0.870V
tD2
tD1
SOFT-START
AND
FAULT LOGIC
tD3 tD4
tD5
EN_VTT
FIGURE 8. POWER SEQUENCING USING THRESHOLDSENSITIVE ENABLE (EN) FUNCTION
VR_RDY
500µs/DIV
1. The bias voltage applied at VCC must reach the internal
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
the ISL6334B, ISL6334C are guaranteed. Hysteresis
between the rising and falling thresholds assure that once
enabled, ISL6334B, ISL6334C will not inadvertently turn
off unless the bias voltage drops substantially (see
“Electrical Specifications” table beginning on page 8).
20
FIGURE 9. SOFT-START WAVEFORMS
The soft-start time is the sum of the 4 periods, as shown in
Equation 14.
t SS = t D1 + t D2 + t D3 + t D4
(EQ. 14)
tD1 is a fixed delay with the typical value as 1.36ms. tD3 is
determined by the fixed 85µs plus the time to obtain valid
VID voltage. If the VID is valid before the output reaches the
FN6689.3
May 5, 2016
ISL6334B, ISL6334C
1.1V, the minimum time to validate the VID input is 500ns.
Therefore, the minimum tD3 is about 86µs.
outlines the interaction between the fault monitors and the
VR_RDY signal.
During tD2 and tD4, ISL6334B, ISL6334C digitally controls
the DAC voltage change at 6.25mV per step. The time for
each step is determined by the frequency of the soft-start
oscillator, which is defined by the resistor RSS from SS pin to
GND. The second soft-start ramp time tD2 and tD4 can be
calculated based on Equations 15 and 16:
1.1  R SS
t D2 = ------------------------  s 
6.25  25
(EQ. 15)
For example, when VID is set to 1.5V and the RSS is set at
100k, the first soft-start ramp time tD2 will be 704µs and the
second soft-start ramp time tD4 will be 256µs.
After the DAC voltage reaches the final VID setting,
VR_RDY will be set to high with the fixed delay tD5. The
typical value for tD5 is 85µs. Before the VR_RDY is
released, the controller disregards the PSI# input and
always operates in normal CCM PWM mode.
The current flowing out of the IMON pin is equal to the
sensed average current inside ISL6334B, ISL6334C. In
typical applications, a resistor is placed from the IMON pin to
GND to generate a voltage, which is proportional to the load
current and the resistor value, as shown in Equation 17:
(EQ. 17)
where VIMON is the voltage at the IMON pin, RIMON is the
resistor between the IMON pin and GND, ILOAD is the total
output current of the converter, RISEN is the sense resistor
connected to the ISEN+ pin, N is the active channel number,
and RX is the DC resistance of the current sense element,
either the DCR of the inductor or RSENSE depending on the
sensing method.
The resistor from the IMON pin to GND should be chosen to
ensure that the voltage at the IMON pin is less than 1.11V
under the maximum load current. If the IMON pin voltage is
higher than 1.11V, overcurrent shutdown will be triggered, as
described in “Overcurrent Protection” on page 22.
A small capacitor can be placed between the IMON pin and
GND to reduce the noise impact. If this pin is not used, tie it
to GND.
Fault Monitoring and Protection
The ISL6334B, ISL6334C actively monitors output voltage and
current to detect fault conditions. Fault monitors trigger
protective measures to prevent damage to a microprocessor
load. One common power-good indicator is provided for linking
to external system monitors. The schematic in Figure 10
21
50%
+
105µA
-
IAVG
OC
DAC
SOFT-START, FAULT
AND CONTROL LOGIC
VDIFF
+
OV
-
+
OC
1.11V
IMON
-
VID + 0.175V
FIGURE 10. VR_RDY AND PROTECTION CIRCUITRY
VR_RDY Signal
Current Sense Output
R IOUT R X
- ------------------ I LOAD
V IOUT = -----------------N
R ISEN
+
(EQ. 16)
-
 V VID – 1.1   R
SS
t D4 = -------------------------------------------------  s 
6.25  25
UV
The VR_RDY pin is an open-drain logic output which
indicates that the soft-start period has completed and the
output voltage is within the regulated range. VR_RDY is
pulled low during shutdown and releases high after a
successful soft-start and a fixed delay tD5. VR_RDY will be
pulled low when an undervoltage or overvoltage condition is
detected, or the controller is disabled by a reset from
EN_PWR, EN_VTT, POR, or VID OFF-code.
Undervoltage Detection
The undervoltage threshold is set at 50% of the VID code.
When the output voltage at VSEN is below the undervoltage
threshold, VR_RDY is pulled low.
Overvoltage Protection
Regardless of the VR being enabled or not, the ISL6334B,
ISL6334C overvoltage protection (OVP) circuit will be active
after its POR. The OVP thresholds are different under different
operation conditions. When VR is not enabled and during the
soft-start intervals tD1, tD2 and tD3, the OVP threshold is
1.273V. Once the controller detects valid VID input, the OVP
trip point will be changed to DAC plus 175mV.
Two actions are taken by ISL6334B, ISL6334C to protect the
microprocessor load when an overvoltage condition occurs.
At the inception of an overvoltage event, all PWM outputs are
commanded low instantly (less than 20ns). This causes the
Intersil drivers to turn on the lower MOSFETs and pull the
output voltage below a level to avoid damaging the load. When
the VDIFF voltage falls below the DAC plus 75mV, PWM
signals enter a high-impedance state. The Intersil drivers
respond to the high-impedance input by turning off both upper
FN6689.3
May 5, 2016
ISL6334B, ISL6334C
and lower MOSFETs. If the overvoltage condition reoccurs,
ISL6334B, ISL6334C will again command the lower MOSFETs
to turn on. ISL6334B, ISL6334C will continue to protect the load
in this fashion as long as the overvoltage condition occurs.
Once an overvoltage condition is detected, normal PWM
operation ceases until ISL6334B, ISL6334C is reset. Cycling
the voltage on EN_PWR, EN_VTT or VCC below the
POR-falling threshold will reset the controller. Cycling the
VID codes will not reset the controller.
Overcurrent Protection
ISL6334B, ISL6334C has two levels of overcurrent protection.
Each phase is protected from a sustained overcurrent
condition by limiting its peak current, while the combined
phase currents are protected on an instantaneous basis.
In instantaneous protection mode, ISL6334B, ISL6334C
utilizes the sensed average current IAVG to detect an
overcurrent condition. See “Channel-Current Balance” on
page 15 for more details on how the average current is
measured. The average current is continually compared with
a constant 105µA reference current, as shown in Figure 10.
Once the average current exceeds the reference current, a
comparator triggers the converter to shutdown.
The current out of IMON pin is equal to the sensed average
current IAVG. With a resistor from IMON to GND, the voltage
at IMON will be proportional to the sensed average current
and the resistor value. The ISL6334B, ISL6334C continuously
monitors the voltage at IMON pin. If the voltage at IMON pin is
higher than 1.11V, a comparator triggers the overcurrent
shutdown. By increasing the resistor between IMON and
GND, the overcurrent protection threshold can be adjusted to
be less than 105µA. For example, the overcurrent threshold
for the sensed average current IAVG can be set to 95µA by
using a 11.8k resistor from IMON to GND.
both upper and lower MOSFETs. The system remains in this
state a period of 4096 switching cycles. If the controller is still
enabled at the end of this wait period, it will attempt a
soft-start. If the fault remains, the trip-retry cycles will
continue indefinitely (as shown in Figure 11) until either
controller is disabled or the fault is cleared. Note that the
energy delivered during trip-retry cycling is much less than
during full-load operation, so there is no thermal hazard
during this kind of operation.
For the individual channel overcurrent protection, ISL6334B,
ISL6334C continuously compares the sensed current signal
of each channel with the 129µA reference current. If one
channel current exceeds the reference current, ISL6334B,
ISL6334C will pull PWM signal of this channel to low for the
rest of the switching cycle. This PWM signal can be turned
on next cycle if the sensed channel current is less than the
129µA reference current. The peak current limit of individual
channel will not trigger the converter to shutdown.
Thermal Monitoring (VR_HOT)
VR_HOT is a thermal signal to indicate the temperature
status of the voltage regulator and valid only after the
controller is enabled. The VR_HOT pin is an open-drain
output, and an external pull-up resistor is required.
The VR_HOT signal can be used to inform the system that
the temperature of the voltage regulator is too high and the
CPU should reduce its power consumption. The VR_HOT
signal may be tied to the CPU’s PROC_HOT signal.
VCC
R TM1
OUTPUT CURRENT
VR_HOT
TM
oc
RNTC
0.333VCC
0A
FIGURE 12. BLOCK DIAGRAM OF THERMAL MONITORING
FUNCTION
OUTPUT VOLTAGE
0V
2ms/DIV
FIGURE 11. OVERCURRENT BEHAVIOR IN HICCUP MODE.
FSW = 500kHz
At the beginning of overcurrent shutdown, the controller
places all PWM signals in a high-impedance state within
20ns, commanding the Intersil MOSFET driver ICs to turn off
22
The diagram of thermal monitoring function block is shown in
Figure 12. One NTC resistor should be placed close to the
power stage of the voltage regulator to sense the operational
temperature, and one pull-up resistor is needed to form the
voltage divider for the TM pin. As the temperature of the
power stage increases, the resistance of the NTC will
reduce, resulting in the reduced voltage at the TM pin.
Figure 13 shows the TM voltage over the temperature for a
typical design with a recommended 6.8k NTC (P/N:
NTHS0805N02N6801 from Vishay) and 1k resistor RTM1.
FN6689.3
May 5, 2016
ISL6334B, ISL6334C
Temperature Compensation
100
The ISL6334B, ISL6334C supports inductor DCR sensing,
or resistive sensing techniques. The inductor DCR has a
positive temperature coefficient, which is about +0.385%/°C.
Since the voltage across inductor is sensed for the output
current information, the sensed current has the same
positive temperature coefficient as the inductor DCR.
90
VTM/VCC (%)
80
70
60
50
40
30
20
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
FIGURE 13. THE RATIO OF TM VOLTAGE TO NTC
TEMPERATURE WITH RECOMMENDED PARTS
We recommend using those resistors for the accurate
temperature compensation.
There is an comparator with hysteresis to compare the TM
pin voltage to the fixed threshold for the VR_HOT signal.
The VR_HOT signal is set to high when the TM voltage goes
below 33.3% of VCC voltage, and is pulled to GND when the
TM voltage goes back to above 39.1% of VCC voltage.
Figure 14 shows the operation of those signals.
In order to obtain the correct current information, there
should be a way to correct the temperature impact on the
current sense component. ISL6334B, ISL6334C provides
two methods: integrated temperature compensation and
external temperature compensation.
Integrated Temperature Compensation
When the TCOMP voltage is equal or greater than VCC/15,
ISL6334B, ISL6334C will utilize the voltage at TM and
TCOMP pins to compensate the temperature impact on the
sensed current. The block diagram of this function is shown
in Figure 15.
VCC
R TM1
TM
TM
0.391*Vcc
0.333*Vcc
o
VR_HOT
c
R NTC
D/A
VCC
TEMPERATURE
T2
T3
NON-LINEAR
A/D
Isen4
Isen3
Isen2
Isen1
CHANNEL
CURRENT
SENSE
I4
I3
I2
I1
ki
R TC1
TCOMP
FIGURE 14. VR_HOT SIGNAL vs TM VOLTAGE
4-BIT
A/D
DROOP AND
OVERCURRENT
PROTECTION
R TC2
Based on the NTC temperature characteristics and the
desired threshold of the VR_HOT signal, the pull-up resistor
RTM1 of TM pin is given by Equation 18:
R TM1 = 2.75xR NTC  T3 
(EQ. 18)
RNTC(T3) is the NTC resistance at the VR_HOT threshold
temperature T3.
The NTC resistance at the set point T2 can be calculated as
shown in Equations 19:
R NTC  T2  = 1.267xR NTC  T3 
(EQ. 19)
With the NTC resistance value obtained from Equations 18
and 19, the temperature value T3 and T2 can be found from
the NTC datasheet.
23
FIGURE 15. BLOCK DIAGRAM OF INTEGRATED
TEMPERATURE COMPENSATION
When the TM NTC is placed close to the current sense
component (inductor), the temperature of the NTC will track
the temperature of the current sense component. Therefore
the TM voltage can be utilized to obtain the temperature of
the current sense component.
Based on VCC voltage, ISL6334B, ISL6334C converts the
TM pin voltage to a 6-bit TM digital signal for temperature
compensation. With the non-linear A/D converter of
ISL6334B, ISL6334C, the TM digital signal is linearly
proportional to the NTC temperature. For accurate
temperature compensation, the ratio of the TM voltage to the
NTC temperature of the practical design should be similar to
that in Figure 13.
FN6689.3
May 5, 2016
ISL6334B, ISL6334C
Depending on the location of the NTC and the airflow, the
NTC may be cooler or hotter than the current sense
component. The TCOMP pin voltage can be utilized to
correct the temperature difference between NTC and the
current sense component. When a different NTC type or
different voltage divider is used for the TM function, the
TCOMP voltage can also be used to compensate for the
difference between the recommended TM voltage curve in
Figure 14 and that of the actual design. According to the
VCC voltage, ISL6334B, ISL6334C converts the TCOMP pin
voltage to a 4-bit TCOMP digital signal as TCOMP factor N.
The TCOMP factor N is an integer between 0 and 15. The
integrated temperature compensation function is disabled for
N = 0. For N = 4, the NTC temperature is equal to the
temperature of the current sense component. For N < 4, the
NTC is hotter than the current sense component. The NTC is
cooler than the current sense component for N > 4. When
N > 4, the larger TCOMP factor N, the larger the difference
between the NTC temperature and the temperature of the
current sense component.
ISL6334B, ISL6334C multiplexes the TCOMP factor N with
the TM digital signal to obtain the adjustment gain to
compensate the temperature impact on the sensed channel
current. The compensated channel current signal is used for
droop and overcurrent protection functions.
9. Run the actual board under full load again with the proper
resistors connected to the TCOMP pin.
10. Record the output voltage as V1 immediately after the
output voltage is stable with the full load. Record the
output voltage as V2 after the VR reaches the thermal
steady state.
11. If the output voltage increases over 2mV as the
temperature increases, i.e. V2 - V1 > 2mV, reduce N and
redesign RTC2; if the output voltage decreases over 2mV
as the temperature increases, i.e. V1 - V2 > 2mV,
increase N and redesign RTC2.
External Temperature Compensation
By pulling the TCOMP pin to GND, the integrated
temperature compensation function is disabled. In addition,
one external temperature compensation network, shown in
Figure 16, can be used to cancel the temperature impact on
the droop (i.e., load line).
COMP
IS L 6 3 3 4 B ,
IS L 6 3 3 4 C
IN T E R N A L
C IR C U IT
FB
o
C
IS E N
Design Procedure
1. Properly choose the voltage divider for the TM pin to
match the TM voltage vs temperature curve with the
recommended curve in Figure 13.
2. Run the actual board under the full load and the desired
cooling condition.
3. After the board reaches the thermal steady state, record
the temperature (TCSC) of the current sense component
(inductor or MOSFET) and the voltage at TM and VCC
pins.
4. Use Equation 20 to calculate the resistance of the TM
NTC, and find out the corresponding NTC temperature
TNTC from the NTC datasheet.
R NTC  T
V TM xR
TM1
= ------------------------------
V CC – V
NTC
TM
(EQ. 20)
5. Use Equation 21 to calculate the TCOMP factor N:
209x  T CSC – T

NTC
N = -------------------------------------------------------- + 4
3xT NTC + 400
(EQ. 21)
6. Choose an integral number close to the above result for
the TCOMP factor. If this factor is higher than 15, use
N = 15. If it is less than 1, use N = 1.
7. Choose the pull-up resistor RTC1 (typical 10k);
8. If N = 15, one does not need the pull-down resistor RTC2.
If otherwise, obtain RTC2 using Equation 22:
NxR TC1
R TC2 = ----------------------15 – N
(EQ. 22)
24
V D IF F
FIGURE 16. EXTERNAL TEMPERATURE COMPENSATION
The sensed current will flow out of the FB pin and develop a
droop voltage across the resistor equivalent (RFB) between
the FB and VDIFF pins. If RFB resistance reduces as the
temperature increases, the temperature impact on the droop
can be compensated. An NTC resistor can be placed close to
the power stage and used to form RFB. Due to the non-linear
temperature characteristics of the NTC, a resistor network is
needed to make the equivalent resistance between the FB
and VDIFF pins reverse proportional to the temperature.
The external temperature compensation network can only
compensate the temperature impact on the droop, while it has
no impact to the sensed current inside ISL6334B, ISL6334C.
Therefore, this network cannot compensate for the
temperature impact on the overcurrent protection function.
General Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to create a multiphase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced in the
following. In addition to this guide, Intersil provides complete
reference designs, which include schematics, bills of
materials, and example board layouts for all common
microprocessor applications.
FN6689.3
May 5, 2016
ISL6334B, ISL6334C
Power Stages
The first step in designing a multiphase converter is to
determine the number of phases. This determination
depends heavily upon the cost analysis, which in turn
depends on system constraints that differ from one design to
the next. Principally, the designer will be concerned with
whether components can be mounted on both sides of the
circuit board; whether through-hole components are
permitted; and the total board space available for power
supply circuitry. Generally speaking, the most economical
solutions are those in which each phase handles between
15A and 25A. All surface-mount designs will tend toward the
lower end of this current range. If through-hole MOSFETs
and inductors can be used, higher per-phase currents are
possible. In cases where board space is the limiting
constraint, current can be pushed as high as 40A per phase,
but these designs require heat sinks and forced air to cool
the MOSFETs, inductors and heat-dissipating surfaces.
MOSFETs
The choice of MOSFETs depends on the current each
MOSFET will be required to conduct; the switching
frequency; the capability of the MOSFETs to dissipate heat;
and the availability and nature of heat sinking and air flow.
LOWER MOSFET POWER CALCULATION
The calculation for heat dissipated in the lower MOSFET is
simple, since virtually all of the heat loss in the lower
MOSFET is due to current conducted through the channel
resistance (rDS(ON)). In Equation 23, IM is the maximum
continuous output current; IP-P is the peak-to-peak inductor
current (see Equation 1); d is the duty cycle (VOUT/VIN); and
L is the per-channel inductance.
P LOW 1 = r DS  ON 
I L, P-P2 1 – d 
 I M 2
   1 – d  + -------------------------------------- N
(EQ. 23)
12
An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the
dead time when inductor current is flowing through the
lower-MOSFET body diode. This term is dependent on the
diode forward voltage at IM, VD(ON); the switching
frequency, Fsw; and the length of dead times, td1 and td2, at
the beginning and the end of the lower-MOSFET conduction
interval respectively.
I

IM I 
(EQ. 24)
M I P-P
P-P- t
P LOW 2 = V D  ON  F sw  ----d1 +  ------ – ---------- t d2
 N- + --------
2 
2
N
Thus the total maximum power dissipated in each lower
MOSFET is approximated by the summation of PLOW,1 and
PLOW,2.
Upper MOSFET Power Calculation
In addition to rDS(ON) losses, a large portion of the upperMOSFET losses are due to currents conducted across the
input voltage (VIN) during switching. Since a substantially
higher portion of the upper-MOSFET losses are dependent on
switching frequency, the power calculation is more complex.
25
Upper MOSFET losses can be divided into separate
components involving the upper-MOSFET switching times;
the lower-MOSFET body-diode reverse-recovery charge, Qrr;
and the upper MOSFET rDS(ON) conduction loss.
When the upper MOSFET turns off, the lower MOSFET does
not conduct any portion of the inductor current until the
voltage at the phase node falls below ground. Once the
lower MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
ramps up to assume the full inductor current. In Equation 25,
the required time for this commutation is t1 and the
approximated associated power loss is PUP,1.
I M I P-P  t 1 
P UP,1  V IN  -----  ----  f
 N- + --------2   2 S
(EQ. 25)
At turn on, the upper MOSFET begins to conduct and this
transition occurs over a time t2. In Equation 26, the
approximate power loss is PUP,2.
 I M I P-P  t 2 
P UP, 2  V IN  ----- – ----------  ----  f S
2  2
N
(EQ. 26)
A third component involves the lower MOSFET’s reverserecovery charge, Qrr. Since the inductor current has fully
commutated to the upper MOSFET before the
lower-MOSFET’s body diode can draw all of Qrr, it is conducted
through the upper MOSFET across VIN. The power dissipated
as a result is PUP,3 and is approximated in Equation 27:
P UP,3 = V IN Q rr f S
(EQ. 27)
Finally, the resistive part of the upper MOSFET’s is given in
Equation 28 as PUP,4.
The total power dissipated by the upper MOSFET at full load
can now be approximated as the summation of the results
from Equations 25, 26, and 27. Since the power equations
depend on MOSFET parameters, choosing the correct
MOSFETs can be an iterative process involving repetitive
solutions to the loss equations for different MOSFETs and
different switching frequencies, as shown in Equation 28.
2
I P-P2
 I M
P UP,4  r DS  ON   ----- d + ---------- d
12
 N
(EQ. 28)
Current Sensing Resistor
The resistors connected to the ISEN+ pins determine the
gains in the load-line regulation loop and the channel-current
balance loop as well as setting the overcurrent trip point.
Select values for these resistors by using Equation 29:
RX
I OCP
R ISEN = -------------------------- ------------–6 N
105 10
(EQ. 29)
where RISEN is the sense resistor connected to the ISEN+
pin, N is the active channel number, RX is the resistance of
the current sense element, either the DCR of the inductor or
RSENSE depending on the sensing method, and IOCP is the
desired overcurrent trip point. Typically, IOCP can be chosen
FN6689.3
May 5, 2016
ISL6334B, ISL6334C
to be 1.2x the maximum load current of the specific
application.
With integrated temperature compensation, the sensed
current signal is independent on the operational temperature
of the power stage, i.e. the temperature effect on the current
sense element RX is cancelled by the integrated
temperature compensation function. RX in Equation 29
should be the resistance of the current sense element at the
room temperature.
When the integrated temperature compensation function is
disabled by pulling the TCOMP pin to GND, the sensed
current will be dependent on the operational temperature of
the power stage, since the DC resistance of the current
sense element may be changed according to the operational
temperature. RX in Equation 29 should be the maximum DC
resistance of the current sense element at the all operational
temperature.
In certain circumstances, it may be necessary to adjust the
value of one or more ISEN resistors. When the components
of one or more channels are inhibited from effectively
dissipating their heat so that the affected channels run hotter
than desired, choose new, smaller values of RISEN for the
affected phases (see the section entitled “Channel-Current
Balance” on page 15). Choose RISEN,2 in proportion to the
desired decrease in temperature rise in order to cause
proportionally less current to flow in the hotter phase, as
shown in Equation 30:
T
R ISEN ,2 = R ISEN ----------2
T 1
(EQ. 30)
In Equation 30, make sure that T2 is the desired temperature
rise above the ambient temperature, and T1 is the measured
temperature rise above the ambient temperature. While a
single adjustment according to Equation 30 is usually
sufficient, it may occasionally be necessary to adjust RISEN
two or more times to achieve optimal thermal balance
between all channels.
where N is the active channel number, RISEN is the sense
resistor connected to the ISEN+ pin, and RX is the
resistance of the current sense element, either the DCR of
the inductor or RSENSE depending on the sensing method.
If one or more of the current sense resistors are adjusted for
thermal balance (as in Equation 30), the load-line regulation
resistor should be selected based on the average value of
the current sensing resistors, as given in Equation 33:
R LL
R FB = ---------RX
 RISEN  n 
(EQ. 33)
n
where RISEN(n) is the current sensing resistor connected to
the nth ISEN+ pin.
Compensation
The two opposing goals of compensating the voltage
regulator are stability and speed. Depending on whether the
regulator employs the optional load-line regulation as
described in Load-Line Regulation, there are two distinct
methods for achieving these goals.
COMPENSATING LOAD-LINE REGULATED
CONVERTER
The load-line regulated converter behaves in a similar
manner to a peak-current mode controller because the two
poles at the output-filter L-C resonant frequency split with
the introduction of current information into the control loop.
The final location of these poles is determined by the system
function, the gain of the current signal, and the value of the
compensation components, RC and CC.
Since the system poles and zero are affected by the values
of the components that are meant to compensate them, the
solution to the system equation becomes fairly complicated.
Fortunately there is a simple approximation that comes very
close to an optimal solution. Treating the system as though it
were a voltage-mode regulator by compensating the L-C
poles and the ESR zero of the voltage-mode approximation
yields a solution that is always stable with very close to ideal
transient performance.
Load-Line Regulation Resistor
RC
The desired loadline can be calculated using Equation 31:
V DROOP
R LL = -----------------------I FL
(EQ. 31)
where IFL is the full load current of the specific application,
and VRDROOP is the desired voltage droop under the full
load condition.
CC
COMP
FB
+
RFB
VDROOP
ISL6334B, ISL6334C
C2 (OPTIONAL)
The load-line regulation resistor is labelled RFB in Figure 6.
Its value depends on the desired loadline requirement of the
application.
VDIFF
Based on the desired loadline RLL, the loadline regulation
resistor can be calculated using Equation 32:
NR
R
ISEN LL
R FB = --------------------------------RX
(EQ. 32)
26
FIGURE 17. COMPENSATION CONFIGURATION FOR
LOAD-LINE REGULATED ISL6334B, ISL6334C
CIRCUIT
FN6689.3
May 5, 2016
ISL6334B, ISL6334C
The feedback resistor, RFB, has already been chosen as
outlined in “Load-Line Regulation Resistor” on page 26.
Select a target bandwidth for the compensated system, f0.
The target bandwidth must be large enough to assure
adequate transient performance, but smaller than 1/3 of the
per-channel switching frequency. The values of the
compensation components depend on the relationships of f0
to the L-C pole frequency and the ESR zero frequency. For
each of the three cases which follow, there is a separate set
of equations for the compensation components.
Case 1:
1
------------------- > f 0
2 LC
IN
0.75V IN
C C = ----------------------------------2V PP R FB f 0
1
1
-------------------  f 0 < ----------------------------2C  ESR 
2 LC
V P-P  2  2 f 02 LC
R C = R FB --------------------------------------------0.75 V
(EQ. 34)
IN
0.75V IN
C C = -----------------------------------------------------------2
 2  f 02 V PP R FB LC
Case 3:
The output inductors and the output capacitor bank together
to form a low-pass filter responsible for smoothing the
pulsating voltage at the phase nodes. The output filter also
must provide the transient energy until the regulator can
respond. Because it has a low bandwidth compared to the
switching frequency, the output filter necessarily limits the
system transient response. The output capacitor must
supply or sink load current while the current in the output
inductors increases or decreases to meet the demand.
In high-speed converters, the output capacitor bank is usually
the most costly (and often the largest) part of the circuit.
Output filter design begins with minimizing the cost of this part
of the circuit. The critical load parameters in choosing the
output capacitors are the maximum size of the load step, I;
the load-current slew rate, di/dt; and the maximum allowable
output-voltage deviation under transient loading, VMAX.
Capacitors are characterized according to their capacitance,
ESR, and ESL (equivalent series inductance).
2f 0 V P-P LC
R C = R FB ------------------------------------0.75V
Case 2:
Output Filter Design
1
f 0 > -----------------------------2C  ESR 
2 f 0 V P-P L
R C = R FB ----------------------------------------0.75 V IN  ESR 
0.75V IN  ESR  C
C C = -----------------------------------------------2V PP R FB f 0 L
In Equation 34, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent-series resistance of
the bulk output-filter capacitance; and VPP is the sawtooth
amplitude described in the “Electrical Specifications” table
beginning on page 8.
The optional capacitor C2, is sometimes needed to bypass
noise away from the PWM comparator. Keep a position
available for C2, and be prepared to install a high-frequency
capacitor of between 10pF and 100pF in case any
leading-edge jitter problem is noted.
Once selected, the compensation values in Equation 34
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to RC. Slowly increase the
value of RC while observing the transient performance on an
oscilloscope until no further improvement is noted. Normally,
CC will not need adjustment. Keep the value of CC from
Equation 34 unless some performance issue is noted.
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will initially
deviate by an amount approximated by the voltage drop across
the ESL. As the load current increases, the voltage drop across
the ESR increases linearly until the load current reaches its final
value. The capacitors selected must have sufficiently low ESL
and ESR so that the total output-voltage deviation is less than
the allowable maximum. Neglecting the contribution of inductor
current and regulator response, the output voltage initially
deviates by an amount, as shown in Equation 35:
di
V   ESL  ----- +  ESR  I
dt
(EQ. 35)
The filter capacitor must have sufficiently low ESL and ESR
so that V < VMAX.
Most capacitor solutions rely on a mixture of high-frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
The ESR of the bulk capacitors also creates the majority of
the output-voltage ripple. As the bulk capacitors sink and
source the inductor AC ripple current (see “Interleaving” on
page 12 and Equation 2), a voltage develops across the
bulk-capacitor ESR equal to IC,PP (ESR). Thus, once the
output capacitors are selected, the maximum allowable
ripple voltage, VPP(MAX), determines the lower limit on the
inductance, as shown in Equation 36.
V – N V

OUT  V OUT
 IN
L  ESR  ---------------------------------------------------------------f S  V IN  V
(EQ. 36)
P-P MAX 
27
FN6689.3
May 5, 2016
ISL6334B, ISL6334C
Equation 37 gives the upper limit on L for the cases when
the trailing edge of the current transient causes a greater
output-voltage deviation than the leading edge. Equation 38
addresses the leading edge. Normally, the trailing edge
dictates the selection of L because duty cycles are usually
less than 50%. Nevertheless, both inequalities should be
evaluated, and L should be selected based on the lower of
the two results. In each equation, L is the per-channel
inductance, C is the total output capacitance, and N is the
number of active channels.
1.25  N  C- V


L  ---------------------------MAX – I  ESR  V IN – V O
 I  2
0.2
0.1
IL(P-P) = 0
IL(P-P) = 0.5 IO
IL(P-P) = 0.75 IO
0
0
0.3
(EQ. 37)
(EQ. 38)
Switching Frequency Selection
There are a number of variables to consider when choosing
the switching frequency, as there are considerable effects on
the upper-MOSFET loss calculation. These effects are
outlined in “MOSFETs” on page 25, and they establish the
upper limit for the switching frequency. The lower limit is
established by the requirement for fast transient response
and small output-voltage ripple as outlined in “Output Filter
Design” on page 27. Choose the lowest switching frequency
that allows the regulator to meet the transient-response
requirements.
Input Capacitor Selection
The input capacitors are responsible for sourcing the AC
component of the input current flowing into the upper
MOSFETs. Their RMS current capacity must be sufficient to
handle the AC component of the current drawn by the upper
MOSFETs which is related to duty cycle and the number of
active phases.
0.2
0.4
0.6
DUTY CYCLE (VO/VIN)
0.8
1.0
FIGURE 18. NORMALIZED INPUT-CAPACITOR RMS CURRENT
vs DUTY CYCLE FOR 2-PHASE CONVERTER
INPUT-CAPACITOR CURRENT (IRMS/IO)
2  N  C  VO
L  --------------------------------- V MAX – I  ESR
 I  2
0.3
INPUT-CAPACITOR CURRENT (IRMS/IO)
Since the capacitors are supplying a decreasing portion of
the load current while the regulator recovers from the
transient, the capacitor voltage becomes slightly depleted.
The output inductors must be capable of assuming the entire
load current before the output voltage decreases more than
VMAX. This places an upper limit on inductance.
IL(P-P) = 0
IL(P-P) = 0.5 IO
IL(P-P) = 0.25 IO
IL(P-P) = 0.75 IO
0.2
0.1
0
0
0.2
0.4
0.6
DUTY CYCLE (VO/VIN)
0.8
1.0
FIGURE 19. NORMALIZED INPUT-CAPACITOR RMS CURRENT
vs DUTY CYCLE FOR 3-PHASE CONVERTER
For a 2-phase design, use Figure 18 to determine the input
capacitor RMS current requirement given the duty cycle,
maximum sustained output current (IO), and the ratio of the
per-phase peak-to-peak inductor current (IL(P-P)) to IO.
Select a bulk capacitor with a ripple current rating which will
minimize the total number of input capacitors required to
support the RMS current calculated. The voltage rating of
the capacitors should also be at least 1.25x greater than the
maximum input voltage.
Figures 19 and 20 provide the same input RMS current
information for 3- and 4-phase designs respectively. Use the
same approach to selecting the bulk capacitor type and
number as previously described.
Low capacitance, high-frequency ceramic capacitors are
needed in addition to the bulk capacitors to suppress leading
and falling edge voltage spikes. The result from the high
current slew rates produced by the upper MOSFETs turn on
and off. Select low ESL ceramic capacitors and place one as
close as possible to each upper MOSFET drain to minimize
board parasitic impedances and maximize suppression.
28
FN6689.3
May 5, 2016
ISL6334B, ISL6334C
INPUT-CAPACITOR CURRENT (IRMS/IO)
0.3
IL(P-P) = 0
IL(P-P) = 0.25 IO
Component Placement
IL(P-P) = 0.5 IO
IL(P-P) = 0.75 IO
0.2
0.1
0
0
0.2
0.4
0.6
DUTY CYCLE (VO/VIN)
0.8
1.0
FIGURE 20. NORMALIZED INPUT-CAPACITOR RMS CURRENT
vs DUTY CYCLE FOR 4-PHASE CONVERTER
INPUT-CAPACITOR CURRENT (IRMS/IO)
0.6
0.4
Within the allotted implementation area, orient the switching
components first. The switching components are the most
critical because they carry large amounts of energy and tend
to generate high levels of noise. Switching component
placement should take into account power dissipation. Align
the output inductors and MOSFETs such that space between
the components is minimized while creating the PHASE
plane. Place the Intersil MOSFET driver IC as close as
possible to the MOSFETs they control to reduce the parasitic
impedances due to trace length between critical driver input
and output signals. If possible, duplicate the same placement
of these components for each phase.
Next, place the input and output capacitors. Position one highfrequency ceramic input capacitor next to each upper
MOSFET drain. Place the bulk input capacitors as close to the
upper MOSFET drains as dictated by the component size and
dimensions. Long distances between input capacitors and
MOSFET drains result in too much trace inductance and a
reduction in capacitor performance. Locate the output
capacitors between the inductors and the load, while keeping
them in close proximity to the microprocessor socket.
Voltage-Regulator (VR) Design Materials
0.2
IL(P-P) = 0
IL(P-P) = 0.5 IO
IL(P-P) = 0.75 IO
0
0
0.2
0.4
0.6
DUTY CYCLE (VO/VIN)
0.8
1.0
FIGURE 21. NORMALIZED INPUT-CAPACITOR RMS
CURRENT vs DUTY CYCLE FOR SINGLE-PHASE
CONVERTER
MULTIPHASE RMS IMPROVEMENT
The tolerance band calculation (TOB) worksheets for VR
output regulation and IMON have been developed using the
Root-Sum-Squared (RSS) method with 3 sigma distribution
point of the related components and parameters. Note that
the “Electrical Specifications” table beginning on page 8
specifies no less than 6 sigma distribution point, not suitable
for RSS TOB calculation. Intersil also developed a set of
worksheets to support VR design and layout. Contact
Intersil’s local office or field support for the latest available
information.
Figure 21 is provided as a reference to demonstrate the
dramatic reductions in input-capacitor RMS current upon the
implementation of the multiphase topology. For example,
compare the input RMS current requirements of a 2-phase
converter versus that of a single phase. Assume both
converters have a duty cycle of 0.25, maximum sustained
output current of 40A, and a ratio of IL(P-P) to IO of 0.5. The
single phase converter would require 17.3ARMS current
capacity while the two-phase converter would only require
10.9ARMS. The advantages become even more pronounced
when output current is increased and additional phases are
added to keep the component cost down relative to the
single phase approach.
Layout Considerations
The following layout strategies are intended to minimize the
impact of board parasitic impedances on converter
performance and to optimize the heat-dissipating capabilities
of the printed-circuit board. These sections highlight some
important practices which should not be overlooked during the
layout process.
29
FN6689.3
May 5, 2016
ISL6334B, ISL6334C
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE
REVISION
CHANGE
May 5, 2016
FN6689.3
Added Revision History and About Intersil sections.
Removed ISL6622B and ISL6610A from the Controller and Driver Recommendation table.
Updated Electrical Spec Table on page 8 as follows:
-EN_PWR Rising Threshold
From: 0.875 (min) 0.897 (typ) 0.920 V (max)
To: 0.830 (min) 0.850 (typ) 0.870 V (max)
-EN_VTT Rising Threshold
From: 0.875 (min) 0.897 (typ) 0.920 V (max)
To: 0.830 (min) 0.850 (typ) 0.870 V (max)
Changed 0.875 to 0.870 in the EN_PWR and EN_VTT Electrical Spec table on page 8 and pin descriptions
on page 11, “ISL6334B and ISL6334C Block Diagram” on page 4, and in Figure 8 on page 20.
Changed 0.745V to 0.735V in the EN_PWR and EN_VTT pin descriptions on page 11.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
30
FN6689.3
May 5, 2016
ISL6334B, ISL6334C
Package Outline Drawing
L40.6x6
40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 3, 10/06
4X 4.5
6.00
36X 0.50
A
B
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
40
31
30
1
6.00
4 . 10 ± 0 . 15
21
10
0.15
(4X)
11
20
TOP VIEW
0.10 M C A B
40X 0 . 4 ± 0 . 1
4 0 . 23 +0 . 07 / -0 . 05
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0 . 90 ± 0 . 1
(
C
BASE PLANE
( 5 . 8 TYP )
SEATING PLANE
0.08 C
SIDE VIEW
4 . 10 )
( 36X 0 . 5 )
C
0 . 2 REF
5
( 40X 0 . 23 )
0 . 00 MIN.
0 . 05 MAX.
( 40X 0 . 6 )
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
31
FN6689.3
May 5, 2016
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