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November 16, 2004
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1-888-I
HIP1011A
FN4631.5
PCI Hot Plug Controller
Features
The HIP1011A is the second PCI Hot Plug Voltage bus
control IC from Intersil. A drop-in alternative to the widely
used HIP1011, the HIP1011A has the same form, fit and
function but additionally features an adjustable latch-off time
of the MOSFET switches and fault reporting.
• Adjustable Delay Time for Turn-Off and Fault Reporting
Like the HIP1011, the HIP1011A creates a small and simple
yet complete power control solution with discrete power
MOSFETs and a few passive components. Four
independent supplies are controlled, +5V, +3.3, +12V, and
-12V. The +12V and -12V switches are integrated. For the
+5V and +3.3V supplies, overcurrent (OC) protection is
provided by sensing the voltage across external currentsense resistors. For the +12V and -12V supplies OC
protection is provided internally. In addition, an on-chip
reference is used to monitor the +5V, +3.3V and +12V
outputs for undervoltage (UV) conditions. The PWRON input
controls the state of the switches. During an OC condition on
any output, or a UV condition on the +5V, +3.3V or +12V
outputs, a LOW (0V) is asserted on the FLTN output and all
MOSFETs are latched-off. The time to FLTN signal going
LOW and MOSFET latch-off is determined by a single
capacitor from the FLTN pin to ground. This added feature
allows the system OS to complete housekeeping activities in
preparation for an unplanned shut down of the affected card.
The FLTN latch is cleared when the PWRON input is toggled
low again. During initial power-up of the main VCC supply
(+12V), the PWRON input is inhibited from turning on the
switches, and the latch is held in the Reset state until the
VCC input is greater than 10V.
• Adjustable Overcurrent Protection for All Supplies
User programmability of the overcurrent threshold, fault
reporting response time, latch-off response time and turn-on
slew rate is provided. A resistor connected to the OCSET pin
programs the OC threshold. A capacitor may be added to
the FLTN pin to adjust both the delay time to reporting a fault
and the latch-off of the supplies after an OC or UV event.
Capacitors connected to the gate pins set the turn-on rate. In
addition the HIP1011A has also been enhanced to tolerate
spurious system noise.
1
• Controls All PCI Supplies: +5V, +3.3V, +12V, -12V
• Internal MOSFET Switches for +12V and -12V Outputs
• P Interface for On/Off Control and Fault Reporting
• Provides Fault Isolation
• Adjustable Turn-On Slew Rate
• Minimum Parts Count Solution
• No Charge Pump
• Pb-Free Available (RoHS Compliant)
Applications
• PCI Hot Plug
• CompactPCI
Ordering Information
PART NUMBER
TEMP. RANGE
(oC)
PACKAGE
PKG.
DWG. #
HIP1011ACB
0 to 70
16 Ld SOIC
M16.15
HIP1011ACBZA
(See Note)
0 to 70
16 Ld SOIC
(Pb-free)
M16.15
HIP1011ACB-T
0 to 70
Tape and Reel
HIP1011ACBZA-T
(See Note)
0 to 70
Tape and Reel (Pb-free)
NOTE: Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with
both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020C.
Pinout
HIP1011A
(SOIC)
TOP VIEW
M12VIN
1
16 M12VO
FLTN
2
15 M12VG
3V5VG
3
14 12VG
VCC
4
13 GND
12VIN
5
12 12VO
3VISEN
6
11 5VISEN
3VS
7
10 5VS
OCSET
8
9
PWRON
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2000, 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HIP1011A
Typical Application
3.3V,
7.6A OUT
12V,
0.5A OUT
-12V,
0.1A OUT
5V,
5A OUT
5m, 1%
3.3V INPUT
5V INPUT
5m, 1%
ITF86130SK8T
ITF86130SK8T
HIP1011A
-12V INPUT
M12VIN
FLTN
3V5VG
VCC
12VIN
3VISEN
3VS
OCSET
12V INPUT
6.04k
1%
0.033F
M12VO
M12VG
12VG
GND
12VO
5VISEN
5VS
PWRON
0.033F
0.033F
(OPTIONAL)
POWER CONTROL INPUT
NOTE: All capacitors are10%.
FAULT OUTPUT (ACTIVE LOW)
Simplified Schematic
5VREF
SET (LOW = FAULT)
FAULT LATCH
LOW = FAULT
COMP
FLTN
+ 4.6V
INHIBIT
COMP
RESET
VCC
VCC
+ 2.9V
INHIBIT
VCC
+ 10.8V
INHIBIT
+
VOCSET/17
COMP
-
5V ZENER
REFERENCE
COMP
5VREF
+
-
5VS
VCC
VCC
3V5VG
COMP
VCC
+
5VISEN
3VS
+
+
VOCSET
VOCSET/0.8
0.3
OCSET
3VISEN
12VIN
VCC
-
100A
-
VOCSET/13.3
COMP
+
12VIN
POWER-ON
RESET
LOW WHEN VCC < 10V
12VG
HIGH = FAULT
VCC
12VO
HIGH = SWITCHES ON
COMP
+
0.7
VOCSET/3.3
M12VIN
+
PWRON
M12VG
GND
M12VIN
M12VO
2
FN4631.5
November 16, 2004
HIP1011A
Pin Descriptions
PIN NO.
DESIGNATOR
FUNCTION
1
M12VIN
-12V Input
2
FLTN
Fault Output
5V CMOS Fault Output; LOW = FAULT. A capacitor may be placed from this pin to ground
to provide delay time to fault notification and power supply latch-off.
3
3V5VG
3.3V/5V Gate Output
Drive the gates of the 3.3V and 5V MOSFETs. Connect a capacitor to ground to set the startup ramp. During turn on, this capacitor is charged with a 25A current source.
4
VCC
12V VCC Input
5
12VIN
12V Input
6
3VISEN
3.3V Current Sense
Connect to the load side of the current sense resistor in series with source of external 3.3V
MOSFET.
7
3VS
3.3V Source
Connect to source of 3.3V MOSFET. This connection along with pin 6 (3VISEN) senses the
voltage drop across the sense resistor.
8
OCSET
Overcurrent Set
Connect a resistor from this pin to ground to set the overcurrent trip point of all four switches.
All four over current trips can be programmed by changing the value of this resistor. The
default (6.04k1%) is compatible with the maximum allowable currents as outlined in the
PCI specification.
9
PWRON
Power On Control
10
5VS
5V Source
Connect to source of 5V MOSFET switch. This connection along with pin 11 (5VISEN)
senses the voltage drop across the sense resistor.
11
5VISEN
5V Current Sense
Connect to the load side of the current sense resistor in series with source of external 5V
MOSFET.
12
12VO
Switched 12V Output
13
GND
Ground
14
12VG
Gate of Internal PMOS Connect a capacitor between 12VG and 12VO to set the start up ramp for the +12V supply.
This capacitor is charged with a 25A current source during start-up. The UV circuitry is
enabled after the voltage on 12VG is less than 400mV. Therefore, if the capacitor on the pin
3 (3V5VG) is more than 25% larger than the capacitor on pin 14 (12VG) a false UV may be
detected during start up.
15
M12VG
Gate of Internal NMOS Connect a capacitor between M12VG and M12VO to set the start up ramp for the M12V
supply. This capacitor is charged with 25A during start up.
16
M12VO
Switched -12V
Output
3
DESCRIPTION
-12V Supply Input. Also provides power to the -12V overcurrent circuitry.
Connect to unswitched 12V supply.
Switched 12V supply input.
Controls all four switches. High to turn switches ON, Low to turn them OFF.
Switched 12V output.
Connect to common of power supplies.
Switched 12V Output.
FN4631.5
November 16, 2004
HIP1011A
Absolute Maximum Ratings
Thermal Information
VCC, 12VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +14.0V
12VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to V12VIN +0.5V
12VO, 12VG, 3V5VG . . . . . . . . . . . . . . . . . . . . . -0.5V to VCC +0.5V
M12VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15.0V to +0.5V
M12VO, M12VG. . . . . . . . . . . . . . . . . . . . . . VM12VIN-0.5V to +0.5V
3VISEN, 5VISEN . . . . . . . . . . . -0.5V to the Lesser of VCC or +7.0V
Voltage, Any Other Pin. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
12VO Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3A
M12VO Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8A
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4KeV (HBM)
Thermal Resistance (Typical, Note 1)
JA (oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
105
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .125oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
Die Characteristics
Number of Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Operating Conditions
VCC Supply Voltage Range. . . . . . . . . . . . . . . . . . +10.8V to +13.2V
12V, 5V and 3.3V Input Supply Tolerances 10%
12VO Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to +0.5A
M12VO Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to +0.1A
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief 379 for details.
2. All voltages are relative to GND, unless otherwise specified.
Electrical Specifications
Nominal 5.0V and 3.3V Input Supply Voltages, 
VCC = 12VIN = 12V, M12VIN = -12V, TA = TJ = 0 to 70oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
7.1
-
A
5V / 3.3V SUPPLY CONTROL
5V Overcurrent Threshold
IOC5V
See Typical Application Diagram
5V Overcurrent Threshold Voltage
VOC5V_1
VOCSET = 0.6V
30
36
42
mV
5V Overcurrent Threshold Voltage
VOC5V_2
VOCSET = 1.2V
66
72
79
mV
5V Undervoltage Trip Threshold
V5VUV
4.42
4.65
4.75
V
5V Undervoltage Fault Response Time
t5VUV
-
150
350
ns
5V Turn-On Time
(PWRON High to 5VOUT = 4.75V)
tON5V
C3V5VG = 0.022F, C5VOUT = 2000F,
RL = 1
-
6.5
-
ms
5VS Input Bias Current
IB5VS
PWRON = High
-40
-26
-20
A
5VISEN Input Bias Current
IB5VISEN
PWRON = High
-160
-140
-110
A
3V Overcurrent Threshold
IOC3V
-
9.0
-
A
See Typical Application Diagram
3V Overcurrent Threshold Voltage
VOC3V_1
VOCSET = 0.6V
42
49
56
mV
3V Overcurrent Threshold Voltage
VOC3V_2
VOCSET = 1.2V
88
95
102
mV
3V Undervoltage Trip Threshold
V3VUV
2.74
2.86
2.97
V
3V Undervoltage Fault Response Time
t3VUV
-
150
350
ns
3V Turn-On Time
(PWRON High to 3VOUT = 3.00V)
tON3V
C3V5VG = 0.022F, C3VOUT = 2000F,
RL = 0.43
-
6.5
-
ms
3VS Input Bias Current
IB3VS
PWRON = High
-40
-26
-20
A
IB3VISEN
PWRON = High
-160
-140
-110
A
3VISEN Input Bias Current
3V5VG Vout Low
Vout_lo_35VG
PWRON = Low, FLTN = Low
-
0.1
0.4
V
3V5VG Vout High
Vout_hi_35VG
PWRON = High, FLTN = High
10.5
11.1
-
V
IC3V5VG
PWRON = High, V3V5VG = 2V
22.5
25.0
27.5
A
Gate Output Charge Current
4
FN4631.5
November 16, 2004
HIP1011A
Electrical Specifications
Nominal 5.0V and 3.3V Input Supply Voltages, 
VCC = 12VIN = 12V, M12VIN = -12V, TA = TJ = 0 to 70oC, Unless Otherwise Specified (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Gate Turn-On Time
(PWRON High to 3V5VG = 11V)
tON3V5V
C3V5VG = 0.1F
-
280
500
s
Gate Turn-Off Time
tOFF3V5V
C3V5VG = 0.1F, 3V5VG from 9.5V to 1V
-
13
17
s
C3V5VG = 0.022F, 3V5VG Falling 90% to
10%
-
2
-
s
Gate Turn-Off Time
+12V SUPPLY CONTROL
On Resistance of Internal PMOS
rDS(ON)12
PWRON = High, ID = 0.5A,
TA = TJ = 25oC
0.18
0.3
0.35

Overcurrent Threshold
IOC12V_1
VOCSET = 0.6V
0.6
0.75
0.9
A
Overcurrent Threshold
IOC12V_2
VOCSET = 1.2V
1.25
1.50
1.8
A
12V Undervoltage Trip Threshold
V12VUV
10.5
10.8
11.15
V
Undervoltage Fault Response Time
t12VUV
-
150
-
ns
Gate Charge Current
IC12VG
PWRON = High, V12VG = 3V
23.5
25.0
28.5
A
Turn-On Time
(PWRON High to 12VG = 1V)
tON12V
C12VG = 0.022F
-
16
20
ms
Turn-Off Time
tOFF12V
C12VG = 0.1F, 12VG
-
9
12
s
C12VG = 0.022F, 12VG Rising
10% - 90%
-
3
-
s
PWRON = High, ID = 0.1A,
TA = TJ = 25oC
0.5
0.7
0.9

Turn-Off Time
-12V SUPPLY CONTROL
On Resistance of Internal NMOS
rDS(ON)M12
Overcurrent Threshold
IOC12V_1
VOCSET = 0.6V
0.15
0.18
0.25
A
Overcurrent Threshold
IOC12V_2
VOCSET = 1.2V
0.30
0.37
0.50
A
Gate Output Charge Current
ICM12VG
PWRON = High, V3VG = -4V
22.5
25
27.5
A
Turn-On Time 
(PWRON High to M12VG = -1V)
tONM12V
CM12VG = 0.022F
-
160
300
s
Turn-On Time 
(PWRON High to M12VO = -10.8V)
tONM12V
CM12VG = 0.022F, CM12VO = 50F,
RL = 120
-
16
-
ms
Turn-Off Time
tOFFM12V
CM12VG = 0.1F, M12VG
-
18
23
s
CM12VG = 0.022F, M12VG Falling 90%
to 10%
-
3
-
s
PWRON = High
-
2
2.6
mA
Turn-Off Time
M12VIN Input Bias Current
IBM12VIN
CONTROL I/O PINS
Supply Current
IVCC
4
5
5.8
mA
OCSET Current
IOCSET
95
100
105
A
FLTN Cap = 100pF
-
500
960
ns
Overcurrent to Fault Response Time
FLTN Cap = 1000pF
-
2200
-
ns
Overcurrent to Fault Response Time
FLTN Cap = 10F
-
30
-
s
0.8
1.6
2.1
V
-
0.6
0.9
V
3.9
4.3
4.9
V
1.45
1.8
2.25
V
9.4
10
10.6
V
Overcurrent to Fault Response Time
PWRON Threshold Voltage
tOC
VTHPWRON
FLTN Output Low Voltage
VFLTN,OL
IFLTN = 2mA
FLTN Output High Voltage
VFLTN,OH
IFLTN = 0 to -4mA
FLTN Output Latch Threshold
VFLTN,TH
12V Power On Reset Threshold
VPOR,TH
5
VCC Voltage Falling
FN4631.5
November 16, 2004
HIP1011A
Typical Performance Curves
1000
320
900
4.632
2.862
300
800
PMOS +12 rON
280
700
5 UV
2.861
4.630
5V UVTRIP (V)
NMOS -12 rON
NMOS rON -12 (m)
PMOS rON +12 (m)
4.631
2.860
4.629
3.3 UV
4.628
3.3V UVTRIP (V)
340
2.859
4.627
260
0
5
600
10 15 20 25 30 35 40 45 50 55 60 65 70
4.626
2.858
5 10 15 20 25 30 35 40 45 50 55 60 65 70
0
TEMPERATURE (oC)
TEMPERATURE (oC)
FIGURE 1. rON vs TEMPERATURE
FIGURE 2. UV TRIP vs TEMPERATURE
10.84
100
OC Vth (mV)
10.82
3V OCVth
80
5V OCVth
70
10.81
60
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70
0
5
10
15
20
TEMPERATURE (oC)
25
30
35
40
45
50
55
60
65
70
TEMPERATURE (oC)
FIGURE 3. 12 UV TRIP vs TEMPERATURE
FIGURE 4. OC Vth vs TEMPERATURE (VROCSET = 1.21V)
102
101
IOC SET (mA)
12 UV TRIP (V)
90
10.83
100
99
98
0
5
10 15
20
25
30
35
40
45
50
55
60
65
70
TEMPERATURE (oC)
FIGURE 5. OCSET I vs TEMPERATURE
6
FN4631.5
November 16, 2004
HIP1011A
Typical Performance Curves
(Continued)
3V5VG
3V5VG
FLTN
FLTN
FLTN
5V Iout
5V Iout
VOLTAGE (2V / DIV)
CURRENT (5A / DIV)
TIME (1s /DIV)
FIGURE 6. FLTN, 3V5VG RESPONSE TO OC, FLTN = 100pF
VOLTAGE (2V / DIV)
CURRENT (5A / DIV)
TIME (1s /DIV)
FIGURE 7. FLTN, 3V5VG RESPONSE TO OC, FLTN CAP = 0.001F
3V5VG
3V5VG
5V Iout
5V Iout
FLTN
FLTN
VOLTAGE (2V / DIV)
TIME (2s /DIV)
CURRENT (5A / DIV)
FIGURE 8. FLTN, 3V5VG RESPONSE TO OC, FLTN CAP = 0.01F
VOLTAGE (2V / DIV)
CURRENT (5A / DIV)
TIME (50s /DIV)
FIGURE 9. FLTN, 3V5VG RESPONSE TO OC, FLTN CAP = 1F
10ms
1ms
VG
100s
10s
1s
100ns
10ns
1ns
100pF
0.001F
0.01F
0.1F
1F
10F
FIGURE 10. RESPONSE TIME vs FLTN CAP
7
FN4631.5
November 16, 2004
HIP1011A
(indicating a fault has occurred) and the start of the gate
drive outputs latching off. The latch-off is initiated by the
falling FLTN signal reaching the output latch threshold
voltage, VFLTN, TH. Table 1 illustrates the effect of the FLTN
capacitor on the response time.
HIP1011A PCI Hot Plug Controller
Key Feature Description and Operation
A drop-in alternative to the widely used HIP1011, the
HIP1011A additionally features an adjustable delay time to
fault reporting and latch-off of the MOSFET switches. During
an over current condition (OC) on any output, or an under
voltage (UV) condition on the +5V, +3.3V or +12V outputs, a
LOW (0V) is presented on the FLTN output and all
MOSFETs are latched-off. A programmable delay time from
an OC or UV event to the FLTN signal going LOW and
MOSFET latch-off can be designed into the system by a
single capacitor from the FLTN pin to ground. The addition of
an increasingly larger capacitor value on the FLTN pin
increases the time from the OC or UV occurrence to the start
of the FLTN high to low transition. The capacitor also slows
the falling ramp thus delaying reaching the FLTN latch
threshold of ~2.4V. Once the FLTN latch voltage threshold is
reached the HIP1011A then simultaneously shuts down all
four supplies. This added feature enables the HIP1011A to
ignore both transient UV and OC events to the extent of a
single capacitor value in the system design. This feature also
may allow the system OS to complete housekeeping
activities in preparation for a possible unplanned shutdown
of the affected card by receiving an early warning signal from
the HIP1011A.
TABLE 1. RESPONSE TIME TABLE
0.001F
0.1F
10F
0.85s
37s
3.8ms
3V5VG Response a
VFLTN, TH
FLTN
a
3V5VG
T1
T2
FIGURE 12. TIMING DIAGRAM
CAN THE HIP1011A BE USED ON A CompactPCI
BOARD?
Customizing and Optimizing Circuit Performance
and Functionality
Yes, the HIP1011A can be used on a CompactPCI card
application. See Technical Brief TB358.
HOW ADJUSTABLE IS THE FAULT REPORTING DELAY
AND TIME TO POWER SUPPLY LATCH-OFF?
Figure 12 illustrates the relationship between the FLTN
signal and the gate drive outputs. Duration a, indicates the
time between FLTN starting to transition from High to Low,
3.3V
7.6A OUT
3.3V INPUT
12V
0.5A OUT
-12V
0.1A OUT
5V
5A OUT
5m 1%
5m 1%
HIP1011A
-12V INPUT
M12VIN
FLTN
3V5VG
VCC
12VIN
3VISEN
3VS
OCSET
12V INPUT
6.04k
1%
M12VO
M12VG
12VG
GND
12VO
5VISEN
5VS
PWRON
5V INPUT
0.033F
0.033F
0.033F
(SEE TABLE 1)
POWER CONTROL INPUT
NOTE:
FAULT OUTPUT (ACTIVE LOW)
3. All capacitors are ±10%.
FIGURE 11. HIP1011A TYPICAL APPLICATION
8
FN4631.5
November 16, 2004
HIP1011A
ARE THERE PCB LAYOUT DESIGN BEST PRACTICES
TO FOLLOW? WHAT ARE THEY?
As with most innovative ICs performing critical tasks there
are crucial PCB layout best practices to follow for optimal
performance. PCB traces that connect each end of the
current sense resistors to the HIP1011A must not carry any
load current. This can be accomplished by two dedicated
PCB traces directly from the sense resistor to the HIP1011A,
see examples of correct and incorrect layouts in Figure 13.
inch SOICs. The typical application requires only 1.1 square
inches of PCB board space.
0.75in
1.5in
FIGURE 14. LAYOUT PLOT, ACTUAL SIZE (0.75in x 1.5in)
CORRECT
TO HIP1011A
VS AND VISEN
INCORRECT
TO HIP1011A
VS AND VISEN
CURRENT
SENSE RESISTOR
FIGURE 13. SENSE RESISTOR LAYOUT
IS THERE A HIP1011A PCI HOT PLUG EVALUATION
BOARD AVAILABLE?
There is an evaluation board available through your local
Intersil sales office. The HIP1011AEVAL1 board (Figure 15)
is a simple board designed to demonstrate and evaluate the
HIP1011A using an external PWRON signal simulating a
PCI Hot Plug environment. The HIP1011AEVAL1 board
comes in 2 parts, the mother board with the HIP1011A,
MOSFETs with external components and a load board
simulating a ‘typical’ PCI load with adequate space for
modifying the existing load or to add an electronic load. Even
with a number of available test points the HIP1011A
implementation space is still very efficient. In addition, the
demo board offers adequate space to evaluate the
application note discussions found in AN9737.
Typical Applications: HIP1011A PCI Hot
Plug Controller
Introduction to HIP1011A and PCI Hot Plug
Evaluation Board
The HIP1011A is compatible with the PCI Hot Plug
specification as it is derived from the widely used HIP1011.
This device facilitates “HOT PLUGGING”, the removal or
insertion of PCI compliant cards without the need to power
down the server voltage bus. The HIP1011A controls all four,
-12V, +12V, +3.3V, +5V supplies found in PCI applications,
monitoring and protecting all against over current (OC) and
the +12V, +3.3V, +5V for under voltage (UV) conditions.
Reference the PCI Hot Plug specification available from
www.pcisig.com.
Figure 14 illustrates the PCB pattern for implementation of
the HIP1011A with 4 power MOSFETs. Additional
components for optimizing performance in particular
applications, ambient electrical noise levels or desired
features will be necessary. The ease of implementation of
the HIP1011A and MOSFETs is complemented by the small
PCB foot print necessary, since both are available in 0.150
9
FN4631.5
November 16, 2004
HIP1011A
BUS BOARD
2 TP6
1 TP7
3, 4, 5 TP8
TP4
3.3VOUT
12VOUT
9, 11, 12 TP5
R2
3.3V INPUT
7, 8, 10 TP9
TP11
5VOUT
-12VOUT
LOAD BOARD
GND
5V INPUT
R1
RL1
3.3V
Q1, Q2
Q3, Q4
TP1
HIP1011A
M12VIN M12VO
FLTN
M12VG
3V5VG
12VG
VCC
GND
12VO
12VIN
3VISEN 5VISEN
5VS
3VS
OCSET PWRON
-12V INPUT
VCC
TP2
12V INPUT TP3
JP1
CL1
RL2
C3
5.0V
C1
CL2
C2
RL3
+12V
CL3
R3
RL4
R4
-12V
C4
INDICATES BANANA JACKS
D1
CL4
INDICATES EDGE CONNECTOR CARD
6
JP2
5V
INDICATES EDGE CONNECTOR SOCKET
TP10
PWRON IN
FIGURE 15. HIP1011AEVAL1
Table 2 details the BOM for the HIP1011AEVAL1 board.
TABLE 2.
COMPONENT
DESIGNATOR
U1
Q1, Q2, Q3, Q4
R1, R2
C1, C2, C3
COMPONENT NAME
COMPONENT DESCRIPTION
HIP1011ACB PCI Hot Plug Controller
Intersil Corporation, HIP1011ACB PCI Hot Plug Controller
RF1K49211
Intersil Corporation, RF1K49211 7A, 12V, 20m, Logic Level
N-Channel MOSFET
RSENSE for 3.3V and 5V Supplies
Dale, WSL-2512 10m Metal Strip Resistor
Gate Timing Capacitors
0.033F 805 Chip Capacitor
R3
Over Current Set Resistor
12.1k 805 Chip Resistor
C4
Fault Stability Capacitor
100pF 805 Chip Cap
Conn. 1
Connector for Load Card
Sullins EZM06DRXH
R4
LED Series Resistor
4.7k 805 Chip Resistor
D1
Fault Indicating LED
Red LED
JP1
VCC to Switched or Unswitched 12V Supply
0.01” Spaced Pins for Jumper Block
JP2
PWRON to 5V
0.01” Spaced Pins for Jumper Block
RL1
3.3V Load Board Resistor
1.1 , 10W
RL2
5.0V Load Board Resistor
2.5 , 10W
RL3
+12V Load Board Resistor
47 , 5W
RL4
-12V Load Board Resistor
240 , 2W
CL1, CL2
+3.3V and +5.0V Load Board Capacitor
2200F
CL3, CL4
+12V and -12V Load Board Capacitor
100F
10
FN4631.5
November 16, 2004
HIP1011A
M16.15 (JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Small Outline Plastic Packages (SOIC)
N
INCHES
INDEX
AREA
H
0.25(0.010) M
B M
SYMBOL
E
-B-
1
2
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
e
B
0.25(0.010) M
C
0.10(0.004)
C A M
B S
MILLIMETERS
MAX
MIN
MAX
NOTES
A
0.053
0.069
1.35
1.75
-
A1
0.004
0.010
0.10
0.25
-
B
0.014
0.019
0.35
0.49
9
C
0.007
0.010
0.19
0.25
-
D
0.386
0.394
9.80
10.00
3
E
0.150
0.157
3.80
4.00
4
e
µ
A1
MIN
0.050 BSC
1.27 BSC
-
H
0.228
0.244
5.80
6.20
-
h
0.010
0.020
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
8o
0o
N

16
0o
16
7
8o
Rev. 1 02/02
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
11
FN4631.5
November 16, 2004
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