DATASHEET

HIP1011D, HIP1011E
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FN4725.5
Dual Slot PCI Hot Plug Controllers
Features
The HIP1011D, HIP1011E are the first ICs available for
independent control of two PCI Hot-Plug slots. The
HIP1011D has all the features and functionality of two single
PCI Hot-Plug slot controllers such as the HIP1011A but in
the same foot print area. Like the single slot HIP1011B, the
HIP1011E does not monitor output voltage nor respond to
undervoltage conditions.
• Independent Power Control of 2 PCI Slots
The HIP1011D, HIP1011E are designed to be physically
placed in close proximity to two adjacent PCI slots thus
reducing layout complexity and placement costs in
assembly. The HIP1011D, HIP1011E provides independent
power control to each slot and the addition of discrete power
MOSFETs and a few passive components creates two
complete power control solutions. The IC integrates the
+12V and -12V current sensing switches for each slot.
Overcurrent (OC) protection is provided by sensing the
voltage across external current-sense resistors. In addition,
on-chip references are used to monitor the +5V, +3.3V and
+12V outputs for undervoltage (UV) conditions *. The two
PWRON inputs control the state of the switches, one each
for slot A and slot B outputs. During an OC condition on any
output, or a UV condition on the +5V, +3.3V or +12V outputs
*, a LOW (0V) is asserted on the associated FLTN output
and all associated switches are latched-off. The outputs
servicing the adjacent slot are unaffected.
• Adjustable Turn-On Slew Rate
The time to FLTN signal going LOW and MOSFET latch off
is user determined by a single capacitor from each FLTN pin
to ground. This added feature enables the HIP1011D,
HIP1011E to ignore system noise transients. The FLTN latch
is cleared when the PWRON input is toggled low again.
During initial power-up of the main VCC supply (+12V), the
PWRON input is inhibited from turning on the switches, and
the latch is held in the Reset state until the VCC input is
greater than 10V.
User programmability of the overcurrent threshold and turnon slew rate is provided. A resistor connected to the OCSET
pin programs the overcurrent threshold for both slots.
Capacitors connected to the gate pins set the turn-on rate.
* UV references do not apply to HIP1011E.
• Turn-Off Delay Time Adjustability
• Internal MOSFET Switches for +12V and -12V Outputs
• P Interface for On/Off Control and Fault Reporting
• Adjustable Overcurrent Protection for All Eight Supplies
• Provides Fault Isolation
• Minimum Parts Count Solution
• No Charge Pump
• 100ns Response Time to Overcurrent
• Pb-Free Available (RoHS Compliant)
Applications
• PCI Hot-Plug
Ordering Information
PART NUMBER
TEMP.
RANGE (°C)
HIP1011DCA*
0 to 70
28 Ld SSOP
M28.15
HIP1011DCAZA*
(See Note)
0 to 70
28 Ld SSOP
(Pb-free)
M28.15
HIP1011ECA*
0 to 70
28 Ld SSOP
M28.15
HIP1011ECAZA*
(See Note)
0 to 70
28 Ld SSOP
(Pb-free)
M28.15
* Add “-T” suffix for tape and reel option.
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding
compounds/die attach materials and 100% matte tin plate termination finish,
which are RoHS compliant and compatible with both SnPb and Pb-free
soldering operations. Intersil Pb-free products are MSL classified at Pb-free
peak reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020C.
Pinout
HIP1011D, HIP1011E (SSOP)
TOP VIEW
M12VO_2 1
28 M12VIN_2
M12VG_2 2
27 3VISEN_2
PWRON_2 3
FLTN_2 4
VSS 5
26 3VS_2
25 5VISEN_2
24 5VS_2
12VG_2 6
23 3V5VG_2
12VO_2 7
22 12VIN_2
12VO_1 8
21 12VIN_1
12VG_1 9
20 3V5VG_1
OCSET 10
19 5VS_1
FLTN_1 11
18 5VISEN_1
PWRON_1 12
1
PKG.
DWG. #
PACKAGE
17 3VS_1
M12VG_1 13
16 3VISEN_1
M12VO_1 14
15 M12VIN_1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 1999, 2000, 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HIP1011D, HIP1011E
Typical Application
-12V
C1
-12V BUS
5V
SLOT 1
5VISEN_1
M12VIN_1
M12G_1
R1
5VS_1
M12VO_1
Q1
3V5VG_1
C2
3.3V
5V BUS
12V
M12VIN_2
M12G_2
3V5VG_2
M12VO_2
5VS_2
Q2
R2
C4
FROM
SYSTEM CONTROLLER
HIP1011D, HIP1011E
3.3V BUS
+12V BUS
C3
5VISEN_2
12VIN_1
12VG_1
3VISEN_1
12VO_1
R3
3VS_1
12VIN_2
12VG_2
Q3
12VO_2
Q4
3VS_2
PWRON_1
PWRON_2
OCSET
R5
R4
VSS
FLTN_1
OPT.
3VISEN_2
FLTN_2
C5
C6
OPT.
TO SYSTEM CONTROLLER
-12V
SLOT 2
12V
3.3V
5V
FIGURE 1.
2
FN4725.5
November 18, 2004
HIP1011D, HIP1011E
Simplified Schematic (1/2 HIP1011D, HIP1011E)
5VREF
SET (LOW = FAULT)
FAULT LATCH
LOW = FAULT
COMP
FLTN
+ 4.6V
INHIBIT
RESET
COMP
+ 2.9V
INHIBIT
COMP
TIED HIGH IN HIP1011D
TIED LOW IN HIP1011E
+ 10.6V
INHIBIT
+
COMP
12VIN
-
12VIN
+
-
5VS
12VIN
3V5VG
12VIN
5VREF
12VIN
12VIN
POWER-ON
RESET
COMP
LOW WHEN 12VIN < 10V
+
5VISEN
-
5V ZENER
REFERENCE
3VS
+
-
3VISEN
12VIN
+
VOCSET
12VIN
+
COMP
100µA
-
OCSET
12VIN
0.3
12VG
HIGH = FAULT
12VO
12VIN
HIGH = SWITCHES ON
PWRON
GND
+
M12VIN
0.7
+
COMP
M12VG
M12VIN
M12VO
FIGURE 2.
3
FN4725.5
November 18, 2004
HIP1011D, HIP1011E
Pin Descriptions
PIN NO.
DESIGNATOR
FUNCTION
DESCRIPTION
15, 28
M12VIN
-12V Input
4, 11
FLTN
Fault Output
20, 23
3V5VG
3.3V/5V Gate Output
21, 22
12VIN
12V Input
12V supply input for IC and 12VO. Both 12VIns to be connected to a single +12V supply.
16, 27
3VISEN
3.3V Current Sense
Connect to the load side of the current sense resistor in series with source of external 3.3V
MOSFET.
17, 26
3VS
3.3V Source
19, 24
5VS
5V Source
Connect to source of 5V MOSFET switch. This connection along with (5VISEN) senses the
voltage drop across the sense resistor.
18, 25
5VISEN
5V Current Sense
Connect to the load side of the current sense resistor in series with source of external 5V
MOSFET.
3, 12
PWRON
Power On Control
Controls all four switches. High to turn switches ON, Low to turn them OFF.
6, 9
12VG
7, 8
12VO
2, 13
M12VG
Gate of Internal NMOS Connect a capacitor between M12VG and M12VO to set the startup ramp for the M12V
supply. This capacitor is charged with 25A during startup.
1, 14
M12VO
Switched -12V Output
10
OCSET
Overcurrent Set
5
VSS
Ground
-12V Supply Input. Also provides power to the -12V overcurrent circuitry.
5V CMOS Fault Output; LOW = FAULT. An optional capacitor may be placed from this pin
to ground to provide additional immunity from power supply glitches.
Drive the gates of the 3.3V and 5V MOSFETs. Connect a capacitor to ground to set the
startup ramp. During turn on, this capacitor is charged with a 25A current source.
HIP1011D UV comparator disabled when this pin is below 9.6V nominal.
Connect to source of 3.3V MOSFET. This connection along with (3VISEN) senses the
voltage drop across the sense resistor.
Gate of Internal PMOS Connect a capacitor between 12VG and 12VO to set the startup ramp for the +12V supply.
This capacitor is charged with a 25A current source during startup.
HIP1011D UV comparator disabled when this pin >1.4V nominal.
Switched 12V Output
4
Switched 12V output. Rated for 0.5A.
Switched -12V Output. Rated for 0.1A.
Connect a resistor from this pin to ground to set the overcurrent trip point of all eight
switches. All eight overcurrent trips can be programmed by changing the value of this
resistor. The default (6.04k, 1%) is compatible with the maximum allowable currents as
outlined in the PCI specification.
Connect to common of power supplies.
FN4725.5
November 18, 2004
HIP1011D, HIP1011E
Absolute Maximum Ratings
Thermal Information
12VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +14.0V
12VO, 12VG, 3V5VG . . . . . . . . . . . . . . . . . . . . -0.5V to 12VIN+0.5V
M12VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -14.0V to +0.5V
M12VO, M12VG. . . . . . . . . . . . . . . . . . . . . . VM12VIN-0.5V to +0.5V
3VISEN, 5VISEN . . . . . . . . . . -0.5V to the Lesser of 12VIN or +7.0V
Voltage, Any Other Pin. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
12VO Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3A
M12VO Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8A
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2KeV (HBM)
Thermal Resistance (Typical, Note 1)
JA (°C/W)
SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
77
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(SSOP - Lead Tips Only)
Operating Conditions
12VIN Supply Voltage Range . . . . . . . . . . . . . . . . +10.8V to +13.2V
5V and 3.3V Input Supply Tolerances 10%
12VO Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to +0.5A
M12VO Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to +0.1A
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. All voltages are relative to GND, unless otherwise specified.
Electrical Specifications
Nominal 5.0V and 3.3V Input Supply Voltages,
12VIN = 12V, M12VIN = -12V, TA = TJ = 0 to 70°C, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
8
-
A
5V/3.3V SUPPLY CONTROL
5V Overcurrent Threshold
IOC5V
See Figure 24, Typical Application
5V Overcurrent Threshold Voltage
VOC5V_1
VOCSET = 0.6V
33
42
50
mV
5V Overcurrent Threshold Voltage
VOC5V_2
VOCSET = 1.2V
70
80
90
mV
5V Undervoltage Trip Threshold
V5VUV
(HIP1011D only)
4.42
4.65
4.8
V
5V Undervoltage Fault Response Time
t5VUV
(HIP1011D only)
-
110
160
ns
5V Turn-On Time
(PWRON High to 5VOUT = 4.75V)
tON5V
C3V5VG = 0.022F, C5VOUT = 2000F, RL = 1
-
6.5
-
ms
3V Overcurrent Threshold
IOC3V
See Figure 24, Typical Application
-
10
-
A
3V Overcurrent Threshold Voltage
VOC3V_1
VOCSET = 0.6V
41
52
62
mV
3V Overcurrent Threshold Voltage
VOC3V_2
VOCSET = 1.2V
89
98
108
mV
3V Undervoltage Trip Threshold
V3VUV
(HIP1011D Only)
2.74
2.86
2.98
V
3V Undervoltage Fault Response Time
t3VUV
(HIP1011D Only)
-
110
160
ns
V3V5VGENVth (HIP1011D Only)
-
9.6
-
V
-
6.5
-
ms
11.5
11.8
-
V
19
25.0
29
A
3V5VG Undervoltage Enable Threshold
Voltage
3V Turn-On Time
(PWRON High to 3VOUT = 3.00V)
3V5VG VOUT High
tON3V
C3V5VG = 0.022F, C3VOUT = 2000F,
RL = 0.43
Vout_hi_35VG PWRON = High, FLTN = High
Gate Output Charge Current
IC3V5VG
PWRON = High, V3V+5VG = 4V
Gate Turn-On Time
(PWRON High to 3V5VG = 11V)
tON3V5V
C3V5VG = 0.033F, 3V5VG Rising 10% to 90%
-
280
-
s
Gate Turn-Off Time
tOFF3V5V
C3V5VG = 0.033F, 3V5VG Falling 90% to 10%
-
2
-
s
5
FN4725.5
November 18, 2004
HIP1011D, HIP1011E
Electrical Specifications
Nominal 5.0V and 3.3V Input Supply Voltages,
12VIN = 12V, M12VIN = -12V, TA = TJ = 0 to 70°C, Unless Otherwise Specified (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
0.3
0.35

-
0.35
0.50

+12V SUPPLY CONTROL
On Resistance of Internal PMOS
rDS(ON)12
PWRON = High, ID = 0.5A
TA = TJ = 25°C
TA = TJ = 70°C
Overcurrent Threshold
IOC12V_1
VOCSET = 0.6V
0.5
0.6
0.9
A
Overcurrent Threshold
IOC12V_2
VOCSET = 1.2V
1.2
1.4
1.8
A
12V Undervoltage Trip Threshold
V12VUV
(HIP1011D only)
10.25
10.6
10.8
V
Undervoltage Fault Response Time
t12VUV
(HIP1011D only)
-
110
-
ns
Gate Charge Current
IC12VG
PWRON = High, V12VG = 10V
19
25.0
29
A
Turn-On Time
(PWRON High to 12VG = 1V)
tON12V
C12VG = 0.033F, 12VG Falling 90% - 10%
-
16
-
ms
Turn-Off Time
tOFF12V
C12VG = 0.022F, 12VG Rising 10% - 90%
-
3
-
s
PWRON = High, ID = 0.1A
-
0.7
1

-
1.0
1.3

-12V SUPPLY CONTROL
On Resistance of Internal NMOS
rDS(ON)M12
TA = TJ = 25°C
TA = TJ = 70°C
Overcurrent Threshold
IOC12V_1
VOCSET = 0.6V
0.13
0.17
0.25
A
Overcurrent Threshold
IOC12V_2
VOCSET = 1.2V
0.23
0.36
0.52
A
Gate Output Charge Current
ICM12VG
PWRON = High, V3VG = -10V
19
25
29
A
Turn-On Time
(PWRON High to M12VO = -10.8V)
tONM12V
CM12VG = 0.033F, CM12VO = 50F, RL = 120
-
16
-
ms
Turn-Off Time
tOFFM12V
CM12VG = 0.033F, M12VG Falling 90% to 10%
-
3
-
s
M12VIN Input Bias Current
IBM12VIN
PWRON = High
-
2.5
5
mA
CONTROL I/O PINS
Supply Current
IVCC
-
5.3
8
mA
OCSET Current
IOCSET
93
100
107
A
tOC
-
500
960
ns
VTHPWRON
1.0
1.6
2.1
V
-
0.25
0.4
V
Overcurrent Fault Response Time
PWRON Threshold Voltage
FLTN Output Low Voltage
VFLTN,OL
IFLTN = 0.9mA
FLTN Output High Voltage
VFLTN,OH
IFLTN = 0 to -4mA
3.5
4.3
-
V
FLTN Output Latch Threshold
VFLTN, TH
FLTN High to Low Transition
1.8
2.3
3
V
12V Power On Enable Threshold
VPOR, THrise
VCC Voltage Rising
9.4
10
10.2
V
12V Power On Reset Threshold
VPOR, THfall
VCC Voltage Falling
8.9
9.3
9.6
V
6
FN4725.5
November 18, 2004
HIP1011D, HIP1011E
Introduction
The HIP1011D and HIP1011E are the first dual PCI slot IC
devices designed to provide control and protection of the
four PCI power supplies independently to two PCI slots. Like
the widely used HIP1011 this device complies with the PCI
Hot Plug specification facilitating the service, upgrading or
expansion of PCI based servers without the need to power
down the server. The HIP1011D protects against overcurrent
(OC) for the -12V, +12V, +3.3V, +5V and undervoltage (UV)
conditions for the +12V, +3.3V, +5V supplies. The HIP1011E
only responds to OC conditions.
Figure 1 illustrates the typical implementation of the
HIP1011D, HIP1011E. Additional components for optimizing
performance for particular applications, or desired features
may be necessary.
Key Feature Description and Operation
The HIP1011D/E, four power MOSFETs and a few passive
components as configured in Figure 1, create a small yet
complete power control solution for two PCI slots. It provides an
OC trip level greater than the maximum PCI specified current
for each supply to each slot. OC monitoring and protection for
the 3.3V and 5V supplies is provided by sensing the voltage
across external current-sense resistors. For the +12V and -12V
inputs, OC protection is provided internally. On-chip references
in the HIP1011D are used to monitor the +5V, +3.3V and +12V
outputs for UV conditions. During an OC condition on any
output, or a UV condition on the +5V, +3.3V or +12V outputs
(HIP1011D only), all slot specific MOSFETs are immediately
latched-off and a LOW (0V) is presented to the appropriate
FLTN output. During initial power-up of the main VCC supply
(+12V), the PWRON inputs are inhibited from turning on the
switches, and the latch is held in the reset state until the VCC
input is greater than 10V. After a fault has been asserted and
FLTN is latched low cycling PWRON low then high will clear the
FLTN latch. User programming of the OC thresholds for both
controlled slots is provided by a single resistor connected to the
OCSET pin along with RSENSE . In addition delay time to latch
off after a fault condition can be increased by increasing the
FLTN to ground capacitance and the turn-on ramp rate can be
increased by increasing the gate pin capacitance.
Customizing Circuit Performance
OverCurrent (OC) Set Functionality and Resistor
Choice
The HIP1011D/E allows easy custom programming of the
OC levels of all 4 supplies simultaneously for both PCI slots
by simply changing the resistor value between OCSET, (pin
10), and ground. The ROCSET value and the OCSET 100A
current source sets a voltage that is used in each of eight
comparators, (one for each supply for both slots). The
voltages developed across the 3.3V and 5V sense resistors
are applied to the inputs of their respective comparators. The
+12V and -12V currents are sensed internally with pilot
7
devices. Once any comparator trips, that output is fed
through logic circuits resulting in the appropriate FLTN, (pin
4 or pin 11), going low, indicating a fault condition on that
particular slot. Because of the internal current monitoring of
the +12V and -12V switches, their programming flexibility is
limited to ROCSET changes. The 3.3V and 5V overcurrent
trip points depend on both ROCSET and the value chosen for
each sense resistor.
See Table 1 to determine OC protection levels relative to
choice of ROCSET and RSENSE values.
Overcurrent design guidelines and recommendations are as
follows:
1. For PCI applications, set ROCSET to 6.04k, and use
5m 1% sense resistors (see Figure 24).
2. For non PCI specified applications, the following
precautions and limitations apply:
A. Do not exceed the maximum power of the integrated
NMOS and PMOS. High power dissipation must be
coupled with effective thermal management. The
integrated PMOS has an rDS(ON) of 0.3. Thus, with 1A
of steady load current on each of the PMOS devices the
power dissipation is 0.6W. The thermal impedance of the
package is 95 degrees Celsius per watt, limiting the
average DC current on the 12V supply to about 1A on
each slot and imposing an upper limit on the ROCSET
resistor. Do not use an ROCSET resistor greater than
15k.
The average current on the -12V supply should not
exceed 0.7A. Since the thermal restrictions on the +12V
supply are more severe, the +12V supply restricts the use
of the HIP1011 to applications where the 12V supplies
draw relatively little current. Since both supplies only have
one degree of freedom, the value of ROCSET, the
flexibility of programming is quite limited. For applications
where more power is required on the +12V supply,
contact your local Intersil sales representative for
information on other Hot Plug solutions.
B. Do not try to sense voltages across the external sense
resistors that are less than 33mV. Spurious faults due to
noise and comparator input sensitivity may result. The
minimum recommended ROCSET value is 6k. This will
set the nominal OC voltage thresholds at 52mV and
42mV for the 3.3V and 5V comparators respectively. This
is the voltage level at which the OC fault (IOUT x RSENSE)
will occur.
C. Minimize VRSENSE so as to not significantly reduce the
voltage delivered to the adapter card. Remember PCB
trace and connector distribution voltage losses also need
to be considered. Make sure that the RSENSE resistor
can adequately handle the dissipated power. For best
results use a 1% precision resistor with a low temperature
coefficient.
D. Minimize external FET rDS(ON). Low rDS(ON) or multiple
MOSFETs in parallel are recommended. See Intersil for a
complete selection of MOSFET offerings.
FN4725.5
November 18, 2004
HIP1011D, HIP1011E
TABLE 1.
SUPPLY
HOW TO DETERMINE +25c NOMINAL (10%) IOC
FOR EACH SUPPLY
+3.3V IOC
((100A x ROCSET)/11.5)/RRSENSE
+5.0V IOC
((100A x ROCSET)/14.5)/RRSENSE
+12V IOC
(100A x ROCSET)/1
-12V IOC
(100A x ROCSET)/3.4
Time Delay to Latch-Off
Time delay to latch-off allows for a predetermined delay from
an OC or UV in the HIP1011D or an OC in the HIP1011E
event to the simultaneous latch-off of all four supply switches
of the affected slot. This delay period is set by the
capacitance value to ground from the FLTN pins for each
slot. This capacitance value tailors the FLTN signal going low
ramp rate. This provides a delay to the fault signal latch-off
threshold voltage, FLTN, Vth. By increasing this time, the
HIP1011D/E delays immediate latch-off of the bus supply
switches, thus ignoring transient faults. See additional
information in the “Using the HIP1011DEVAL1 Platform”
section of this data sheet. The HIP1011E has all features of
the HIP1011D but it does not respond to UV events.
Caution: The primary purpose of a protection device such
as the HIP1011D/E is to quickly isolate a faulted card from
the voltage bus. Delaying the time to latch-off works against
this primary concern so care must be taken when using this
feature. Ensure adequate sizing of external FETs to carry
additional current during time out period. Understand that
voltage bus disruptions must be minimized for the time delay
period in the event of a crow bar failure.
Devices using an unadjustable preset delay to latch-off time
present the user with the inability to eliminate these
concerns increasing cost and the chance of additional ripple
through failures.
HIP1011D, HIP1011E Soft Start and Turn-Off
Considerations
The HIP1011D/E does allow the user to select the rate of
ramp up on the voltage supplies. This startup ramp
minimizes in-rush current at startup while the on card bulk
capacitors charge. The ramp is created by placing
capacitors on M12VG to M12VO, 12VG to 12VO and 3V5VG
to ground. These capacitors are each charged up by a
nominal 25A current during turn on. The same value for all
gate timing capacitors is recommended. A recommended
minimum value of 0.033F as a smaller value may cause
overcurrent faults at power up. This recommendation results
in a nominal gate voltage ramp rate of 0.76V/ms. The gate
capacitors must be discharged when a fault is detected to
turn off the power FETs. Thus, larger caps slow the response
time. If the gate capacitors are too large the HIP1011D/E
may not be able to adequately protect the bus or the power
FETs. The HIP1011D/E have internal discharge FETs to
8
discharge the load when disabled. Upon turn-off these
internal switches on each output discharge the load
capacitance pulling the output to GND. These switches are
also on when PWRON is low thus an open slot is held at the
GND level.
Decoupling Precautions and Recommendations
For the HIP1011D/E proper decoupling is a particular
concern during the normal switching operation and
especially during a card crowbar failure. If a card
experiences a crow bar short to ground, the supply to the
other card will experience transients until the faulted card is
isolated from the bus. In addition the common IC nodes
between the two sides can fluctuate unpredictably resulting
in a false latch-off of the second slot. Additionally to the
mother board bulk capacitance, it is recommended that 10F
capacitors be placed on both the +12V and -12V lines of the
HIP1011D/E as close to the chip as possible.
Recommended PCB Layout Design Best Practices
To ensure accurate current sensing, PCB traces that
connect each of the current sense resistors to the
HIP1011D/E must not carry any load current. This can be
accomplished by two dedicated PCB kelvin traces directly
from the sense resistors to the HIP1011D/E (see examples
of correct and incorrect layouts below in Figure 3). To reduce
parasitic inductance and resistance effects, maximize the
width of the high-current PCB traces.
CORRECT
TO HIP1011D/E
VS AND VISEN
INCORRECT
TO HIP1011D
VS AND VISEN
CURRENT
SENSE RESISTOR
FIGURE 3. SENSE RESISTOR PCB LAYOUT
FN4725.5
November 18, 2004
HIP1011D, HIP1011E
Typical Performance Curves
1000
320
900
4.632
2.862
300
800
PMOS +12 rON
280
700
5V UVTRIP (V)
NMOS -12 rON
NMOS rON -12 (m)
PMOS rON +12 (m)
4.631
5 UV
2.861
4.630
4.629
2.860
3.3 UV
4.628
3.3V UVTRIP (V)
340
2.859
4.627
260
0
600
10 15 20 25 30 35 40 45 50 55 60 65 70
5
4.626
2.858
5 10 15 20 25 30 35 40 45 50 55 60 65 70
0
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 4. rON vs TEMPERATURE
FIGURE 5. UV TRIP vs TEMPERATURE (HIP1011D only)
10.59
100
3V OCVth, VOCSET = 1.2V
OC Vth (mV)
12 UV TRIP (V)
85
10.57
10.55
5V OCVth, VOCSET = 1.2V
70
3V OCVth, VOCSET = 0.6V
55
5V OCVth, VOCSET = 0.6V
10.53
40
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70
0
5
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 6. 12 UV TRIP vs TEMPERATURE (HIP1011D only)
FIGURE 7. OC Vth vs TEMPERATURE
6
10.0
+12V POWER ON ENABLE
5
4
-12V BIAS
3
+12V THRESHOLDS (V)
+12V BIAS
ABS ±12V BIAS (mA)
10 15 20 25 30 35 40 45 50 55 60 65 70
9.75
9.5
9.25
+12V POWER ON RESET
2
9.0
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (°C)
FIGURE 8. BIAS CURRENT vs TEMPERATURE
9
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (°C)
FIGURE 9. 12V ENABLE AND RESET THRESHOLD
VOLTAGES vs TEMPERATURE
FN4725.5
November 18, 2004
HIP1011D, HIP1011E
Typical Performance Curves
(Continued)
1.5
0.4
-12V OVERCURRENT (A)
+12V OVERCURRENT (A)
VOCSET = 1.2V
1.25
VOCSET = 1.2V
1.0
0.75
VOCSET = 0.6V
0.5
0.3
0.2
VOCSET = 0.6V
0.1
0
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70
0
5
10 15 20 25 30 35 40 45 50 55 60
TEMPERATURE (°C)
FIGURE 10. +12V OVERCURRENT LEVEL vs TEMPERATURE
FIGURE 11. -12V OVERCURRENT vs TEMPERATURE
2.4
FLTN LATCH OFF THRESHOLD (V)
102
101
100
99
2.35
2.3
2.25
2.2
98
0
5
0
10 15 20 25 30 35 40 45 50 55 60 65 70
5
10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 12. OCSET CURRENT vs TEMPERATURE
FIGURE 13. FLTN LATCH-OFF THRESHOLD VOLTAGE vs
TEMPERATURE
100
OV/UV TO FAULT RESPONSE TIME (ns)
IOC SET (µA)
65 70
TEMPERATURE (°C)
90
80
70
60
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (°C)
FIGURE 14. OVERCURRENT AND UNDERVOLTAGE TO FLTN RESPONSE TIME vs TEMPERATURE
10
FN4725.5
November 18, 2004
HIP1011D, HIP1011E
Using the HIP1011DEVAL1 Platform
Evaluating Time Delay to Latch-Off
Test point numbers (TP#) correspond to the HIP1011D/E
device (U5) pin numbers. Thus TP3 and TP12 are
PWRON_2 and PWRON_1 respectively. These 2 pins are
the HIP1011D/E control inputs for each of the 2 integrated
but independent PCI power controllers in the HIP1011D/E.
Provided for delay to latch-off evaluation are 2 locations for
SMD capacitors, C7 and C8. Filling these locations places a
capacitor to ground from each of the HIP1011D/E FLTN pins
thus tailoring the FLTN signal going low ramp rate. This
provides a delay to the fault signal latch-off threshold
voltage, FLTN Vth. By increasing this time the HIP1011D
delays immediate latch-off of the bus supply switches, thus
ignoring transient OC and UV conditions. See Table 3
illustrating the time it takes for switch gate turn-off from the
FLTN start of response to an OC or UV condition. The FLTN
response to an OC or UV condition is 110ns. See Figures 20
through 23 for waveforms.
On the HIP1011DEVAL1 platform are 4 HUF76132SK8,
(11.5m, 30V, 11.5A) N-Channel power MOSFETs, (Q1- Q4)
these are used as the external switches for the +5V and
+3.3V supplies to the load card connectors, P1 and P2.
The intent of any protection device is to isolate the supply
quickly so a faulty card does not drag down a supply. A
longer latch-off delay results in less isolation from a faulty
card to supply.
General and Biasing Information
The HIP1011DEVAL1 platform (Figure 24) comes as a three
part set consisting of 1 motherboard emulator and 2 load
cards. This evaluation platform allows a designer to evaluate
and modify the performance and functionality of the
HIP1011D or HIP1011E in a simple environment.
Current sensing is facilitated by the four 5m 1W metal strip
resistors (R1-R4), the voltages developed across the sense
resistors are compared to references on board the
HIP1011D/E.
TABLE 3.
C7 AND C8 VALUE
OPEN
0.001F
0.01F
0.1F
FLTN to Gate Response
0.1s
0.44s
2.9s
28s
The HIP1011DEVAL1 platform is powered through the J1 to
J5 connector jacks near the top of the board (see Table 2 for
bias voltage assignments.)
TABLE 2. HIP1011DEVAL1 BIAS ASSIGNMENTS
FLTN
J1
J2
J3
J4
J5
GND
+5V
-12V
+12V
+3.3V
After properly biasing the HIP1011D/E and ensuring there is an
adequate ground return from the HIP1011DEVAL1 platform to
the power supplies, (otherwise anomalous and unpredictable
results will occur) signal the PWRON inputs low then insert the
load cards as shown in Figure 15. Signaling either or both
PWRON pins high (>2.4V) will turn on the appropriate FET
switches and apply voltage to the load cards.
3V5VG
FLTN, Vth
FIGURE 16. TIMING DIAGRAM
10ms
1ms
LOAD CARDS
100µs
10µs
1µs
100ns
10ns
HIP1011D
1ns
OPEN
0.001µF
0.01µF
0.1µF
1µF
10µF
FIGURE 17. TYPICAL OC/UV TO VG RESPONSE vs FLTN CAP
FIGURE 15. CORRECT INSTALLATION OF LOAD CARDS
* The HIP1011DEVAL board is supplied with a HIP1011D
installed and in addition a loose packed HIP1011E.
11
FN4725.5
November 18, 2004
HIP1011D, HIP1011E
Typical Performance Curves (Continued)
SUPPLY CURRENT
CH3
SUPPLY CURRENT
CH2
CH1
CH2
ENABLE 2
ENABLE 2
CH1
ENABLE 1
ENABLE 1
CH1 AND CH2 VOLTAGE (5V/DIV)
CH3 CURRENT (2A/DIV)
TIME (100ms/DIV)
FIGURE 18. HIP1011DEVAL1 3.3V SUPPLY CURRENT AS
EACH SLOT CONTROLLER TURNS ON INTO
LOAD CARD
CH1 AND CH2 VOLTAGE (5V/DIV)
CH3 CURRENT (2A/DIV)
TIME (100ms/DIV)
FIGURE 19. HIP1011DEVAL1 3.3V SUPPLY CURRENT AS
CONTROLLER 1 TURNS ON INTO SHORTED
LOAD CARD
VG
VG
FLTN
FLTN
TIME (1µs/DIV)
FLTN = OPEN
VOLTAGE (2V/DIV)
FIGURE 20. FLTN TO 35VG DELAY
VOLTAGE (2V/DIV)
TIME (1µs/DIV)
FLTN = 0.001µF
FIGURE 21. FLTN TO 35VG DELAY
VG
VG
FLTN
FLTN
VOLTAGE (2V/DIV)
TIME (2µs/DIV)
FLTN = 0.01µF
FIGURE 22. FLTN TO 35VG DELAY
12
VOLTAGE (2V/DIV)
TIME (10µs/DIV)
FLTN = 0.1µF
FIGURE 23. FLTN TO 35VG DELAY
FN4725.5
November 18, 2004
HIP1011D, HIP1011E
12V
P1
-12V
J3
-12V BUS
C1
5V
5VISEN_1
M12VIN_1
M12G_1
R1
5VS_1
M12VO_1
Q1
3V5VG_1
J1
C2
3.3V
M12VIN_2
M12G_2
3V5VG_2
M12VO_2
5VS_2
J2
5V BUS
Q2
R2
J4
+12V BUS
C3
C4
TP3
5VISEN_2
12VIN_1
12VG_1
HIP1011D, HIP1011E
U1
12VO_1
C6
R3
3VS_1
12VIN_2
12VG_2
Q3
12VO_2
3.3V BUS
J5
Q4
3VS_2
PWRON_1
PWRON_2
OCSET
TP12
C5
3VISEN_1
R4
VSS
3VISEN_2
FLTN_2
FLTN_1
TP11
R5
-12V
R6
R7
D1
D2
C7
NO POP
P2
12V
C8
NO POP
3.3V
TP4
5V
FIGURE 24.
TABLE 4. HIP1011DEVAL1 BOARD COMPONENT LISTING
COMPONENT
DESIGNATOR
U1
COMPONENT NAME
COMPONENT DESCRIPTION
HIP1011DCB or HIP1011ECB Dual PCI HotPlug
Controller
Intersil, HIP1011DCB or HIP1011ECB Dual PCI HotPlug
Controller
HUF76132SK8 (or equivalent)
HUF76132SK8 (or equivalent), 11.5m, 30V, 11.5A Logic Level
N-Channel MOSFET
R1 - R4
Sense Resistor for 3.3V and 5V Supplies
Dale, WSL-2512 5m Metal Strip Resistor
C1 - C6
Gate Timing Capacitors
0.033F 805 Chip Capacitor
R5
Overcurrent Set Resistor
6k 805 Chip Resistor
Latch-Off Delay Capacitors
Place provided for 805 Chip Cap
R6, R7
LED Series Resistors
470 805 Chip Resistors
D1, D2
Fault Indicating LED
Green SMD LED
Q1, Q2, Q3, Q4
C7, C8 (Not Provided)
TP1 - TP28
P1, P2
Test Point for Corresponding Device Pin Number
Connectors for Load Cards
13
Sullins EZM06DRXH
FN4725.5
November 18, 2004
HIP1011D, HIP1011E
TABLE 4. HIP1011DEVAL1 BOARD COMPONENT LISTING (Continued)
COMPONENT
DESIGNATOR
COMPONENT NAME
COMPONENT DESCRIPTION
RL1
3.3V Load Board Resistor
1.1, 10W
RL2
5.0V Load Board Resistor
2.5, 10W
RL3
+12V Load Board Resistor
47, 5W
RL4
-12V Load Board Resistor
240, 2W
CL1, CL2
+3.3V and +5.0V Load Board Capacitors
2200F
CL3, CL4
+12V and -12V Load Board Capacitors
100F
RL1
3.3V
CL1
RL2
5.0V
CL2
RL3
+12V
CL3
RL4
-12V
CL4
FIGURE 25. LOAD BOARD (2x)
14
FN4725.5
November 18, 2004
HIP1011D, HIP1011E
Shrink Small Outline Plastic Packages (SSOP)
Quarter Size Outline Plastic Packages (QSOP)
M28.15
N
INDEX
AREA
H
0.25(0.010) M
E
2
SYMBOL
3
0.25
0.010
SEATING PLANE
-A-
INCHES
GAUGE
PLANE
-B1
28 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
(0.150” WIDE BODY)
B M
A
D
L
h x 45°
-C-

e
A2
A1
B
C
0.10(0.004)
0.17(0.007) M
C A M
B S
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
MIN
MAX
MILLIMETERS
MIN
MAX
NOTES
A
0.053
0.069
1.35
1.75
-
A1
0.004
0.010
0.10
0.25
-
A2
-
0.061
-
1.54
-
B
0.008
0.012
0.20
0.30
9
C
0.007
0.010
0.18
0.25
-
D
0.386
0.394
9.81
10.00
3
E
0.150
0.157
3.81
3.98
4
e
0.025 BSC
0.635 BSC
-
H
0.228
0.244
5.80
6.19
-
h
0.0099
0.0196
0.26
0.49
5
L
0.016
0.050
0.41
1.27
6
N

28
0°
28
8°
0°
7
8°
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
Rev. 1 6/04
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch)
per side.
5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of “B”
dimension at maximum material condition.
10. Controlling dimension: INCHES. Converted millimeter dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
15
FN4725.5
November 18, 2004
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