DATASHEET

ODUCT
OBSOLETE PR
PLACEMENT
RE
D
DE
NO RECOMMEN
nter at
nical Support Ce
contact our Tech www.intersil.com/tsc
or
1-888-INTERSIL
DATASHEET
Dual Slot PCI-Express Hot Plug Controller
ISL6112
Features
The ISL6112 targets the PCI-Express add-in card hot plug
application. Together with two each of N-Channel and
P-Channel MOSFETs, four current sense resistors, and several
external passive components, the ISL6112 provides a
compliant hot plug power control solution to any combination
of two PCI-Express X1, X4, X8 or X16 slots.
• Supports Two Independent PCI-Express Slots
The ISL6112 features the ability to program a maximum
current regulated level for each of the MAIN outputs for a
common programmable duration. With this ability, both fault
isolation protection and imperviousness to electrical transients
(OC and soft-start protection) are provided to each system
supply. For each 12VMAIN supply, the current regulated (CR)
level is set by a resistor value dependent on the size of the
PCI-Express connector (X1, X4/X8 or X16) to be powered. This
resistor is a sub ohm standard value current sense resistor;
one each for each of the 3VMAIN and 12VMAIN supplies. The
voltage across this resistor is compared to a 50mV reference,
providing a nominal CR protection level that would be set
above the maximum specified slot limits. The 3.3V supply can
use a 15mΩ sense resistor, compared to a 50mV reference, to
provide a nominal regulated current limit of 3.3A to all
connector sizes. A shutdown without a CR duration delay is
invoked if RSENSE voltage is >100mV. VAUX is internally
monitored and controlled to provide nominal limiting to 1A of
load current.
• Programmable Current Regulation Protection Function for X1,
X4, X8, X16 Connectors
• 12V, 3.3V, and 3.3VAUX Supplies Supported per PCI Express
Specification V1.0A
• Voltage Tolerant I/O SMBus Interface for Slot Power Control
and Status, Compatible with SMBus 2.0 Systems
• Programmable Current Regulation Duration
• Programmable In-Rush Current Limiting
• Dual-Level Fault Detection for Quick Fault Response Without
Nuisance Tripping
• Slot-to-Slot Electrical and Thermal Isolation
• Two General-Purpose Input Pins Suitable for Interface to
Logic and Switches
• Pb-Free (RoHS Compliant)
Applications
• PCI Express V1.0A Hot-Plug Power Control
• PCI-Express Servers
• Power Supply Distribution and Control
104
1200
103
1150
AUX CURRENT LIMIT (mA)
WOC THRESHOLD VOLTAGE (V)
The ISL6112 is System Management Interface (SMI) capable,
with an integrated SMBus link for communication, control,
monitoring, and reporting of IC and slot conditions.
Information such as UV, OC, STATUS, and power level are
available. Additionally, the IC has a minimum of I/O for
implementations where Hot-Plug Hardware Interface (HPI) is
implemented.
• Highest Available Accuracy External RSENSE Current
Monitoring on Main Supplies
102
101
100
99
98
97
96
-60
-40
-20
0
20
40
60
80
100
120
FIGURE 1. FAST TRIP THRESHOLD VOLTAGE vs TEMPERATURE
1
1050
1000
950
900
850
800
-60
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
August 25, 2011
FN6456.1
1100
FIGURE 2. AUX CURRENT LIMIT vs TEMPERATURE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2007, 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL6112
Typical Application Diagram
+12V
SYSTEM
POWER +3.3V
SUPPLY
VSTBY
0.1µF
PCI-EXPRESS CONNECTOR
0.1µF
11
26
15
VSTBYA VSTBYB VAUXA
12VINA
2 CFILTERA
VSTBY
35 CFILTERB
C1
C2
100k
100k
100k 100k
9
FORCE_ONA
28
FORCE_ONB
4
GPI_A0
38
GPI_B0
VSTBY
AUXENA
AUXENB
ONA
ONB
VSTBY
HOT-PLUG
CONTROLLER
PWRGDA
PWRGDB
FAULTA
FAULTB
SMBUS
BASE
ADDRESS
VSTBY
5
12VSENSEA 8
3VINA 12
FORCE_ONB
GPI_A0
RSENSE^
#CGS
22nF
12VGATEA 3
#CGD
6800pF
12VOUTA 10
FORCE_ONA
PCI
EXPRESS
BUS
0.1µF
*R12VGATEA
15
0.1µF
12V
2.1A (x4/x8)
RSENSE^
0.015
3VSENSEA 13
GPI_B0
*R3VGATEA
3VGATEA 14
15
3VOUTA 16
#
C
GATE
ISL6112
22nF
10k x 4
12VINB 32
0.1µF
45
AUXENA
42
12VSENSEB 29
AUXENB
44
#CGS *R12VGATEB
ONA
22nF
43
15
34
ONB
12VGATEB
#CGD
6800pF
27
12VOUTB
10k x 4
0.1µF
6
PWRGDA
31
3VINB
PWRGDB
25
1
FAULTA
36
3VSENSEB 24
FAULTB
*R3VGATEB
3VGATEB 23
41
15
A0
3VOUTB 21
40
A1
VAUXB 22
39
A2
17
#CGATE
37 INT
GND
22nF
33
47 SCL
GND
48 SDA
GND 46
3.3V
3.0A
RSENSE^
12V
2.1A (x4/x8)
RSENSE^
0.015
3.3V
3.0A
3.3AUX
375mA
PCI
EXPRESS
DATA BUS
10k x 3
SMBUS I/O
SDA
SDA
SCL
SCL MANAGEMENT
CONTROLLER
INT
INT
3.3AUX
375mA
PCI-EXPRESS CONNECTOR
* Values for R12VGATE and R3VGATE may vary
depending upon the CGS of the external MOSFETs.
# These components are not required for ISL6112
operation but can be implemented for GATE output
slew rate control (application specific).
• Bold lines indicate high current paths.
^ RSENSE value is application specific.
2
FN6456.1
August 25, 2011
ISL6112
Functional Block Diagram (One Channel)
ON
VSTBY
AUXEN
12VIN
POWER-ON
RESET
250µs
VSTBY
UVLO
12VGATE
VAUX CHARGE
PUMP AND
MOSFET
VAUX
12VSENSE
12VIN
50mV
VAUX
OVERCURRENT
12V
UVLO
3VIN
50mV
ON/OFF
3VGATE
12V BIAS
ON/OFF
3VSENSE
3VIN
100mV*
PWRGD
THERMAL
SHUTDOWN
ON/OFF
100mV*
ON/OFF
3V
UVLO
FAULT
ON/
OFF
VSTBY
IREF
VAUX
PWRGD
LOGIC CIRCUITS
12VPWRGD
12VOUT
CFILTER
10.5V
1.25V
3VPWRGD
3VOUT
DIGITAL CORE/SERIAL INTERFACE
2.8V
VSTBY
INT
40k x 3
FORCE_ON
GND
GPI
SCL SDA
A2 A1 A0
BOTH A AND B SLOTS SHARE THE SCL, SDA, A0, A1, A2, INT PINS.
3
FN6456.1
August 25, 2011
ISL6112
Pin Configuration
INT
GPI_B0
A2
A1
A0
AUXENB
ONB
ONA
AUXENA
GND
SCL
SDA
ISL6112
(48 LD 7X7 QFN)
TOP VIEW
48 47 46 45 44 43 42 41 40 39 38 37
36 FAULTB
FAULTA 1
CFILTERA 2
35 CFILTERB
12VGATEA 3
34 12VGATEB
GPI_A0 4
33 GND
12VINA 5
32 12VINB
GND
PWRGDA 6
NC 7
31 PWRGDB
30 NC
(EXPOSED BOTTOM PAD)
12VSENSEA 8
29 12VSENSEB
FORCE_ONA 9
28 FORCE_ONB
12VOUTA 10
27 12VOUTB
VSTBYA 11
26 VSTBYB
25 3VINB
3VINA 12
3VSENSEB
3VGATEB
VAUXB
3VOUTB
NC
NC
NC
GND
3VOUTA
VAUXA
3VGATEA
3VSENSEA
13 14 15 16 17 18 19 20 21 22 23 24
Pin Descriptions
PIN NUMBER
PIN NAME
PIN FUNCTION
5, 32
12VINA, 12VINB
Provides 12VMAIN power supply and the high side of the sense resistor inputs. This must be a Kelvin
connection between IC and sense resistor. An undervoltage lockout circuit (UVLO) prevents the switches from
turning on while this input is less than its lockout threshold.
12, 25
3VINA, 3VINB
Provides 3.3VMAIN power supply and the high side of the sense resistor inputs. This must be a Kelvin
connection between IC and sense resistor. An undervoltage lockout circuit (UVLO) prevents the switches from
turning on while this input is less than its lockout threshold.
16, 21
3VOUTA, 3VOUTB
3.3VOUT. Connected to 3.3V FET source. These are used to monitor the 3.3V output voltages for Power-Good
status.
10, 27
12VOUTA, 12VOUTB 12VOUT. Connected to 12V FET drain. These are used to monitor the 3.3V output voltages for Power-Good
status.
8, 29
12VSENSEA,
12VSENSEB
12VMAIN low side of sense resistor connection. When either current limit threshold of the load current across
the sense resistor = 50mV is reached, the related 12VGATE pin is modulated to maintain a constant voltage
across the sense resistor and thus a constant current into the load. If the 50mV threshold is exceeded for tFLT,
the isolation protection is tripped, and the GATE pin for the affected supply’s external MOSFET is immediately
pulled high. This must be a Kelvin connection between IC and sense resistor.
13, 24
3VSENSEA,
3VSENSEB
3.3VMAIN low side of sense resistor connection. When either current limit threshold of the load current across
the sense resistor = 50mV is reached, the related 3V GATE pin is modulated to maintain a constant voltage
across the sense resistor and thus a constant current into the load. If the 50mV threshold is exceeded for tFLT,
the isolation protection is tripped, and the GATE pin for the affected supply’s external MOSFET is immediately
pulled low. This must be a Kelvin connection between IC and sense resistor.
3, 34
12VGATEA
12VGATEB
12V gate drive outputs. Each pin connects to the gate of an external P-Channel MOSFET. During power-up, the
CGATE and the CGS of the MOSFETs are connected to a 25µA current sink. This controls the value of dv/dt
seen at the source of the MOSFETs. During current limit events, the voltage at this pin is adjusted to maintain
constant current through the switch for a period of tFLT. Whenever an overcurrent, thermal shutdown, or input
undervoltage fault condition occurs, the GATE pin for the affected slot is immediately brought high. These pins
are charged by an internal current source during power-down.
4
FN6456.1
August 25, 2011
ISL6112
Pin Descriptions (Continued)
PIN NUMBER
PIN NAME
PIN FUNCTION
14, 23
3VGATEA 3VGATEB
3V gate drive outputs. Each pin connects to the gate of an external N-Channel MOSFET. During power-up, the
CGATE and the CGS of the MOSFETs are connected to a 25µA current source. This controls the value of dv/dt
seen at the source of the MOSFETs, and hence the current flowing into the load capacitance. During current
limit events, the voltage at this pin is adjusted to maintain constant current through the switch for a period of
tFLT. Whenever an overcurrent, thermal shutdown, or input undervoltage fault condition occurs, the GATE pin
for the affected slot is immediately brought low. During power-down, these pins are discharged by an internal
current source.
11, 26
VSTBYA, VSTBYB
3.3V standby input voltage. Required to support PCI-Express VAUX output. Additionally, the SMBus logic and
internal registers run off of VSTBY to ensure that the chip is accessible during standby modes. A UVLO circuit
prevents turn-on of this supply until VSTBY rises above its UVLO threshold. Both pins must be externally
connected together at the ISL6112 controller.
15, 22
VAUXA, VAUXB
44, 43
ONA, ONB
Enable inputs. Rising-edge triggered. Used to enable or disable the MAINA and MAINB (+3.3V and +12V)
outputs. Taking ON low after a fault resets the +12V and/or +3.3V fault latches for the affected slot. Tie these
pins to GND if using SMI power control. Also see pin descriptions for FAULTA and FAULTB.
45, 42
AUXENA, AUXENB
Level sensitive auxiliary enable inputs. Used to enable or disable the VAUX outputs. Taking AUXEN low after a
fault resets the respective slot’s Aux Output Fault Latch. Tie these pins to GND if using SMI power control. Also
see pin descriptions for FAULTA and FAULTB.
3.3VAUX outputs to PCI-Express card slots. These outputs connect the 3.3AUX pin of the PCI-Express
connectors to VSTBY via internal 400m MOSFETs. These outputs are 1A current limited and protected
against short-circuit faults.
2, 35
CFILTERA, CFILTERB Overcurrent timers. Capacitors connected between these pins and GND set the duration of CRTIM. CRTIM is
the amount of time for which a slot remains in current limit before its isolation protection is invoked.
6, 31
PWRGDA PWRGDB Power-is-Good outputs. Open-drain, active-low. Asserted when a slot has been commanded to turn on and has
successfully begun delivering power to its respective +12V, +3.3V, and VAUX outputs. Each pin requires an
external pull-up resistor to VSTBY.
1, 36
FAULTA, FAULTB
Fault outputs. Open-drain, active-low. Asserted whenever the isolation protection trips due to a fault condition
(overcurrent, input undervoltage, over-temperature). Each pin requires an external pull-up resistor to VSTBY.
Bringing the slot’s ON pin low resets FAULT, if FAULT was asserted in response to a fault condition on one of
the slot’s MAIN outputs (+12V or +3.3V). FAULT is reset by bringing the slot’s AUXEN pin low if FAULT was
asserted in response to a fault condition on the slot’s VAUX output. If a fault condition occurred on both the
MAIN and VAUX outputs of the same slot, then both ON and AUXEN must be brought low to de-assert the FAULT
output.
9, 28
FORCE_ONA
FORCE_ONB
Enable inputs. Active-low, level-sensitive. Asserting a FORCE_ON input turns on all three of the respective
slot’s outputs (+12V, +3.3V, and VAUX) while specifically defeating all protections on those supplies. This
explicitly includes all overcurrent and short-circuit protections, and on-chip thermal protection for the VAUX
supplies. Additionally included are the UVLO protections for the +3.3V and +12VMAIN supplies. The
FORCE_ON pins do not disable UVLO protection for the VAUX supplies. These input pins are intended for
diagnostic purposes only. Asserting FORCE_ON causes the respective slot’s PWRGD and FAULT pins to enter
their open-drain state. Note that the SMBus register set continues to reflect the actual state of each slot’s
supplies. There is a pair of register bits, accessible via the SMBus, which can be set to disable (unconditionally
de-assert) either or both of the FORCE_ON pins; see CNTRL Register Bit D[2].
4, 38
GPI_A0, GPI_B0
General purpose inputs. The states of these two inputs are available by reading the Common Status Register,
Bits [4:5]. If not used, connect each pin to GND.
39, 40, 41
A2, A1, A0
SMBus address select pins. Connect to ground or leave open in order to program device SMBus base address.
These inputs have internal pull-up resistors to VSTBY. Address programmed on rising VSTBY.
48
SDA
Bidirectional SMBus data line.
47
SCL
SMBus clock input.
37
INT
Interrupt output. Open-drain, active-low output. Asserted whenever a power fault is detected if the INTMSK bit
(CS Register Bit D[3]) is a logical “0”. This output is cleared by performing an “echo reset” to the appropriate
fault bits in the STAT or CS registers. This pin requires an external pull-up resistor to VSTBY.
17, 33, 46
GND
IC reference pins. Connect together and tie directly to the system’s analog GND plane directly at the device.
7, 18, 19, 20, 30
NC
Reserved. Make no external connections to these pins.
5
FN6456.1
August 25, 2011
ISL6112
Ordering Information
PART NUMBER
(Note 2)
PART MARKING
ISL6112IRZA (Notes 1, 3)
ISL6112 IRZ
ISL6112EVAL1Z
Evaluation Platform
PACKAGE
(Pb-Free)
TEMP RANGE (°C)
-40 to +85
48 Ld 7x7 QFN
PKG. DWG. #
L48.7x7
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6112. For more information on MSL please see Tech Brief TB363.
6
FN6456.1
August 25, 2011
ISL6112
Absolute Maximum Ratings (Note 4)
Thermal Information
12VIN, 12VSENSE, 12VOUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14.5V
VSTBY, 3VIN, 3VSENSE, 3VOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7V
12VGATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 12VI
3VGATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 12VI
Logic I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +5.5V
VAUX Output Current . . . . . . . . . . . . . . . . . . . . . . . . . Short Circuit Protected
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V
Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1kV
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
48 Ld 7x7 QFN Package (Notes 5, 6). . . . .
27
3
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
12VMAIN Supply Voltage Range. . . . . . . . . . . . . . . . . . . . . . . . +12V ± -10%
3.3VMAIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . +3.3V ± -10%
AUXI Supply Voltage Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.3V ± -10%
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. All voltages are relative to GND, unless otherwise specified.
5. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
6. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
12VIN = 12V, 3VIN = 3.3V, VSTBY = 3.3V, TA = TJ = -40°C to +85°C, unless otherwise noted. Boldface
limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
TYP
MAX
(Note 7)
UNITS
0.9
1.5
mA
ICC3.3
0.1
0.2
mA
ICCSTBY
5
6
mA
8
9
10
V
SYMBOL
CONDITION
MIN
(Note 7)
POWER CONTROL AND LOGIC SECTIONS
Supply Current
ICC12
Undervoltage Lockout Thresholds
HPI Enabled or SMI enabled with no load
VUVLO(12V)
12VIN increasing
VUVLO(3V)
3VIN increasing
2.1
2.5
2.75
V
VSTBY increasing
2.8
2.9
2.96
V
VUVLO(STBY)
Undervoltage Lockout Hysteresis
12VIN, 3VIN
VHYSUV
180
mV
Undervoltage Lockout Hysteresis
VSTBY
VHYSSTBY
50
mV
Power-Good Undervoltage Thresholds
Power-Good Detect Hysteresis
VUVTH(12V)
12VOUT decreasing
10.15
10.5
10.75
V
VUVTH(3V)
3VOUT decreasing
2.7
2.8
2.9
V
VUVTH(VAUX)
VAUX decreasing
2.55
2.8
3
V
VHYSPG
12VGATE Voltage
VGATE (12V)
30
mV
Max. Gate Voltage when Enabled
0
0.4
0.55
V
12VGATE Sink Current
IGATE(12VSINK)
Start Cycle
17
25
35
µA
12VGATE Pull-up Current (Fault Off)
IGATE (12VPULLUP)
Any fault condition
(VDD – VGATE) = 2.5V
35
72
-
mA
12VIN –
0.3
12VIN –
0.2
12VIN
V
Start Cycle
17
25
35
µA
Any fault condition
VGATE = 2.5V
80
105
3VGATE Voltage
VGATE(3V)
3VGATE Charge Current
IGATE
(3VCHARGE)
3VGATE Sink Current (Fault Off)
IGATE(3VSINK)
7
Minimum Gate Voltage when Enabled
mA
FN6456.1
August 25, 2011
ISL6112
Electrical Specifications
12VIN = 12V, 3VIN = 3.3V, VSTBY = 3.3V, TA = TJ = -40°C to +85°C, unless otherwise noted. Boldface
limits apply over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
CONDITION
MIN
(Note 7)
TYP
MAX
(Note 7)
UNITS
1.20
1.25
1.30
V
2
2.5
3
µA
CFILTER OVERCURRENT DELAY TIME PINS 2 AND 35 FLOATING
CFILTER Threshold Voltage
VFILTER
CFILTER Charging Current
Nominal Current Limit Duration =
CCFILTER x 550k
IFILTER
VXVIN – VXSENSE > VTHILIMIT
tFILTER
CFILTER Open
10
µs
Current Limit Threshold Voltages
VTHILIMIT
VXIN – VXVSENSE
47.5
50
52.5
mV
Fast-Trip Threshold Voltages
VTHFAST
VXVIN – VXVSENSE
85
100
115
mV
XVSENSE Input Current
ISENSE
LOW-Level Input Voltage ON, AUXEN,
GPI, FORCE_ON, PRSNT
VIL
Output LOW Voltage FAULT, PWRGD
VOL
HIGH-Level Input Voltage ON, AUXEN,
GPI, FORCE_ON
VIH
Internal Pull-ups to VSTBY
0.1
0.8
V
0.4
V
5
V
40
50
kΩ
0.5
1
µA
-2
2
µA
-2
2
µA
IOL = 3mA
2.1
RPULL-UP
12VIN, 3VIN Input Leakage Current
ILKG,OFF XVIN
Input Leakage Current, ON, AUXEN,
FORCE_ON
IIL
ILKG(OFF)
Off-State Leakage Current FAULT,
PWRGD, GPI
Over-temperature Shutdown and
Reset Thresholds, with Overcurrent On
Slot
TOV
Over-temperature Shutdown and
Reset Thresholds, All Other Conditions
(All Outputs Will Latch Off)
rDS(AUX)
Output MOSFET Resistance VAUX
MOSFET
Off-State Output Offset Voltage VAUX
VOFF(VAUX)
VSTBY = +3.3V, 12VIN = OFF; 3VIN = OFF
GPI ILKG for these two pins measured with
VAUX OFF
µA
TJ increasing, each slot
140
°C
TJ decreasing, each slot
130
°C
TJ increasing, each slot
160
°C
TJ decreasing, each slot
150
°C
IDS = 375mA
VAUX = Off
0.8
350
mΩ
25
40
mV
1
1.2
A
Regulated Current Level
ILIM(AUX)
Output Discharge Resistance
RDIS(12V)
12VOUT = 6.0V
1400
1850
Ω
RDIS(3V)
3VOUT = 1.65V
140
180
Ω
RDIS(VAUX)
3VAUX = 1.65V
350
400
Ω
12V Current Limit Response Time
(See “Typical Application Diagram” on
page 2).
tOFF(12V)
CGATE = 25pF
VIN – VSENSE = 140mV
1
2.1
µs
3.3V Current Limit Response Time
(See “Typical Application Diagram” on
page 2).
tOFF(3V)
CGATE = 25pF
VIN – VSENSE = 140mV
0.3
1
µs
VAUX Current Limit Response Time
(See “Typical Application Diagram” on
page 2).
tSC
VAUX = 0V, VSTBY = +3.3V
2.5
µs
Delay from MAIN Overcurrent to FAULT
Output
tPROP
(12V FAULT or 3V
FAULT)
1
µs
8
CFILTER = 0
VIN – VSENSE = 140mV
FN6456.1
August 25, 2011
ISL6112
Electrical Specifications
12VIN = 12V, 3VIN = 3.3V, VSTBY = 3.3V, TA = TJ = -40°C to +85°C, unless otherwise noted. Boldface
limits apply over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
CONDITION
Delay from VAUX Overcurrent to FAULT
Output
tPROP
(VAUXFAULT)
ILIM(AUX) to FAULT output CFILTER = 0 VAUX
Output Grounded
ON, AUXEN, PRSNT Minimum Pulse
Width
Power-On Reset Time after VSTBY
Becomes Valid
MIN
(Note 7)
TYP
MAX
(Note 7)
UNITS
1
µs
tW
100
ns
tPOR
250
µs
SMBUS TIMING
SCL (clock) period
t1
2.5
µs
Data In setup time to SCL HIGH
t2
100
ns
Data Out stable after SCL LOW
t3
300
ns
Data LOW setup time to SCL LOW
t4
100
ns
Data HIGH hold time after SCL HIGH
t5
100
ns
NOTE:
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
9
FN6456.1
August 25, 2011
ISL6112
Typical Performance Curves
6.0
1.0
5.8
0.8
12V ICC
(HPI and SMI)
5.4
SMI ICCSTBY
5.2
ICC (mA)
ICCSTBY (mA)
5.6
5.0
4.8
HPI ICCSTBY
4.6
4.4
0.6
0.4
3.3V ICC
0.2
(HPI and SMI)
4.2
4.0
-60
-40
-20
0
20
40
60
80
100
0
-50
120
0
TEMPERATURE (°C)
FIGURE 3. ICCSTBY CURRENT vs TEMPERATURE
150
104
WOC THRESHOLD VOLTAGE (V)
CURRENT LIMIT Vth (mV)
100
FIGURE 4. ICC CURRENT vs TEMPERATURE
53
52
51
50
49
48
47
-60
-40
-20
0
20
40
60
80
100
120
103
102
101
100
99
98
97
96
-60
-40
-20
TEMPERATURE (°C)
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 5. CURRENT LIMIT THRESHOLD VOLTAGE vs
TEMPERATURE
FIGURE 6. FAST TRIP THRESHOLD VOLTAGE vs TEMPERATURE
1200
400
1150
380
AUX RESISTANCE (mΩ)
AUX CURRENT LIMIT (mA)
50
TEMPERATURE (°C)
1100
1050
1000
950
900
850
360
IAUX = 375mA
340
320
300
280
260
240
220
800
-60
-40
-20
0
20
40
60
80
100
TEMPERATURE (°C)
FIGURE 7. AUX CURRENT LIMIT vs TEMPERATURE
10
120
200
-60
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 8. AUX rDS(ON) vs TEMPERATURE
FN6456.1
August 25, 2011
ISL6112
Typical Performance Curves (Continued)
AUX AND 3MAIN RISING UVLO (V)
12MAIN UVLO RISING (V)
9.30
9.25
9.20
9.15
9.10
9.05
-60
-40
-20
0
20
40
60
80
100
120
3.1
2.9
AUX
2.7
2.5
2.3
3MAIN
2.1
1.9
1.7
1.5
-60
-40
-20
10.54
2.80
10.52
2.79
10.50
10.48
10.46
10.44
10.42
10.40
-20
0
20
40
60
80
100
2.78
GATE FAULT OFF CURRENT (mA)
TURN-ON CURRENT (µA)
3VGATE
24.0
23.5
12VGATE
22.5
-20
0
20
40
60
80
TEMPERATURE (°C)
FIGURE 13. ISL6112 GATE TURN-ON CURRENT (ABS) vs
TEMPERATURE
11
120
3MAIN
2.75
2.74
2.73
AUX
2.72
2.71
-40
-20
0
20
40
60
80
100
120
FIGURE 12. AUX AND 3MAIN POWER GOOD THRESHOLD VOLTAGE vs
TEMPERATURE
25.0
-40
100
TEMPERATURE (°C)
25.5
22.0
-60
80
2.76
2.70
-60
120
FIGURE 11. 12MAIN POWER GOOD THRESHOLD VOLTAGE
vs TEMPERATURE
23.0
60
2.77
TEMPERATURE (°C)
24.5
40
FIGURE 10. AUX AND 3.3MAIN RISING UVLO THRESHOLD VOLTAGE
vs TEMPERATURE
AUX AND 3MAIN UV Vth (V)
12MAIN UV Vth (V)
FIGURE 9. 12MAIN RISING UVLO THRESHOLD VOLTAGE
vs TEMPERATURE
-40
20
TEMPERATURE (°C)
TEMPERATURE (°C)
10.38
-60
0
100
120
120
100
3GATE
80
60
12GATE
40
20
0
-60
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 14. GATE FAULT OFF CURRENT (ABS) vs TEMPERATURE
FN6456.1
August 25, 2011
ISL6112
Typical Performance Curves (Continued)
1.30
3.0
FILTER THRESHOLD (V)
FILTER CURRENT (µA)
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
-60
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 15. FILTER CHARGE CURRENT vs TEMPERATURE
Functional Description
The ISL6112 protects the power supplies in PCI-Express systems
that utilize hot-pluggable add-in cards. This IC, together with two
each of N-Channel and P-Channel MOSFETs, four current sense
resistors, and a few external passive components, provides a
compliant hot plug power control solution to any combination of
two PCI-Express X1, X4, X8 or X16 slots.
The ISL6112 primarily features start-up in-rush current
protection, maximum current regulated (CR) levels for each of
the MAIN and AUX outputs, and programmable CR duration so
that both fault isolation protection and imperviousness to
electrical transients are provided. The ISL6112 also offers input
and output voltage supervisory functions and two operational
system interfaces for implementation flexibility.
In-Rush Current Protection
When any electronic circuitry is powered up, there is an in-rush of
current due to the charging of bulk capacitance that resides
across the circuit board supply pins. This transient in-rush current
may cause the system supply voltages to temporarily droop out
of regulation, causing data loss or system lock-up. The ISL6112
addresses these issues by limiting the in-rush currents to the
PCI-Express add-in cards, thereby controlling the rate at which
the load circuits turn on. See Figures 17, 18, 19, 20, 21 and 22
for AUX and MAIN turn-on examples that illustrate the current
limiting capabilities across a variety of compensation component
values.
MAIN Supply Overcurrent Protection
For each of the 3VMAIN and 12VMAIN supplies, the current
regulated (CR) levels are set by a sub ohm value sense resistor.
The value for 12VMAIN is dependant on the size of the
PCI-Express connector (X1, X4/X8 or X16) to be powered. The
voltage across this resistor is compared to a 50mV internal
reference, providing a nominal CR protection level that would be
set above the maximum specified slot limits. The 3.3VMAIN
supply can use a 15m sense resistor compared to a 50mV
reference to provide a nominal regulated current limit of 3.3A, as
this supply has a common 3A maximum across all slot sizes. For
both MAIN supplies, there is a Way Overcurrent (WOC) shutdown
12
1.28
1.26
1.24
1.22
1.20
-60
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 16. FILTER THRESHOLD VOLTAGE vs TEMPERATURE
protocol that is without a CR duration. WOC is invoked if the load
current causes the RSENSE voltage to be >100mV (see Figures
23 and 24).
VAUX Supply Overcurrent Protection
The VAUX load current is internally monitored and controlled via
an internal power FET. This FET has a typical rDS(ON) of 320mΩ at
a VAUX current of 375mA to minimize distribution losses to
typically <100mV through the IC. Using active monitoring and
control, the ISL6112 provides nominal limiting to ~1000mA of
load current across the temperature range and for various
loading conditions. See Figures 17, 25 and 26 for examples of
this performance.
Current Regulation (CR) Duration
The CR duration for each slot is set by an external capacitor
between the associated CFILTER pin and ground. This feature
masks current transients and overcurrents prior to supply
turn-off. Once the CR duration has expired, the IC quickly turns
off the associated MAIN outputs via its external FETs or the failed
AUX output, unloading the faulted load card from the supply
voltage rails.
UVLO, Power-Good, and FAULT
The ISL6112 incorporates undervoltage lock-out (UVLO)
protections on each of the four MAIN VIN and two VSTBY supplies
to prevent operation during a brown-out condition. Likewise, on
the outputs are minimum voltage compliances that must be
satisfied for the Power-Good output, PWRGD, to be asserted.
There is some hysteresis on the UVLO levels as the voltage on VIN
decreases to ensure IC operation below the minimum operating
supply standards. The FAULT output is asserted (low) whenever
there is an OC, OT or UV condition. The FAULT is cleared once the
appropriate enable is deasserted.
Operational System Interfaces
The ISL6112 employs two system interfaces: the hardware
Hot-Plug Interface (HPI) and the System Management Interface
(SMI). The HPI I/O includes ON, AUXEN, FAULT and PWRGD. The
SMI I/O consists of SDA, SCL, and INT, the signals of which
conform to the levels and timing of the SMBus specification (see
FN6456.1
August 25, 2011
ISL6112
“SMI-only Control Applications” on page 18). The ISL6112 can be
operated exclusively from either the SMI or HPI, or can employ
the HPl for power control while continuing to use the SMI for
access to all but the power control registers.
In addition to the basic power control features of the ISL6112
accessible by the HPI, the SMI gives the host access to the
following information from the part:
• Fault conditions occurring on each supply. These faults include
overcurrent, over-temperature and undervoltage.
• GPI pin status when using the system.
When using the SMI for power control, the HPI must not be used.
Conversely, when using the HPI for power control, power control
commands must not be executed over the SMI bus. All other
register accesses via the SMI bus remain permissible while in HPI
control mode. When using SMI exclusively, the HPI input pins (ON,
AUXEN, and FORCE_ON) should be configured as shown in Figure
27 (disabling HPI when SMI control is used). This configuration
safeguards the power slots if the SMBus communication link is
disconnected for any reason.
When using HPI exclusively, the SMBus (or SMI) will be inactive if
the input pins (SDA, SCL, A0, A1, and A2) are configured as
shown in Figure 27.
12VOUT
VAUX
VAUX
12VGATE
AUXEN
AUXEN
12IOUT
IAUX
CFILTER
IAUX
CGD = 6800pF
CGS = 22nF
FIGURE 17. VAUX TURN-ON RLOAD = 10Ω, CLOAD = 100µF
FIGURE 18. 12VMAIN START-UP RLOAD = 10Ω, CLOAD = 470µF
3VOUT
12VOUT
3VGATE
12VGATE
3IOUT
12IOUT
CFILTER
CFILTER
CFILTER RESPONDING TO UNSHOWN MAIN SUPPLY
CGATE = 22nF
FIGURE 19. 3VMAIN START-UP RLOAD = 2Ω, CLOAD = 470µF
13
CGD = 6800pF
CGS = 2200pF
FIGURE 20. 12VMAIN START-UP RLOAD = 10Ω, CLOAD = 470µF
FN6456.1
August 25, 2011
ISL6112
3VGATE
12VOUT
3VOUT
12VGATE
3IOUT
12IOUT
CFILTER
CFILTER
CFILTER RESPONDING TO UNSHOWN MAIN SUPPLY
CGD = 9800pF
CGS = 2200pF
CGATE = 2200pF
FIGURE 21. 3VMAIN START-UP RLOAD = 2Ω, CLOAD = 470µF
FIGURE 22. 12VMAIN START-UP RLOAD = 10Ω, CLOAD = 470µF
3VGATE
12VGATE
12VOUT
12IOUT
CFILTER
CFILTER
3VOUT
3IOUT
FIGURE 23. 12VMAIN WOC SHUT-DOWN
VAUX
CFILTER
IAUX
FIGURE 24. 3VMAIN WOC SHUT-DOWN
VAUX
CFILTER
IAUX
FIGURE 25. VAUX OC REGULATION AND SHUT-DOWN
14
FIGURE 26. VAUX WOC REGULATION AND SHUT-DOWN
FN6456.1
August 25, 2011
ISL6112
VSTBY
INT
100k
100k
100k
SCL
SDA
INT#
A2
A1
A0
DISABLING SMI WHEN HPI CONTROL IS USED
VSTBY
100k 9
100k 28
45
42
44
43
FORON#_A
FORON#_B
AUXENA
AUXENB
ONA
ONB
DISABLING HPI WHEN SMI CONTROL IS USED
FIGURE 27. I/O CONFIGURATION FOR DISABLING HPI/SMI CONTROL
12VOUT
12VGATE
3IOUT
12IOUT
3VOUT
3VGATE
CFILTER
FIGURE 28. 12VMAIN CR AND SHUT-DOWN
ISL6112 Bias, Power-On Reset, and Power
Cycling
The ISL6112 uses VSTBY as the only supply source. VSTBY is
required for proper operation of the ISL6112 SMBus and
registers and must be applied at all times. A Power-On-Reset
(POR) cycle is initiated after VSTBY rises above its UVLO threshold
and remains satisfied for 250µs. All internal registers are cleared
after POR. If VSTBY is recycled, the ISL6112 enters a new POR
cycle. VSTBY must be the first supply voltage applied, followed by
the MAIN supply inputs of 12VIN and 3VIN. The SMBus is ready
for access at the end of the POR cycle (250µs after VSTBY is
valid). During tPOR, all outputs remain off.
Enabling the VAUX Outputs
Upon asserting an AUXEN input, the related internal power switch
turns on, connecting the nominally 3.3V VSTBY supply to its VAUX
load. The turn-on is slew rate limited and invokes the current
15
CFILTER
FIGURE 29. 3VMAIN CR AND SHUT-DOWN
regulation feature so as not to droop the supply due to in-rush
current load. Figure 17 illustrates the VAUX turn-on performance
into a 10, 100µF load.
Standby Mode
Standby mode is entered when one or more of the MAIN supply
inputs (12VIN and/or 3VIN) is either absent, below its respective
UVLO threshold, or OFF. The ISL6112 also has 3.3V auxiliary
outputs (VAUXA and VAUXB), satisfying an optional PCI-Express
requirement. These outputs are fed from the VSTBY input pins.
They are independent of the MAIN outputs and are controlled by
the AUXEN input pins or via their respective bits in the control
registers. Should the MAIN supply inputs fall below their
respective UVLO thresholds, VAUX still functions, as long as
VSTBY is compliant. Prior to standby mode, ONA and ONB (or the
control register MAINA and MAINB bits) inputs must be
deasserted, or the ISL6112 asserts its FAULT outputs. If an
FN6456.1
August 25, 2011
ISL6112
undervoltage condition on either of the MAIN supply inputs is
detected, INT also asserts, if interrupts are enabled.
Enabling the MAIN GATE Outputs
When a slot's MAIN supplies are off, the 12VGATE pin is held high
with an internal pull-up to the 12VIN voltage. Similarly, the
3VGATE pin is internally held low to GND. When the MAIN
supplies of the ISL6112 are enabled by asserting ON, the related
3VGATE and 12VGATE pins are each connected to a constant
current supply. For the 3VGATE pin, this supply is nominally a
25µA current source. For the 12VGATE pin, the supply is
nominally a -25µA current sink. The 3VGATE is charged up to the
12VIN voltage, while the 12GATE is pulled down to GND, for
maximum enhancement of the N-Channel and P-Channel FETs,
respectively.
Estimating In-Rush Current and VOUT Slew
Rate at Start-Up
The expected in-rush current can be estimated by using
Equation 1:
 C LOAD
I IN – RUSH NOMINALLY = 25A  -----------------
 C GATE 
(EQ. 1)
where 25µA is the GATE pin charge current, and CLOAD is the
load capacitance. CGATE is the total GATE capacitance, including
CISS of the external MOSFET and any external capacitance
connected from the GATE output pin to the GATE reference, GND,
or source.
An estimate for the output slew rate of 3.3V outputs and 12V
outputs, where there is little or no external 12VGATE output
capacitors, can be determined from Equation 2:
I LIM
dv/dt VOUT NOMINALLY = ----------------C LOAD
(EQ. 2)
where ILIM = 50mV/RSENSE and CLOAD is the load capacitance.
As a consequence, the CR duration, tFILTER, must be
programmed to exceed the time it takes to fully charge the
output load to the input rail voltage level.
MAIN Outputs (Start-up Delay and Slew-Rate
Control)
The 3.3V outputs act as source followers. In this mode of
operation, VSOURCE = [VGATE – V TH(ON)] until the associated
output reaches 3.3V. The voltage on the gate of the MOSFET
continues to rise until it reaches 12V, which ensures minimum
rDS(ON). For the 12V outputs, the MOSFET can be optionally
configured as a Miller integrator by adding a CGD capacitor
connected between the MOSFET's gate and drain to adjust the
VOUT ramp time. In this configuration, the feedback action from
drain to gate of the MOSFET causes the voltage at the drain of
the MOSFET to slew in a linear fashion at a rate estimated by
Equation 3:
25A
dv/dt VOUT NOMINALLY = --------------C GD
(EQ. 3)
Table 1 approximates the output slew-rate for various values of
CGATE when start-up is dominated by GATE capacitance (external
16
CGATE from GATE pin to ground, plus CGS of the external MOSFET
for the 3.3V rail and CGD for the 12V rail).
TABLE 1. 3.3V AND 12V OUTPUT SLEW-RATE SELECTION FOR GATE
CAPACITANCE DOMINATED START-UP
| IGATE | = 25µA
CGATE or CGD
dv/dt (load)
0.01µF (Note)
2.5V/ms
0.022µF (Note)
1.136V/ms
0.047µF
0.532 V/ms
0.1µF
0.250V/ms
NOTE: Values in this range are affected by the internal parasitic
capacitances of the MOSFETs used, and should be verified
experimentally.
Note that all of these performance estimates are useful only for
first-order time and loading expectations, because they do not
look at other significant loading factors. Figures 18, 19, 20, 21
and 22 illustrate empirically the discussed turn-on performance
with the noted loading and compensation conditions.
Notice the degree of control over the in-rush current and the
GATE ramp rate as the values are changed, which provides for
highly customizable turn-on characteristics.
In some scope shots, although the CFILTER shows ramping in the
absence of excessive displayed loading current, CFILTER is
responding to the other MAIN supply current that is not
displayed.
All scope shots were taken from the ISL6112EVAL1Z, with any
component changes noted.
Current Regulation (CR) Function
The ISL6112 provides a current regulation and limiting function
that protects the input voltage supplies against excessive loads,
including short circuits. When the current from any slot’s MAIN
outputs exceeds the current limit threshold (ILIM = 50mV/RSENSE)
for a duration greater than tFILTER, the isolation protection is
tripped, and both related MAIN supplies are shut off, as shown in
Figures 28 and 29. Should the load current cause a MAIN output
VSENSE to exceed VTHFAST, the output is immediately shut off, with
no tFILTER delay, as shown in Figures 28 and 29.
The VAUX outputs have a different isolation protection function.
The VAUX isolation circuit does not incorporate a fast-trip
detector; instead, they regulate the output current into a fault to
avoid exceeding their operating current limit. The protection
circuit trips due to an overcurrent on VAUX when the
programmable CR duration timer, tFILTER, expires. This use of the
tFILTER timer prevents the circuit from tripping prematurely due
to brief current transients. See Figures 25 and 26 for illustrations
of the VAUX protection performance into a slight OC and more
severe OC condition, respectively. The ISL6112 AUX current
control responds proportionally to the severity of the OC
condition, resulting in faster VAUX pull-down and current
regulation until tFILTER has expired.
Following a fault condition, the outputs can be turned on again
(1) via the ON inputs if the fault occurred on one of the MAIN
outputs), (2) via the AUXEN inputs if the fault occurred on the AUX
outputs, or (3) by cycling both ON and AUXEN if faults occurred on
FN6456.1
August 25, 2011
ISL6112
both the MAIN and AUX outputs. A fault condition can
alternatively be cleared under SMI control of the ENABLE bits in
the CNTRL registers (see “Control Register Bits D[1:0]” on
page 21). When the circuit protection trips, FAULT is asserted if
the outputs were enabled through the HPI inputs. If SMI is
enabled, INT is asserted (unless interrupts are masked). Note
that INT is deasserted by writing a Logic 1 back into the
respective fault bit positions in the STAT register or the “Common
Status Register (CS) 8-Bits, Read/Write” on page 24.
The ISL6112 current regulation duration (tFILTER) is individually
set for each slot by an external capacitor at the CFILTER pin to
GND. Once the CR mode is entered, the external cap is charged
with a 2.5µA current source to 1.25V. Once this threshold has
been reached, the IC turns off only the related faulted outputs
[either both MAIN (external FETs) outputs or AUX (internal FET)]
and sets the FAULT output low. For a desired tFILTER, the value for
CFILTER is given by Equation 4:
nominal t FILTER
C FILTER = -----------------------------------------500k
(EQ. 4)
where 500kis the nominalVFILTER/nominal IFILTER and where
tFILTER is the desired response time, with the values for IFILTER
and VFILTER being found in the “Electrical Specifications Table”
on page 7. See Table 2 for nominal tFILTER times for given
CFILTER cap values.
TABLE 2. NOMINAL tFILTER DURATION
CFILTER CAPACITANCE (µF)
TIME (ms)
Open
0.01
0.01
5
0.022
11
0.047
24
0.1
50
NOTE: Nominal CR_DUR = CFILTER cap (F) * 500k.
Because the ISL6112 has its CR feature invoked as it turns on the
FETs into the load, tFILTER consideration is minimal. A maximum
bulk capacitance is specified for each supported power level, and it
must be charged at the CR limit. In-rush current time must be
considered when determining tFILTER duration.
Power-Down Cycle
When a slot is turned off under either HPI or SMI control, internal
discharge FETs connected to the output load provide a discharge
path for load capacitance connected to the part’s outputs. These
FETs ensure the outputs are pulled to GND. This is a compliance
requirement if a replacement add-in card is inserted into the slot.
Thermal Shutdown
The internal VAUX MOSFETs are protected against damage not
only by current limiting, but by a dual-mode over-temperature
protection scheme as well. Each slot controller on the ISL6112 is
thermally isolated from the other. Should an overcurrent
condition raise the junction temperature of one slot’s controller
and pass elements to +140°C, all outputs for that slot (including
VAUX) are shut off, and the slot’s FAULT output is asserted. The
other slot’s operating condition remains unaffected. However,
should the ISL6112 die temperature exceed +160°C, both slots
17
(all outputs, including VAUXA and VAUXB) are shut off, whether or
not a current limit condition exists. A +160°C over-temperature
condition additionally sets the over-temperature bit (OT_INT) in
the Common Status Register (see “Common Status Register (CS)
8-Bits, Read/Write” on page 24).
PWRGD Outputs
The ISL6112 has two PWRGD outputs; one for each slot. These
open-drain, active-low outputs require an external pull-up resistor
to VSTBY. Each output is asserted when a slot has been enabled
and has successfully begun delivering power to its respective
+12V, +3.3V, and VAUX outputs. An equivalent logic diagram for
PWRGD is shown in Figure 30.
FORCE_ON Inputs
The level-sensitive, active-low FORCE_ON inputs are provided to
facilitate design or debugging of systems using the ISL6112.
Asserting FORCE_ON turns on all three of the respective slot’s
outputs (12MAIN, 3MAIN, and VAUX), while specifically defeating all
overcurrent and short circuit protections and on-chip thermal
protection for the VAUX supplies. Additionally, asserting FORCE_ON
disables all input and output UVLO protections, with the exception of
the VSTBY input, UVLO.
Asserting FORCE_ON causes the slot PWRGD and FAULT
outputs to enter the open-drain state. Additionally, there are
two SMBus accessible register bits (see Control Register Bit
D[2] in Tables 5 and 7) that can be set to disable the
corresponding slot’s FORCE_ON pins. This allows system
software to prevent these hardware overrides from being
inadvertently activated during normal use. When not used, each
FORCE_ON pin can be connected to VSTBY by using an external
pull-up resistor, or it can simply be shorted to VSTBY.
General Purpose Input (GPI) Pins
Two pins on the ISL6112 are available for use as GPI pins. The logic
state of each of these pins can be determined by polling Bits [4:5] of
the Common Status Register. Both of these inputs are compliant to
3.3V. If GPI is not used, each input must be connected to GND.
Hot-Plug Interface (HPI)
After the input supplies are above their respective UVLO
thresholds, the Hot-Plug Interface can be used for power control
by enabling the control input pins (AUXEN and ON) for each slot.
For the ISL6112 to turn on the VAUX supply for either slot, the
AUXEN control must be enabled after the power-on-reset delay,
tPOR (typically, 250µs), has elapsed.
System Management Interface (SMI)
The ISL6112 System Management Interface (SMI) uses the
Read_Byte and Write_Byte subsets of the SMBus protocols to
communicate with its host via the SMI bus. The INT output
signals the controlling processor that one or more events need
attention, if an interrupt-driven architecture is used. Note that the
ISL6112 does not participate in the SMBus Alert Response
Address (ARA) portion of the SMBus protocol.
FN6456.1
August 25, 2011
ISL6112
AUXEN
VAUX
3VAUX_UV
ON
MAIN
12VOUT_UV
3VOUT_UV
FORCE_ON
FORCE_EN
VSTBY
(1)
(2)
(3)
PWRGD
(1)
(4)
(3)
(1) EXTERNAL PIN
(2) CNTRL REGISTER BIT D[0]
(3)
(3) INTERNAL FLAG
(1)
(4) CNTRL REGISTER BIT D[1]
(5) CNTRL REGISTER BIT D[2]
(5)
FIGURE 30. PWRGD LOGIC DIAGRAM
Fault Reporting and Interrupt Generation
SMI-ONLY CONTROL APPLICATIONS
For applications in which the ISL6112 is controlled only by SMI,
ON and AUXEN are connected to GND, and the FORCE_ON pins
are either shorted or are connected to VSTBY as shown in
Figure 27. In these cases, the ISL6112 FAULT outputs and
STATUS Register Bit D[7] (FAULT) are not activated, because fault
status is determined by polling STATUS Register Bits D[4], D[2],
D[0] and CS (Common Status) Register Bits D[2:1]. Individual
fault bits in the STATUS and CS registers are asserted after POR,
when:
For SMI control applications in which the FORCE_ON inputs are
needed for diagnostic purposes, the FORCE_ON inputs must be
enabled; that is, CNTRL Register Bit D[2] should read Logical “0.”
Once FORCE_ON inputs are asserted, all output voltages are
present with all circuit protection features disabled, including
over-temperature protection on VAUX outputs. To inhibit
FORCE_ON operation, a Logical “1” is written to the CNTRL
Register Bit D[2] locations.
HPI-ONLY CONTROL APPLICATIONS
• Either or both CNTRL Register Bits D[1:0] are asserted, AND
For applications in which the ISL6112 is controlled only by HPI,
SMBus signals SCL, SDA, and INT are connected to VSTBY as
shown in Figure 27. In this configuration, the ISL6112 FAULT
outputs are activated after POR and become asserted when:
• 12VIN, 3VIN, or VSTBY input voltage is lower than its respective
ULVO threshold, OR
Either or both external ON and AUXEN input signals are asserted,
AND
• The fast OC circuit isolation protection has tripped, OR
• 12VIN, 3VIN, or VSTBY input voltage is lower than its respective
ULVO threshold, OR
• The slow OC circuit isolation protection has tripped AND its
filter time-out has expired, OR
• The fast OC circuit isolation protection has tripped, OR
• The slow OC circuit isolation protection has tripped AND Slot
die temperature > +140°C, OR
• The slow OC circuit isolation protection has tripped AND its
filter time-out has expired, OR
• The ISL6112 global die temperature > +160°C
• The slow OC circuit isolation protection has tripped AND slot
die temperature > +140°C, OR
Once asserted, to clear any one or all STATUS Register Bits D[4],
D[2], D[0] or CS Register Bits D[2], D[1], a software subroutine
can perform an “echo reset” in which a Logical “1” is written
back to those register bit locations that have indicated a fault.
This method of “echo reset” allows data to be retained in the
STATUS and/or CS registers until such time as the system is
prepared to operate on that data.
The ISL6112 can operate in interrupt mode or polled mode. For
interrupt-mode operation, the open-drain, active-LOW INT output
signal is activated after POR if the INTMSK bit (CS Register Bit
D[3]) has been reset to Logical “0”. Once activated, the INT
output is asserted by any one of the fault conditions previously
listed. It is deasserted when one or all STATUS Register Bits D[4],
D[2], D[0] or CS Register Bits D[2], D[1] are reset upon the
execution of an SMBus “echo reset” WRITE_BYTE cycle. For
polled-mode operation, the INTMSK bit should be set to Logical
“1,” thereby inhibiting INT output pin operation.
18
• The ISL6112 global die temperature > +160°C.
To clear FAULT outputs, once asserted, either or both ON and
AUXEN input signals must be deasserted. (See FAULT pin in “Pin
Descriptions” table on page 4 for additional information.) If the
FORCE_ON inputs are used for diagnostic purposes, both the
FAULT and PWRGD outputs are deasserted after the FORCE_ON
inputs are asserted.
Serial Port Operation
The ISL6112 uses standard SMBus Write_Byte and Read_Byte
operations for communication with its host. The SMBus
Write_Byte operation involves sending the device’s target
address, with the R/W bit (LSB) set to the low (write) state,
followed by a command byte and a data byte. The SMBus
Read_Byte operation is similar, but it is a composite write and
read operation. The host first sends the device’s target address,
followed by the command byte, as in a write operation. A new
FN6456.1
August 25, 2011
ISL6112
“Start” bit must then be sent to the ISL6112, followed by a repeat
of the device address, with the R/W bit set to the high (read)
state. The data to be read from the part may then be clocked out.
The exception to this rule is that, if the location latched in the
pointer register from the last write operation is known to be
correct (i.e., points to the desired register within the ISL6112),
the “Receive_Byte” procedure may be used. To perform a
Receive_Byte operation, the host sends an address byte to select
the target ISL6112, with the R/W bit set to the high (read) state,
and then retrieves the data byte. Figures 33, 34 and 35 show the
formats for these data read and data write procedures.
The Command Register is eight bits (one byte) wide. This byte
carries the address of the ISL6112 register to be operated upon.
Command byte values corresponding to the ISL6112 register
addresses are shown in Table 4. Command byte values other than
0000 0XXXb = 00h – 07h are reserved and should not be used.
ISL6112 SMBus Address Configuration
The ISL6112 responds to its own unique SMBus address, which
is assigned using A2, A1, and A0. These represent the three
Least Significant Bits (LSB) of its 7-bit address, as shown in
Table 3. These address bits are assigned only during power-up of
the VSTBY supply input. These address bits allow up to eight
ISL6112 devices in a single system. These pins are either
grounded or left unconnected to specify a logical 0 or logical 1,
respectively. A pin designated as a logical 1 may also be pulled
up to VSTBY.
TABLE 3. ISL6112 SMBUS ADDRESSING
INPUTS
ISL6112 DEVICE ADDRESS
A2
A1
A0
BINARY
HEX
0
0
0
1000 000X*b
80h
0
0
1
1000 001Xb
82h
0
1
0
1000 010Xb
84h
0
1
1
1000 011Xb
86h
1
0
0
1000 100Xb
88h
1
0
1
1000 101Xb
8Ah
1
1
0
1000 110Xb
8Ch
1
1
1
1000 111Xb
8Eh
* Where X = “1” for READ and “0” for WRITE
19
FN6456.1
August 25, 2011
ISL6112
Timing Diagrams
SCL
t5
t2
t4
SDA
DATA IN
t3
SDA
DATA OUT
FIGURE 31. SMBUS TIMING
+3.3V
UVLO
VSTBY
VIH
AUXEN
VIH
VIL
0
tPOR
VAUX_OUT
0
ILIM(AUX)
tFLT
ISTEADY-STATE
I
AUX_OUT
0
VIH
ON
VIH
VIL
0
12VOUT
0
3VOUT
0
PWRGD_
0
ILIM(3V)
tFLT
ISTEADY-STATE
0
I3VOUT
FAULT_
0
INT*
*
*
0
* INT DE-ASSERTED BY SOFTWARE
FIGURE 32. HOT-PLUG INTERFACE OPERATION
ISL6112 DEVICE ADDRESS
DATA
COMMAND BYTE TO ISL6112
DATA BYTE TO ISL6112
S 1 0 0 0 A2 A1 A0 0 A 0 0 0 0 0 X X X A D7 D6 D5 D4 D3 D2 D1 D0 A P
START
R/W = WRITE
ACKNOWLEDGE ACKNOWLEDGE
ACKNOWLEDGE
CLK
MASTER TO DEVICE TRANSFER,
i.e., DATA DRIVEN BY MASTER.
DEVICE TO MASTER TRANSFER,
i.e., DATA DRIVEN BY DEVICE.
FIGURE 33. WRITE_BYTE PROTOCOL
20
FN6456.1
August 25, 2011
ISL6112
Timing Diagrams
(Continued)
ISL6112 DEVICE ADDRESS
DATA
COMMAND BYTE TO ISL6112
ISL6112 DEVICE ADDRESS
DATA READ FROM ISL6112
S 1 0 0 0 A2 A1 A0 0 A 0 0 0 0 0 X X X A S 1 0 0 0 A2 A1 A0 1 A D7 D6 D5 D4 D3 D2 D1 D0 /A P
R/W = WRITE ACKNOWLEDGE ACKNOWLEDGE START
START
R/W = READ ACKNOWLEDGE NOT ACKNOWLEDGE
CLK
MASTER TO DEVICE TRANSFER,
i.e., DATA DRIVEN BY MASTER.
DEVICE TO MASTER TRANSFER,
i.e., DATA DRIVEN BY DEVICE.
FIGURE 34. READ_BYTE PROTOCOL
ISL6112 DEVICE ADDRESS
DATA
BYTE READ FROM ISL6112
S 1 0 0 0 A2 A1 A0 1 A D7 D6 D5 D4 D3 D2 D1 D0 /A P
START
R/W = READ
ACKNOWLEDGE NOT ACKNOWLEDGE STOP
CLK
MASTER TO DEVICE TRANSFER,
i.e., DATA DRIVEN BY MASTER.
DEVICE TO MASTER TRANSFER,
i.e., DATA DRIVEN BY DEVICE.
FIGURE 35. RECEIVE_BYTE PROTOCOL
ISL6112 Register Set and Programmer’s Model
TABLE 4. ISL6112 REGISTER ADDRESSES
TARGET REGISTER
LABEL
COMMAND BYTE VALUE
DESCRIPTION
READ
WRITE
POWER-ON
DEFAULT
CNTRLA
Control Register Slot A
02h
02h
00h
CNTRLB
Control Register Slot B
03h
03h
00h
STATA
Slot A Status
04h
04h
00h
STATB
Slot B Status
05h
05h
00h
CS
Common Status Register
06h
06h
xxxx 0000b
Reserved
Reserved/Do Not Use
07h - FFh
07h - FFh
Undefined
Detailed Register Descriptions
Control Register, Slot A (CNTRLA) 8-Bits, Read/Write
TABLE 5. CONTROL REGISTER, SLOT A (CNTRLA)
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
read-only
read-only
read-only
read-only
read-only
read/write
read/write
read/write
AUXAPG
MAINAPG
Reserved
Reserved
Reserved
FORCE_A
ENABLE
MAINA
VAUXA
BIT(s)
FUNCTION
OPERATION
AUXAPG
AUX output power-good status, Slot A
1 = Power-is-Good (VAUXA Output is above its UVLO threshold)
MAINAPG
MAIN output power-good status, Slot A
1 = Power-is-Good (MAINA Outputs are above their UVLO
thresholds)
D[5]
Reserved
Always read as zero
D[4]
Reserved
Always read as zero
21
FN6456.1
August 25, 2011
ISL6112
BIT(s)
FUNCTION
OPERATION
D[3]
Reserved
Always read as zero
FORCE_A
ENABLE
Allows or inhibits the operation of the FORCE_ONA input pin
0 = FORCE_ONA is enabled
1 = FORCE_ONA is disabled
MAINA
MAIN enable control, Slot A
0 = OFF, 1 = ON
VAUXA
VAUX enable control, Slot A
0 = OFF, 1 = ON
0000 0000b = 00h
0000 0010b = 02h
Power-Up Default Value:
Read Command_Byte Value (R/W):
The power-up default value is 00h. Slot is disabled upon power-up; i.e., all supply outputs are off.
NOTES:
8. The state of the PWRGDA pin is the logical AND of the values of the AUXAPG and the MAINAPG bits, except when FORCE_ONA is asserted. If
FORCE_ONA is asserted (the pin is pulled low), and FORCE_AENABLE is set to a logic zero, the PWRGDA pin will be unconditionally forced to its
open-drain (“Power Not Good”) state.
9. The values of the MAINAPG and AUXAPG register bits are not affected by FORCE_ONA, but will instead continue to read as high if power is “Good,”
and as low if the conditions that indicate power is good are not met.
Status Register Slot A (STATUSA) 8-Bits, Read-Only
TABLE 6. STATUS REGISTER, SLOT A (STATA)
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
read-only
read-only
read-only
read/write
read-only
read/write
read-only
read/write
FAULTA
MAINA
VAUXA
VAUXAF
Reserved
12VAF
Reserved
3VAF
BIT(s)
FUNCTION
OPERATION
FAULTA
FAULT Status - Slot A
1 = Fault pin asserted (FAULTA pin is LOW); 0 = Fault pin
deasserted (FAULTA pin is HIGH). See Notes 10, 11, and 12.
MAINA
MAIN Enable Status - Slot A
Represents the actual state (on/off) of the two Main Power
outputs for Slot A (+12V and +3.3V). 1 = Main Power ON;
0 = Main Power OFF
VAUXA
VAUX Enable Status - Slot A
Represents the actual state (on/off) of the Auxiliary Power
output for Slot A. 1 = AUX Power ON; 0 = AUX Power OFF
VAUXAF
Overcurrent Fault: VAUXA supply
1 = Fault; 0 = No fault
D[3]
Reserved
Always read as zero
12VAF
Overcurrent Fault: +12V supply
1 = Fault; 0 = No fault
D[1]
Reserved
Always read as zero
3VAF
Overcurrent Fault: 3.3V supply
1 = Fault; 0 = No fault
22
FN6456.1
August 25, 2011
ISL6112
BIT(s)
FUNCTION
Power-Up Default Value:
Command_Byte Value (R/W):
OPERATION
0000 0000b = 00h
0000 0100b = 04h
The power-up default value is 00h. Both slots are disabled upon power-up; i.e., all supply outputs are off. In response to an overcurrent fault condition,
writing a Logical 1 back into the active (or set) bit position will clear the bit and deassert INT. The status of the FAULTA pin is not affected by reading
the Status Register or by clearing active status bits.
NOTES:
10. If FAULTA has been set by an overcurrent condition on one or more of the MAIN outputs, the ONA input must go LOW to reset FAULTA. If FAULTA has
been set by a VAUXA overcurrent event, the AUXENA input must go LOW to reset FAULTA. If an overcurrent has occurred on both a MAIN output and
the VAUX output of slot A, both ONA and AUXENA of the slot must go low to reset FAULTA.
11. Neither the FAULTA bits nor the FAULTA pins are active when the ISL6112 power paths are controlled by SMI. When using SMI power path control,
AUXENA and ONA pins for that slot must be tied to GND.
12. If FORCE_ONA is asserted (low), the FAULTA pin will be unconditionally forced to its open-drain state. Note that the value in the FAULTA register bit
is not affected by FORCE_ONA. It will instead continue to read as a high if no faults are present on Slot A, and as a low if any fault conditions exist
that would disable Slot A if FORCE_ONA was not asserted.
Control Register, Slot B (CNTRLB) 8-Bits, Read/Write
TABLE 7. CONTROL REGISTER, SLOT B (CNTRLB)
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
read-only
read-only
read-only
read-only
read-only
read/write
read/write
read/write
AUXBPG
MAINBPG
Reserved
Reserved
Reserved
FORCE_B
ENABLE
MAINB
VAUXB
BIT(s)
FUNCTION
OPERATION
AUXBPG
AUX output power-good status, Slot B
1 = Power-is-Good (VAUXB Output is above its UVLO threshold)
MAINBPG
MAIN output power-good status, Slot B
1 = Power-is-Good (MAINB Outputs are above their UVLO
thresholds)
D[5]
Reserved
Always read as zero
D[4]
Reserved
Always read as zero
D[3]
Reserved
Always read as zero
FORCE_B
ENABLE
Allows or inhibits the operation of the FORCE_ONB input pin
0 = FORCE_ONB is enabled
1 = FORCE_ONB is disabled
MAINB
MAIN enable control, Slot B
0 = OFF, 1 = ON
VAUXB
VAUX enable control, Slot B
0 = OFF, 1 = ON
0000 0000b = 00h
0000 0011b = 03h
Power-Up Default Value:
Command_Byte Value (R/W):
The power-up default value is 00h. Slot is disabled upon power-up; i.e., all supply outputs are off.
NOTES:
13. The state of the PWRGDB pin is the logical AND of the values of the AUXBPG and MAINBPG bits, except when FORCE_ONB is asserted. If
FORCE_ONB is asserted (the pin is pulled low), and FORCE_BENABLE is set to a logic zero, the PWRGDB pin will be unconditionally forced to its
open-drain (“Power Not Good”) state.
14. The values of the MAINBPG and AUXBPG register bits are not affected by FORCE_ONB, but will instead continue to read as high if power is “Good,”
and as low if the conditions, which indicate that power is good, are not met.
23
FN6456.1
August 25, 2011
ISL6112
Status Register Slot B (STATB) 8-Bits, Read-Only
TABLE 8. STATUS REGISTER, SLOT B (STATB)
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
read-only
read-only
read-only
read/write
read-only
read/write
read-only
read/write
FAULTB
MAINB
VAUXB
VAUXBF
Reserved
12VBF
Reserved
3VBF
BIT(s)
FUNCTION
OPERATION
FAULTB
FAULT Pin Status - Slot B
1 = Fault pin asserted (FAULTB pin is LOW); 0 = Fault pin
deasserted (FAULTB pin is HIGH). See Notes 15, 16, and
17.
MAINB
MAIN Enable Status - Slot B
Represents the actual state (on/off) of the four Main
Power outputs for Slot B (+12V and +3.3V):
1 = MAIN Power ON
0 = MAIN Power OFF
VAUXB
VAUX Enable Status - Slot B
Represents the actual state (on/off) of the Auxiliary Power
output for Slot B:
1 = AUX Power ON
0 = AUX Power OFF
VAUXBF
Overcurrent Fault: VAUXB supply
1 = Fault; 0 = No fault
D[3]
Reserved
Always read as zero
12VBF
Overcurrent Fault: +12V supply
1 = Fault; 0 = No fault
D[1]
Reserved
Always read as zero
3VBF
Over current Fault: 3.3V supply
1 = Fault; 0 = No fault
Power-Up Default Value:
Command_Byte Value (R/W):
0000 0000h = 00h
0000 0101b = 05h
The power-up default value is 00h. Both slots are disabled upon power-up; i.e., all supply outputs are off. In response to an overcurrent fault condition,
writing a logical 1 back into the active (or set) bit position will clear the bit and deassert INT. The status of the FAULTB pin is not affected by reading the
Status Register or by clearing active status bits.
NOTES:
15. If FAULTB has been set by an overcurrent condition on one or more of the MAIN outputs, the ONB input must go LOW to reset FAULTB. If FAULTB
has been set by a VAUXB overcurrent event, the AUXENB input must go LOW to reset FAULTB. If an overcurrent has occurred on both a MAIN output
and the VAUX output of Slot B, both ONB and AUXENB of the slot must go low to reset FAULTB.
16. Neither the FAULTB bits nor the FAULTB pins are active when the ISL6112 power paths are controlled by SMI. When using SMI power path control,
the AUXENB and ONB pins for that slot must be tied to GND.
17. If FORCE_ONB is asserted (low), the FAULTB pin will be unconditionally forced to its open-drain state. Note that the value in the FAULTB register bit
is not affected by FORCE_ONB, but will instead continue to read as a high if no faults are present on Slot B, and as a low if any fault conditions exist
that would disable Slot B if FORCE_ONB was not asserted.
Common Status Register (CS) 8-Bits, Read/Write
TABLE 9. COMMON STATUS REGISTER (CS)
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
read-write
read-write
read-only
read-only
read-write
read-write
read-write
read-only
Reserved
Reserved
GPI_B0
GPI_A0
INTMSK
UV_INT
OT_INT
Reserved
BIT(s)
FUNCTION
OPERATION
D[7]
Reserved
Always read as zero
D[6]
Reserved
Always read as zero
24
FN6456.1
August 25, 2011
ISL6112
BIT(s)
FUNCTION
OPERATION
GPI_B0
General Purpose Input 0, Slot B
State of GPI_B0 pin
GPI_A0
General Purpose Input 0, Slot A
State of GPI_A0 pin
INTMSK
Interrupt Mask
0 = INT generation is enabled
1 = INT generation is disabled
The ISL6112 does not participate in the SMBus Alert
Response Address (ARA) protocol.
UV_INT
Undervoltage Interrupt
0 = No UVLO fault
1 = UVLO fault
Set whenever a circuit isolation protection fault condition
occurs as a result of an undervoltage lockout condition on one
of the main supply inputs. This bit is only set if a UVLO
condition occurs while the ON pin is asserted or the MAIN
control bits are set.
OT_INT
Over-temperature Interrupt
0 = Die Temp < +160°C.
1 = Fault: Die Temp > +160°C.
Set if a fault occurs as a result of the ISL6112 die temperature
exceeding +160°C.
D[0]
Reserved
Undefined
Power-Up Default Value:
Command_Byte Value (R/W):
00000000b = 00h
00000110b = 06h
NOTE: To reset the OT_INT and UV_INT fault bits, a logical 1 must be written back to these bits.
PCI-Express Application
Recommendations
For each of the 3.3VMAIN and +12VMAIN supplies, the CR level
is set by an external sense resistor value. This value depends on
the maximum power specified for the PCI-Express connector and
the application (X1, 10W or 25W; X4, X8, 25W; X16, 25W or
75W; and X16 Graphics -ATX, 150W). The power rating is a
combination of the main and the optional auxiliary supplies. The
sense resistor is a low ohmic, standard value current sense
resistor (one for each slot). The voltage across this resistor is
compared to a 50mV reference. The 3.3VMAIN supply is rated for
3A maximum across all slots, regardless of size and power. The
use of a 15m sense resistor compared to the 50mV reference
provides a nominal CR of 3.3A, or 11% higher than the 3A
maximum specification.
On the 12VMAIN, for a 10W connector, a 75m sense resistor
provides a nominal CR level of 0.66A, 32% above the 0.5A
maximum specification. For a 25W connector, a 20m sense
resistor provides a nominal CR level of 2.5A, which is 19% above
the 2.1A maximum specification. For a 75W connector, an 8m
sense resistor provides a nominal CR level of 6.25A, or 14%
above the 5.5A maximum specification. The X16 Graphics-ATX
150W card is a special case. The 150W is provided by two slots,
each providing up to a maximum of 75W from the 12VMAIN, as
this type of card does not consume 3.3VMAIN or AUX supply
power. For each of the slots, a 7m sense resistor provides a
nominal CR level of 7.1A, which is 14% above the 6.25A
maximum specification.
parameter. Table 10 shows recommended 12VMAIN sense
resistor values for particular power levels.
TABLE 10. NOMINAL CURRENT REGULATION LEVEL
12VMAIN RSENSE
(mΩ)
12VMAIN
CR (A)
PCI-E ADD-IN BOARD POWER
LEVEL SUPPORTED (W)
75
0.7
10
20
2.5
25
8
6.2
75
7
7
150
NOTE: CR Level = VTHILIMIT/RSENSE.
Providing a nominal CR protection level above the maximum
specified limits of the card ensures that the card is able to draw
its maximum specified loads. It also ensures enough headroom
before a regulated current limiter is invoked to protect against
transients and other events. This headroom margin can be
adjusted up or down by using different sense resistor values.
The ISL6112 provides a best-in-class ±5% current regulation
threshold specification over temperature for the MAIN supplies.
This is the highest accuracy and lowest variability for this critical
25
FN6456.1
August 25, 2011
ISL6112
Using the ISL6112EVAL1Z
Platform
The ISL6112EVAL1Z is provided in HPI mode, with the clock
shorted to ground.
The primary ISL6112 evaluation platform is shown
photographically in Figure 36 and schematically on page 28. This
evaluation board highlights a PCB layout that confines all
necessary active and passive components in an area measuring
12mmx55mm. This width is smaller than the specified
PCI-Express socket-to-socket spacing, allowing for intimate
co-location of the load power control and the load itself.
Around the central highlighted layout are numerous labeled test
points and configuration jumpers where there are node names
such as AO(L/R). The pin name outside the parentheses relates
to the ISL6112. The ISL6113 and ISL6114 also use this
evaluation platform, as all three parts have a common pinout for
the common pin functions. The pin names in parentheses are for
the ISL6113 and ISL6114. The specific evaluation board ordered
and received will reflect the part number in the area below the
Intersil logo, either by label or silk-screened lettering. For pins
that are not common across the ISL6112, ISL6113, and
ISL6114, there is a matrix detailing the differences in the bottom
left corner.
The evaluation platform is to be biased through the six banana
jacks: turn on the VSTBY supply first, and then the other MAIN
supplies, in any order. With appropriate signaling to the AUXEN
and ON inputs, the user should see turn-on waveforms. External
current loading must be added to demonstrate OC and WOC
response performance.
The SCL and SDA inputs in the top right quadrant of the
evaluation board can be used to demonstrate SMI operation. The
board’s default address is configured as ‘000’ via three jumpers
located on the right side of the board and labeled A0, A1, and A2.
The HPI inputs must be disabled as shown in Figure 27. If
additional software is needed to configure and control, there is a
LabView based program available from Intersil for demonstration
of the ISL6112 functionality. User lab test hardware and
instrument support is not available.
CAUTION: The ISL6112EVAL1Z gets very hot to the touch after
operating for a few minutes. The hottest areas are marked on the
evaluation board.
CAUTION HOT
SDA
GND
SMI
ADDRESS
CAUTION HOT
SCL
CAUTION HOT
FIGURE 36. ISL6112EVAL1Z BOARD PHOTO
26
FN6456.1
August 25, 2011
ISL6112
TABLE 11. ISL6112EVAL1Z BOARD COMPONENTS LISTING
COMPONENT DESIGNATOR
U1
COMPONENT FUNCTION
COMPONENT DESCRIPTION
ISL6112
PCI-Express Dual Slot Hot Plug Controller
Q1, Q4
Voltage Rail Switches
SI4405DY or equivalent, P-Channel MOSFET
Q2, Q3
Voltage Rail Switches
SI4820DY or equivalent, N-Channel MOSFET
R1, R3, R6, R8
Current Sense Resistor
0.020 1%, 2512
Pull-up Resistors on FORCEON and GPI Inputs
100k, 0201
I/O Pull-up resistors
10k, 0201
R2, R4, R5, R7
FET Gate Series Resistance
15, 0201
C1, C7, C8, C13
FET Gate Capacitance
22nF 10%, 16V, 0402
MAIN and VSTBY Decoupling Capacitance
1µF 10%, 6.3V, 0402
P-FET Gate To Drain Capacitance
6.8nF 10%, 6.3V, 0201
CFILTER Capacitance (5ms)
0.01µF 10%, 6.3V, 0201
R24, R25
AUX Load Resistance
10W 20%, 3W
C17, C18
AUX Load Capacitance
100µF 20%, 25V, Radial Electrolytic
R22, R26, R28, 29
12MAIN Load Resistance
20W 20%, 10W
R23, R27
3MAIN Load Resistance
2W 20%, 10W
12MAIN and 3MAIN Load Capacitance
470µF 20%, 16V, Radial Electrolytic
R9, R10, R17, R20
R11, R12, R13, 14, R15, R16, R18, 19, R21
C3, C5, C6, C10, C11, C14
C2, C12
C4, C9
C15, C16, C19, C20
27
FN6456.1
August 25, 2011
28
ISL6112
FN6456.1
August 25, 2011
ISL6112
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest revision.
DATE
REVISION
CHANGE
7/12/2011
FN6456.1
• Changed title from “Dual Slot PCI-Express Power Controller" to "Dual Slot PCI-Express Hot Plug Controller".
• Removed retired parts ISL6112INZA and ISL6112INZA-T* from Ordering Information. Removed package
outline drawing, pin configuration diagram, and thermal information for TQFP package used for retired
parts.
9/30/2007
FN6456.0
Initial Release
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page
on intersil.com: ISL21400
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff
FITs are available from our website at: http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
29
FN6456.1
August 25, 2011
ISL6112
Package Outline Drawing
L48.7x7
48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 5, 4/10
4X 5.5
7.00
A
44X 0.50
B
37
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
48
1
7.00
36
4. 30 ± 0 . 15
12
25
(4X)
0.15
13
24
0.10 M C A B
48X 0 . 40± 0 . 1
TOP VIEW
4 0.23 +0.07 / -0.05
BOTTOM VIEW
SEE DETAIL "X"
( 6 . 80 TYP )
(
0.10 C
BASE PLANE
0 . 90 ± 0 . 1
4 . 30 )
C
SEATING PLANE
0.08 C
SIDE VIEW
( 44X 0 . 5 )
C
0 . 2 REF
5
( 48X 0 . 23 )
( 48X 0 . 60 )
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
30
FN6456.1
August 25, 2011
Similar pages