DATASHEET

ISL8840AMZ, ISL8841AMZ, ISL8842AMZ,
ISL8843AMZ, ISL8844AMZ, ISL8845AMZ
Data Sheet
December 1, 2011
High Performance Industry Standard
Single-Ended Current Mode PWM
Controller
FN6792.1
Features
• Full Mil-Temp Electrical Performance from -55°C to +125°C
The ISL884xAMBEPZ is a high performance drop-in
replacement for the popular 28C4x and 18C4x PWM
controllers suitable for a wide range of power conversion
applications including boost, flyback, and isolated output
configurations. Its fast signal propagation and output
switching characteristics make this an ideal product for
existing and new designs.
Features include 30V operation, low operating current, 90µA
start-up current, adjustable operating frequency to 2MHz,
and high peak current drive capability with 20ns rise and fall
times.
• Controlled Baseline with One Wafer Fabrication Site and
One Assembly/Test Site
• Full Homogenous Lot Processing in Wafer Fab
• No Combination of Wafer Fabrication Lots in Assembly
• Full Traceability Through Assembly and Test by
Date/Trace Code Assignment
• Enhanced Process Change Notification
• Enhanced Obsolescence Management
• Eliminates Need for Up-Screening a COTS Component
• 1A MOSFET Gate Driver
PART NUMBER
RISING UVLO
(V)
MAX. DUTY CYCLE
(%)
ISL8840AMBEPZ
7.0
100
ISL8841AMBEPZ
7.0
50
• Fast Transient Response with Peak Current Mode Control
ISL8842AMBEPZ
14.4
100
• 30V Operation
ISL8843AMBEPZ
8.4
100
• Adjustable Switching Frequency to 2MHz
ISL8844AMBEPZ
14.4
50
• 20ns Rise and Fall Times with 1nF Output Load
ISL8845AMBEPZ
8.4
50
• Trimmed Timing Capacitor Discharge Current for Accurate
Deadtime/Maximum Duty Cycle Control
• 90µA Start-up Current, 125µA Maximum
• 35ns Propagation Delay Current Sense to Output
• 1.5MHz Bandwidth Error Amplifier
Pinout
ISL884XAMBEPZ
(8 LD SOIC)
TOP VIEW
8 VREF
COMP 1
FB 2
7 VDD
CS 3
6 OUT
RTCT 4
5 GND
• Tight Tolerance Voltage Reference Over Line, Load and
Temperature
• ±3% Current Limit Threshold
• Pb-Free (RoHS compliant)
Applications
• Isolated Flyback and Forward Regulators
• Boost Regulators
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2008, 2011. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL8840AMZ, ISL8841AMZ, ISL8842AMZ, ISL8843AMZ, ISL8844AMZ, ISL8845AMZ
Ordering Information
PART NUMBER
(Notes 1, 2)
PART
MARKING
TEMP RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL8840AMBEPZ
8840A MBEPZ
-55 to +125
8 Ld SOIC
M8.15
ISL8841AMBEPZ
8841A MBEPZ
-55 to +125
8 Ld SOIC
M8.15
ISL8842AMBEPZ
8842A MBEPZ
-55 to +125
8 Ld SOIC
M8.15
ISL8843AMBEPZ
8843A MBEPZ
-55 to +125
8 Ld SOIC
M8.15
ISL8844AMBEPZ
8844A MBEPZ
-55 to +125
8 Ld SOIC
M8.15
ISL8845AMBEPZ
8845A MBEPZ
-55 to +125
8 Ld SOIC
M8.15
NOTES:
1. Add “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD020.
2
FN6792.1
December 1, 2011
Functional Block Diagram
+
-
VREF
VREF
5.00V
START/STOP
UV COMPARATOR
ENABLE
VDD OK
VREF FAULT
+
VREF
UV COMPARATOR
GND
2.5V
A
4.65V
4.80V
+-
3
+-
A = 0.5
PWM
COMPARATOR
+-
CS
100mV
2R
1.1V
CLAMP
+
-
FB
VF TOTAL = 1.15V
ERROR
AMPLIFIER
+
-
ONLY
ISL8841AMBEPZ/
ISL8844AMBEPZ/
ISL8845AMBEPZ
R
Q
T
COMP
Q
OUT
S Q
36k
R Q
RESET
DOMINANT
VREF
100k
2.9V
1.0V
ON
150k
OSCILLATOR
COMPARATOR
<10ns
+
RTCT
8.4mA
FN6792.1
December 1, 2011
ON
CLOCK
ISL8840AMZ, ISL8841AMZ, ISL8842AMZ, ISL8843AMZ, ISL8844AMZ, ISL8845AMZ
VDD
ISL8840AMZ, ISL8841AMZ, ISL8842AMZ, ISL8843AMZ, ISL8844AMZ, ISL8845AMZ
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . GND -0.3V to +30V
OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to VDD + 0.3V
Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to 6.0V
Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1A
Thermal Resistance (Note 4)
θJA (°C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Supply Voltage Range (Note 3) . . . . . . . . . . . . . . . . . . . . . 9V to 30V
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
3. All voltages are with respect to GND.
4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Technical Brief TB379 for details.
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram” on page 3.
VDD = 15V, Rt = 10kΩ, Ct = 3.3nF, TA = -55 to +125°C, Typical values are at TA = +25°C. Parameters with MIN
and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
START Threshold (ISL8840AMBEPZ,
ISL8841AMBEPZ)
6.5
7.0
7.5
V
START Threshold (ISL8843AMBEPZ,
ISL8845AMBEPZ)
8.0
8.4
9.0
V
13.3
14.3
15.3
V
STOP Threshold (ISL8840AMBEPZ,
ISL8841AMBEPZ)
6.1
6.6
6.9
V
STOP Threshold (ISL8843AMBEPZ,
ISL8845AMBEPZ)
7.3
7.6
8.0
V
STOP Threshold (ISL8842AMBEPZ,
ISL8844AMBEPZ)
8.0
8.8
9.6
V
Hysteresis (ISL8840AMBEPZ, ISL8841AMBEPZ)
-
0.4
-
V
Hysteresis (ISL8843AMBEPZ, ISL8845AMBEPZ)
-
0.8
-
V
UNDERVOLTAGE LOCKOUT
START Threshold (ISL8842AMBEPZ,
ISL8844AMBEPZ)
(Note 7)
Hysteresis (ISL8842AMBEPZ, ISL8844AMBEPZ)
-
5.4
-
V
Start-up Current, IDD
VDD < START Threshold
-
90
125
µA
Operating Current, IDD
(Note 5)
-
2.9
4.0
mA
Operating Supply Current, ID
Includes 1nF GATE loading
-
4.75
5.5
mA
REFERENCE VOLTAGE
Overall Accuracy
Over line (VDD = 12V to 30V), load,
temperature
4.900
5.000
5.050
V
Long Term Stability
TA = +125°C, 1000 hours (Note 6)
-
5
-
mV
-20
-
-
mA
5
-
-
mA
-1.0
-
1.0
µA
Current Limit, Sourcing
Current Limit, Sinking
CURRENT SENSE
Input Bias Current
VCS = 1V
CS Offset Voltage
VCS = 0V (Note 6)
95
100
105
mV
COMP to PWM Comparator Offset Voltage
VCS = 0V (Note 6)
0.80
1.15
1.30
V
0.97
1.00
1.03
V
Input Signal, Maximum
4
FN6792.1
December 1, 2011
ISL8840AMZ, ISL8841AMZ, ISL8842AMZ, ISL8843AMZ, ISL8844AMZ, ISL8845AMZ
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram” on page 3.
VDD = 15V, Rt = 10kΩ, Ct = 3.3nF, TA = -55 to +125°C, Typical values are at TA = +25°C. Parameters with MIN
and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested (Continued)
PARAMETER
TEST CONDITIONS
Gain, ACS = ΔVCOMP/ΔVCS
0 < VCS < 910mV, VFB = 0V
CS to OUT Delay
MIN
TYP
MAX
UNITS
2.5
3.0
3.5
V/V
-
35
60
ns
ERROR AMPLIFIER
Open Loop Voltage Gain
(Note 6)
60
90
-
dB
Unity Gain Bandwidth
(Note 6)
1.0
1.5
-
MHz
Reference Voltage
VFB = VCOMP
2.460
2.500
2.535
V
FB Input Bias Current
VFB = 0V
-1.0
-0.2
1.0
µA
COMP Sink Current
VCOMP = 1.5V, VFB = 2.7V
1.0
-
-
mA
COMP Source Current
VCOMP = 1.5V, VFB = 2.3V
-0.4
-
-
mA
COMP VOH
VFB = 2.3V
4.80
-
VREF
V
COMP VOL
VFB = 2.7V
0.4
-
1.0
V
PSRR
Frequency = 120Hz, VDD = 12V to
30V (Note 6)
60
80
-
dB
Frequency Accuracy
Initial, TA = +25°C
48
51
53
kHz
Frequency Variation with VDD
TA = +25°C, (f30V - f10V)/f30V
-
0.2
1.0
%
OSCILLATOR
Temperature Stability
(Note 6)
-
-
5
%
Amplitude, Peak-to-Peak
Static Test
-
1.75
-
V
RTCT Discharge Voltage (Valley Voltage)
Static Test
-
1.0
-
V
Discharge Current
RTCT = 2.0V
6.2
8.0
8.5
mA
VDD - OUT, IOUT = -200mA
-
1.0
2.0
V
Gate VOL
OUT - GND, IOUT = 200mA
-
1.0
2.0
V
Peak Output Current
COUT = 1nF (Note 6)
-
1.0
-
A
Rise Time
COUT = 1nF (Note 6)
-
20
40
ns
Fall Time
COUT = 1nF (Note 6)
-
20
40
ns
GATE VOL UVLO Clamp Voltage
VDD = 5V, ILOAD = 1mA
-
-
1.2
V
OUTPUT
Gate VOH
PWM
Maximum Duty Cycle
(ISL8840AMBEPZ, ISL8842AMBEPZ,
ISL8843AMBEPZ)
COMP = VREF
94.0
96.0
-
%
Maximum Duty Cycle
(ISL8841AMBEPZ, ISL8844AMBEPZ,
ISL8845AMBEPZ)
COMP = VREF
47.0
48.0
-
%
Minimum Duty Cycle
COMP = GND
-
-
0
%
NOTES:
5. This is the VDD current consumed when the device is active but not switching. Does not include gate drive current.
6. Limits established by characterization and are not production tested.
7. Adjust VDD above the start threshold and then lower to 15V.
5
FN6792.1
December 1, 2011
ISL8840AMZ, ISL8841AMZ, ISL8842AMZ, ISL8843AMZ, ISL8844AMZ, ISL8845AMZ
Typical Performance Curves
1.001
NORMALIZED VREF
NORMALIZED FREQUENCY
1.01
1.00
0.99
1.000
0.999
0.998
0.997
0.996
0.98
-60 -40 -20
0
20
40
60
80
0.995
-60 -40
100 120 140
TEMPERATURE (°C)
20
40
60
80 100 120 140
FIGURE 2. REFERENCE VOLTAGE vs TEMPERATURE
103
1.001
FREQUENCY (Hz)
NORMALIZED EA REFERENCE
0
TEMPERATURE (°C)
FIGURE 1. FREQUENCY vs TEMPERATURE
1.000
0.998
0.997
0.996
-60 -40 -20
-20
220pF
330pF
470pF
100 120 140
1.0nF
10
2.2nF
3.3nF
4.7nF
6.8nF
1
0
20 40 60 80
TEMPERATURE (°C)
100pF
100
1
10
Rt (kΩ)
100
FIGURE 4. RESISTANCE FOR CT CAPACITOR VALUES GIVEN
FIGURE 3. EA REFERENCE vs TEMPERATURE
Pin Descriptions
RTCT - This is the oscillator timing control pin. The
operational frequency and maximum duty cycle are set by
connecting a resistor, Rt, between VREF and this pin and a
timing capacitor, Ct, from this pin to GND. The oscillator
produces a sawtooth waveform with a programmable
frequency range up to 2.0MHz. The charge time, tC, the
discharge time, tD, the switching frequency, f, and the
maximum duty cycle, DMAX, can be approximated from the
following equations:
COMP - COMP is the output of the error amplifier and the
input of the PWM comparator. The control loop frequency
compensation network is connected between the COMP and
FB pins.
FB - The output voltage feedback is connected to the
inverting input of the error amplifier through this pin. The
non-inverting input of the error amplifier is internally tied to a
reference voltage.
t C ≈ 0.533 ⋅ R t ⋅ C t
(EQ. 1)
CS - This is the current sense input to the PWM comparator.
The range of the input signal is nominally 0V to 1.0V and has
an internal offset of 100mV.
⎛ 0.008 ⋅ R t – 3.83 ⎞
t D ≈ – R t ⋅ C t ⋅ In ⎜ ------------------------------------------- ⎟
⎝ 0.008 ⋅ R t – 1.71 ⎠
(EQ. 2)
GND - GND is the power and small signal reference ground
for all functions.
f = 1 ⁄ (tC + tD)
(EQ. 3)
D = tC ⋅ f
(EQ. 4)
The formulae have increased error at higher frequencies due
to propagation delays. Figure 4 may be used as a guideline
in selecting the capacitor and resistor values required for a
given frequency.
6
OUT - This is the drive output to the power switching device.
It is a high current output capable of driving the gate of a
power MOSFET with peak currents of 1.0A. This GATE
output is actively held low when VDD is below the UVLO
threshold.
VDD - VDD is the power connection for the device. The total
supply current will depend on the load applied to OUT. Total
IDD current is the sum of the operating current and the
average output current. Knowing the operating frequency, f,
FN6792.1
December 1, 2011
ISL8840AMZ, ISL8841AMZ, ISL8842AMZ, ISL8843AMZ, ISL8844AMZ, ISL8845AMZ
and the MOSFET gate charge, Qg, the average output
current can be calculated from Equation 5:
I OUT = Qg × f
(EQ. 5)
affects COMP. During power-down, diode D1 quickly
discharges C1 so that the soft-start circuit is properly
initialized prior to the next power-on sequence.
Gate Drive
To optimize noise immunity, bypass VDD to GND with a
ceramic capacitor as close to the VDD and GND pins as
possible.
VREF - The 5.00V reference voltage output. +1.0/-1.5%
tolerance over line, load and operating temperature. Bypass
to GND with a 0.1µF to 3.3µF capacitor to filter this output as
needed.
Functional Description
The ISL884xAMBEPZ is capable of sourcing and sinking 1A
peak current. To limit the peak current through the IC, an
optional external resistor may be placed between the
totem-pole output of the IC (OUT pin) and the gate of the
MOSFET. This small series resistor also damps any
oscillations caused by the resonant tank of the parasitic
inductances in the traces of the board and the FET’s input
capacitance.
Slope Compensation
Features
The ISL884xAMBEPZ current mode PWM makes an ideal
choice for low-cost flyback and forward topology
applications. With its greatly improved performance over
industry standard parts, it is the obvious choice for new
designs or existing designs which require updating.
Oscillator
The ISL884xAMBEPZ has a sawtooth oscillator with a
programmable frequency range to 2MHz, which can be
programmed with a resistor from VREF and a capacitor to
GND on the RTCT pin. (Please refer to Figure 4 for the
resistor and capacitance required for a given frequency.)
Soft-Start Operation
Soft-start must be implemented externally. One method,
illustrated in Figure 5, clamps the voltage on COMP.
For applications where the maximum duty cycle is less than
50%, slope compensation may be used to improve noise
immunity, particularly at lighter loads. The amount of slope
compensation required for noise immunity is determined
empirically, but is generally about 10% of the full scale
current feedback signal. For applications where the duty
cycle is greater than 50%, slope compensation is required to
prevent instability.
Slope compensation may be accomplished by summing an
external ramp with the current feedback signal or by
subtracting the external ramp from the voltage feedback
error signal. Adding the external ramp to the current
feedback signal is the more popular method.
From the small signal current-mode model [1] it can be
shown that the naturally-sampled modulator gain, Fm,
without slope compensation, is in Equation 6.
1
Fm = -----------------S n t SW
D1
R1
COMP
Q1
GND
C1
ISL884xAMBEPZ
VREF
(EQ. 6)
where Sn is the slope of the sawtooth signal and tsw is the
duration of the half-cycle. When an external ramp is added,
the modulator gain becomes Equation 7:
1
1
Fm = ------------------------------------ = --------------------------( S n + S e )t SW
m c Snt SW
(EQ. 7)
where Se is slope of the external ramp and
FIGURE 5. SOFT-START
The COMP pin is clamped to the voltage on capacitor C1
plus a base-emitter junction by transistor Q1. C1 is charged
from VREF through resistor R1 and the base current of Q1.
At power-up C1 is fully discharged, COMP is at ~0.7V, and
the duty cycle is zero. As C1 charges, the voltage on COMP
increases, and the duty cycle increases in proportion to the
voltage on C1. When COMP reaches the steady state
operating point, the control loop takes over and soft-start is
complete. C1 continues to charge up to VREF and no longer
7
Se
m c = 1 + ------Sn
(EQ. 8)
The criteria for determining the correct amount of external
ramp can be determined by appropriately setting the
damping factor of the double-pole located at the switching
frequency. The double-pole will be critically damped if the
Q-factor is set to 1, over-damped for Q < 1, and
under-damped for Q > 1. An under-damped condition may
result in current loop instability.
1
Q = ------------------------------------------------π ( m c ( 1 – D ) – 0.5 )
(EQ. 9)
FN6792.1
December 1, 2011
ISL8840AMZ, ISL8841AMZ, ISL8842AMZ, ISL8843AMZ, ISL8844AMZ, ISL8845AMZ
where D is the percent of on-time during a switching cycle.
Setting Q = 1 and solving for Se yields Equation 10:
1
1
S e = S n ⎛ ⎛ --- + 0.5⎞ ------------- – 1⎞
⎠1 –D
⎝⎝π
⎠
(EQ. 10)
RtCt signal. A typical application sums the buffered RtCt
signal with the current sense feedback and applies the result
to the CS pin, as shown in Figure 6.
Since Sn and Se are the on time slopes of the current ramp
and the external ramp, respectively, they can be multiplied
by tON to obtain the voltage change that occurs during tON.
VREF
(EQ. 11)
CS
R6
where Vn is the change in the current feedback signal (ΔI)
during the on-time and Ve is the voltage that must be added
by the external ramp.
RTCT
C4
For a flyback converter, Vn can be solved for in terms of
input voltage, current transducer components, and primary
inductance, yielding
D ⋅ t SW ⋅ V IN ⋅ R CS 1
1
V e = -------------------------------------------------- ⎛ ⎛ --- + 0.5⎞ ------------- – 1⎞
⎠1 –D
⎝⎝ π
⎠
Lp
V
(EQ. 12)
where RCS is the current sense resistor, fSW is the switching
frequency, Lp is the primary inductance, VIN is the minimum
input voltage, and D is the maximum duty cycle.
The current sense signal at the end of the on-time for CCM
operation is:
( 1 – D ) ⋅ VO ⋅ f
N S ⋅ R CS ⎛
SW⎞
V CS = ------------------------ ⎜ I O + ----------------------------------------------⎟
2L
NP
⎝
⎠
s
V
(EQ. 13)
where VCS is the voltage across the current sense resistor,
Ls is the secondary winding inductance, and IO is the output
current at current limit. Equation 13 assumes the voltage
drop across the output rectifier is negligible.
Since the peak current limit threshold is 1.00V, the total
current feedback signal plus the external ramp voltage must
sum to this value when the output load is at the current limit
threshold.
V e + V CS = 1
(EQ. 14)
Substituting Equations 12 and 13 into Equation 14 and
solving for RCS yields Equation 15:
1
R CS = ----------------------------------------------------------------------------------------------------------------------------------------------------1
( 1 – D ) ⋅ V O ⋅ f sw⎞
D ⋅ f sw ⋅ V IN ⎛ --π- + 0.5 ⎞ N s ⎛
------------------------------⋅ ⎜ ------------------ – 1⎟ + ------- ⋅ ⎜ I O + --------------------------------------------⎟
⎜ 1–D
⎟ N ⎝
Lp
2L s
⎠
p
⎝
⎠
(EQ. 15)
Adding slope compensation is accomplished in the
ISL884xAMBEPZ using an external buffer transistor and the
8
ISL8843
R9
1
1
V e = V n ⎛ ⎛ --- + 0.5⎞ ------------- – 1⎞
⎠1 –D
⎝⎝π
⎠
FIGURE 6. SLOPE COMPENSATION
Assuming the designer has selected values for the RC filter
(R6 and C4) placed on the CS pin, the value of R9 required
to add the appropriate external ramp can be found by
superposition.
2.05D ⋅ R 6
V e = ---------------------------R6 + R9
(EQ. 16)
V
The factor of 2.05 in Equation 16 arises from the peak
amplitude of the sawtooth waveform on RtCt minus a
base-emitter junction drop. That voltage multiplied by the
maximum duty cycle is the voltage source for the slope
compensation. Rearranging to solve for R9 yields:
( 2.05D – V e ) ⋅ R 6
R 9 = ---------------------------------------------Ve
Ω
(EQ. 17)
The value of RCS determined in Equation 15 must be
rescaled so that the current sense signal presented at the
CS pin is that predicted by Equation 13. The divider created
by R6 and R9 makes this necessary.
R6 + R9
R′ CS = --------------------- ⋅ R CS
R9
(EQ. 18)
Example:
VIN = 12V
VO = 48V
Ls = 800µH
Ns/Np = 10
Lp = 8.0µH
IO = 200mA
Switching Frequency, fSW = 200kHz
Duty Cycle, D = 28.6%
FN6792.1
December 1, 2011
ISL8840AMZ, ISL8841AMZ, ISL8842AMZ, ISL8843AMZ, ISL8844AMZ, ISL8845AMZ
R6 = 499Ω
Fault Conditions
Solve for the current sense resistor, RCS, using Equation 15.
A Fault condition occurs if VREF falls below 4.65V. When a
Fault is detected, OUT is disabled. When VREF exceeds
4.80V, the Fault condition clears, and OUT is enabled.
RCS = 295mΩ
Determine the amount of voltage, Ve, that must be added to
the current feedback signal using Equation 12.
Ground Plane Requirements
R9 = 2.67kΩ
Careful layout is essential for satisfactory operation of the
device. A good ground plane must be employed. A unique
section of the ground plane must be designated for high di/dt
currents associated with the output stage. VDD should be
bypassed directly to GND with good high frequency
capacitors.
Determine the new value of RCS (R’CS) using Equation 18.
References
Ve = 92.4mV
Using Equation 17, solve for the summing resistor, R9, from
CT to CS.
R’CS = 350mΩ
Additional slope compensation may be considered for
design margin. The previous discussion determines the
minimum external ramp that is required. The buffer transistor
used to create the external ramp from RtCt should have a
sufficiently high gain (>200) so as to minimize the required
base current. Whatever base current is required reduces the
charging current into RtCt and will reduce the oscillator
frequency.
9
[1] Ridley, R., “A New Continuous-Time Model for Current
Mode Control”, IEEE Transactions on Power
Electronics, Vol. 6, No. 2, April 1991.
FN6792.1
December 1, 2011
ISL8840AMZ, ISL8841AMZ, ISL8842AMZ, ISL8843AMZ, ISL8844AMZ, ISL8845AMZ
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
N
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
H
0.25(0.010) M
B M
INCHES
E
SYMBOL
-B-
1
2
3
L
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
MIN
MAX
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.1890
0.1968
4.80
5.00
3
E
0.1497
0.1574
3.80
4.00
4
e
α
B S
0.050 BSC
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
N
α
NOTES:
MILLIMETERS
8
0°
8
8°
0°
7
8°
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
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10
FN6792.1
December 1, 2011
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