750W

Application Note 1885
Author: Alan Yu
ISL6731AEVAL2Z and ISL6731BEVAL2Z: High
Performance Boost CCM PFC Front End for Server
Power Applications
Introduction
Design Specifications
This application note describes the design and
implementation of a 390V, 750W, Continuous Conduction
Mode (CCM) Boost PFC converter using either ISL6731A or
ISL6731B. The converter exhibits high power factor, low THD
and high conversion efficiency. The ISL6731A, ISL6731B are
voltage mode power factor correction (PFC) controllers
designed to drive cost-effective high performance converters
to meet the tight input line harmonic requirements. The IC can
be ISL6731A (124kHz) or ISL6731B (64kHz).
• Input Voltage, VIN: 90V - 265VAC
• Output Voltage, VO: 390VDC
• Output Current, IO: 1.92A (750W)
• Switching Frequency:
ISL6731A (124kHz) or ISL6731B (64kHz)
• Efficiency: Full Load, 93% @ 115V; 97% @ 230V
• PF: Full Load, 0.99
Application
• THD: Full Load, 2%
• Board Dimension: 121×96×38 mm3(L×W×H)
PFC front end for server, data center, telecom, industrial and
infrastructure power applications.
Test Setup
Key Features
• See the test set-up in Figure 9 on page 7
• A 12VDC FAN is needed to cool the heat-sink during the test,
especially at full load with low line 90~140VAC input!
• Universal input: 90V~265VAC
• Adaptive control to achieve extremely low THD and high PF
without DSP.
Ordering Information
• Compact implementation
PART NUMBER
DESCRIPTION
References
ISL6731AEVAL2Z
750W Boost CCM PFC, 124KHz
• “ISL6731A, ISL6731B” datasheet
ISL6731BEVAL2Z
750W Boost CCM PFC, 64kHz
VI
V LINE
Q1
+
CO
{
Sv= {
Sp=
Q3
Sv
Q6
Q4
Sp
H, IF HEAVY LOAD
L, IF LIGHT LOAD
H, IF LOW LINE
L, IF HIGH LINE
VCC
Sp
ISEN
VIN
ICOMP
V OUT
ISL6731
BO
GATE
GND
OVP
FB
COMP
Sp
Load_Sw
V
Sv
Line_Sw
SKIP VREG
Q5
Sv
FIGURE 1. SIMPLIFIED SCHEMATIC
March 20, 2014
AN1885.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2014. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
Application Note 1885
Component Selection Guidelines
A 750W, universal input, PFC converter design is provided for
demonstration. The design method is for a continuous current
mode power factor correction boost converter with the
ISL6731B. The switching frequency is 64kHz.
Table 1 shows the design parameters.
TABLE 1. CONVERTER DESIGN PARAMETERS
PARAMETER
CONDITIONS
MIN
TYP
MAX UNIT
VLINE
90
115/230 265
FLINE
47
63
Hz
750
W
POMAX
Maximum Output
Power
THOLD
Hold Up Time
Efficiency
VLINE = 115VAC
VAC
20
ms
92
%
First, calculate the maximum input RMS current, IINMAX.
(EQ. 1)
Where η is the converter efficiency at VRMSmin. PF is the power
factor at VRMSmin.
750W
I INMAX = ---------------------------- = 9.06A
0.92 • 90V
(EQ. 8)
Select the bridge diode using Equation 9 and sufficient reverse
breakdown voltage. Assuming the forward voltage, VF,BR, is 1.1V
across each rectifier diode. The power loss of the rectifier bridge
can be calculated:
P BR = 2 • V F, BR • I INAVE ( MAX )
(EQ. 9)
P BR = 2 • 1.1V • 8.2A = 17.9W
(EQ. 10)
INPUT CAPACITOR SELECTION
Refer to the “Recommended Filtering Capacitor” table, in the
ISL6731A, ISL6731B datasheet for the recommended input filter
capacitor value.
0.22
C F1 = 750W • ----------- = 1.65μF
100
(EQ. 11)
The definition of CF1 is on the block diagram in the ISL6731A,
ISL6731B datasheet.
BOOST INDUCTOR SELECTION
P OMAX
I INMAX = ----------------------------------η • V RMSmin
2 • 2 • 9.06A
I INAVE ( max ) = -------------------------------------- = 8.2A
π
(EQ. 2)
Assuming the current is sinusoidal and the peak-to-peak ripple at
line is 40%.
This is the recommended capacitor used after the diode bridge.
For better power factor, less capacitance can be used. To lower
the input filter inductor size, more capacitance can be used.
One 0.68µF capacitor is used for CF1.
BOOST DIODE SELECTION
The boost diode loss is determined by the diode forward voltage
drop, VF and the output average current. The maximum output
current is:
The boost inductor, LBST, is given by the following equation:
P OMAX
I OUT ( max ) = -------------------V OUT
(EQ. 12)
2 • V RMSmin⎞
2V RMSmin
⎛
L BST ≥ ---------------------------------------------------------------- • ⎜ 1 – ---------------------------------------⎟
V OUT
0.4 • F sw • 2 • I INMAX ⎝
⎠
750W
I OUT ( max ) = ---------------- = 1.923A
390V
(EQ. 13)
90V
2 • 90V
L BST ≥ ------------------------------------------------------ • ⎛ 1 – ------------------------⎞ = 261μH
0.4 • 64kHz • 9.06 A ⎝
390V ⎠
(EQ. 3)
(EQ. 4)
An 850µH inductor was selected. The peak current of the inductor
is the sum of the average peak inductor current and half of the
peak-to-peak ripple current. Select and design the boost inductor
as given by Equation 3. The ISL6731A and ISL6731B provide a
peak current limit function that can prevent the boost inductor
saturation. Assuming 25% margin is given to the OCP threshold,
select and design the boost inductor with saturation current given
by Equation 5 with 25% margin.
I LPeak =
LPeak =
1
2 • I INMAX + --- • Δ
2
I
(EQ. 5)
( 3.152A )
2 • 9.06A + ------------------------ = 14.4A
2
(EQ. 6)
P FD = I OUT ( max ) • V F
(EQ. 14)
P FD = 1.923A • 1.3V = 2.5W
(EQ. 15)
The IDH05S60C part is selected.
The reverse recovery loss on the diode can be calculated. The
QRR is found from the diode datasheet. QRR = 12nC.
The reverse recover loss on the diode can be estimated:
1
P RRD = --- • Q
• V OUT • F
4
RR
sw
(EQ. 16)
1
P RRD = --- • 12nC • 390V • 64kHz = 0.075W
4
(EQ. 17)
The total power loss on the diode is:
P D = P FD + P RRD = ( 2.5 + 0.075 )W = 2.575W
INPUT RECTIFIER
The maximum average input current is calculated:
2 • 2 • I INMAX
I INAVE ( max ) = -----------------------------------------π
Submit Document Feedback
The forward power loss on the diode is:
(EQ. 7)
2
(EQ. 18)
MOSFET POWER DISSIPATION
The power dissipation on the MOSFET is from two different types
of losses; the conduction loss and the switching loss.
AN1885.0
March 20, 2014
Application Note 1885
For the MOSFET, the worst case is at minimum line input voltage.
First, the drain to source RMS current is calculated:
8 2 V RMSmin
I DS ( max ) = I INMAX 1 – ----------- • -------------------------V
3π
(EQ. 19)
8 2 90V
I DS ( max ) = 9.06A 1 – ----------- • -------------- = 7.7A
3π 390V
(EQ. 20)
OUT
Select the proper capacitor according to the hold time and ripple
RMS current requirement. The actual capacitance is 2x270µF.
It is important to make sure the output peak-to-peak ripple is
less than the minimum OVP threshold. The ESR of the capacitor
at 2 times the line frequency is found in the capacitor datasheet.
The ESR is 367mΩ.
2
( 4πf line ⋅ C O ⋅ ESR ) + 1
V Opp = I OUT ( max ) ⋅ ----------------------------------------------------------------------( 4πf
) ⋅ C ⋅ 0.8
line
The MOSFET, SPP20N60C3 is selected.
(EQ. 21)
2
P COND = I DS ( max ) • R DS ( on )
2
P COND = 7.7A • 0.188Ω = 11.12W
(EQ. 22)
The switching loss of the MOSFET consists of three parts: the
turn-on loss, the turn-off loss and the COSS loss.
(EQ. 32)
O
2
( 4π ⋅ 60Hz ⋅ 540μF ⋅ 0.367Ω ) + 1
V Opp = 1.923A ⋅ ----------------------------------------------------------------------------------------------- = 5.97V
( 4π ⋅ 60Hz ) ⋅ 540μF ⋅ 0.8
(EQ. 33)
The minimum OVP threshold is 103% of the nominal output
value. The maximum output peak-to-peak ripple should be less
than 6% of the nominal value, which is 23.4VP-P.
From the MOSFET datasheet, the typical switching losses curves
are provided.
CURRENT SENSING RESISTORS
EON = 0.022mJ, EOFF = 0.029mJ.
Please refer to Equation 34 for calculation of the current sensing
resistor RCS.
The switching loss due to transition is calculated:
(EQ. 23)
P SW = ( E ON + E OFF ) • F
sw
P SW = ( 0.022mJ + 0.029mJ ) • 64kHz = 3.26W
(EQ. 24)
The loss caused by COSS can be estimated as:
From the datasheet, the COSS is 61pF at 390V.
2
2
P OSS = --- 61pF • 390V • 64kHz = 0.394W
3
(EQ. 34)
While a large RCS renders better current sensing accuracy, larger
RCS also incurs higher power dissipation. Select RCS from
available standard value resistors to determine the sense
resistor.
(EQ. 35)
R CS = 0.044Ω
(EQ. 25)
2
2
P OSS = --- C OSS • V OUT • F
3
sw
120mV ⋅ 265V ⋅ 0.92
R CS ≥ ------------------------------------------------------- = 0.028Ω
2 ⋅ 750W
(EQ. 26)
The maximum power dissipation on the RCS occurs at low line
and full load condition. The maximum power dissipation is
calculated:
2
(EQ. 36)
P RCSMAX = I INMAX • R CS
2
THE TOTAL LOSS ON THE MOSFET
P COND + P SW + P
OSS
= 11.12W + 3.26W + 0.394W = 14.78W
(EQ. 27)
OUTPUT CAPACITOR SELECTION
The output capacitor, CO, is required to hold the output above
300V during one line cycle. For capacitors with 10% tolerance,
the tolerance should be taken into consideration. Thus, the
output capacitance should be greater than:
2 ⋅ T HOLD ⋅ P
1
OMAX
C O ≥ ---------------------------------------------------- ⋅ ----------------2
2
1 – 0.1
V OUT
– V HOLD
2 ⋅ 20ms ⋅ 750W
C O ≥ ---------------------------------------------- ⋅ 1.25 = 537μF
2
( 390 ) – ( 300V ) 2
(EQ. 28)
(EQ. 29)
V OUT
8 2
I CORMS ( max ) = I OUT ( max ) ----------- • -------------------------- – 1
3π V RMSmin
(EQ. 30)
8 2 390V
I CORMS ( max ) = 1.923A ----------- • -------------- – 1 = 3.942A
3π
90V
(EQ. 31)
3
The resistor RSEN sets the overcurrent protection limit.
R CS • I LPeak • ( 1 + 0.25 )
R SEN ≥ -------------------------------------------------------------------2 • 0.5 I OC
(EQ. 38)
Where |x| stands for the ABS (x) function. IOC is overcurrent
threshold (in datasheet).
0.044Ω • 14.4A • 1.25
R SEN ≥ ----------------------------------------------------------- = 5.0kΩ
159μA
(EQ. 39)
The selected RSEN is 5.2kΩ.
CURRENT LOOP COMPENSATION
Calculate the ripple RMS current through the capacitor:
Submit Document Feedback
(EQ. 37)
P RCSMAX = 9.06A • 0.044Ω = 3.61W
The input current shaping is achieved by comparing the sensed
current signal to the sensed input voltage signal. The current
error amplifier (Gmi), together with the current compensation
network, adjusts the duty cycle so that the inductor current
traces the sensed rectified voltage. Thus, unity power factor is
achieved.
The compensation network consists of the Trans-Conductance
error amplifier (Gmi) and the impedance network (ZICOMP). The
goal of the compensation network is to provide a closed loop
transfer function with the sufficient 0dB crossing frequency
AN1885.0
March 20, 2014
Application Note 1885
(f0dB) and adequate phase margin. Phase margin is the
difference between the open loop phase at f0dB and 180°. The
following equations relate the compensation network’s poles,
zeros and gain to the components (Ric, Cic and Cip) in Figure 2.
VI
Q1
CO
s --------------------+1
2 ⋅ π ⋅ FZ
1
-----------------------------------------------------------------G ci ( s ) = Gmi
•
( C ic + C ip ) ⋅ s
s
----------------------- + 1
2 ⋅ π ⋅ FP
RCS
CURRENT
MIRROR
2:1
I
CS
Rcs Ris 1
Gsm = --------------- ⋅ --------- --------Rsen 2 Vm
IREF
G ILOOP ( s ) = G id ( s ) • G sm • G ci ( s )
RIS
Gmi
Ric
120
GILOOP(s)
Gci(s)
80
60
GAIN (dB)
FC
F Z = -------------------------------------------------------⎛
⎞
⎛ F C⎞
tan ⎜ atan ⎜ -------⎟ + Φ M⎟
F
⎝
⎠
⎝ P⎠
FP
FZ
(EQ. 46)
Where FC = Fsw/9 = 7.1kHz, ΦM is the phase margin, which is
50°. FP = Fsw/4 = 16kHz.
FC
Thus, the current loop compensation zero is:
Gid(s)
40
(EQ. 45)
It is recommended to set the crossover frequency from 1/10 to
1/6 of the switching frequency with phase margin of about 60°.
A high frequency pole is set at 1/2 or less of the switching
frequency for ripple filtering. In this example, we set the
crossover, FC at 1/9 of the switching frequency.
Cip
FIGURE 2. INDUCTOR CURRENT SENSING SCHEME
20
( 64kHz ) ⁄ 9
F Z = ------------------------------------------------------------- = 2.04kHz
4
⎛
tan atan ⎛ ---⎞ + 50deg⎞
⎝
⎝ 9⎠
⎠
0
-20
(EQ. 44)
where Vm is the amplitude of the PWM carrier. The open loop
gain of the current loop is
ICOMP
100
(EQ. 43)
The current gain and modulation gain Gsm is:
ISEN
Cic
(EQ. 42)
The compensation gain uses external impedance networks as
shown in Figure 2, Gci(s) is given by:
CF1
RSEN
Near crossover frequency, the transfer function from duty cycle to
inductor current is well approximated Equation 42:
V OUT
G id ( s ) = ---------------------L BST ⋅ s
VOUT
L
Use the following guidelines for locating the poles and zeros of
the compensation network.
(EQ. 47)
Gsm
The total compensation capacitance is calculated:
-40
10
100
1k
10k
100k
FREQUENCY (Hz)
FIGURE 3. ASYMPTOTIC BODE PLOT OF CURRENT LOOP GAIN
1
F Z = -----------------------------------2π • R ic • C
(EQ. 40)
ic
2
⎛⎛
A IDC R CS ⎞
V OUT
1 + ( fc ⁄ fz ) ⎞
-⎟ (EQ. 48)
C ip + C ic = ⎜ ⎜ --------------------------------------- ⋅ -------------- ⋅ ----------------⎟ ⋅ -----------------------------⎜⎝
2 V
2⎟
R SEN⎠
+
(
⁄
f
)
1
f
m
L
⋅
(
2πf
)
⎝ BST
c p ⎠
c
C ip + C ic = 8.148nF
(EQ. 49)
fz
C ip = ( C ip + C iC ) ---f
(EQ. 50)
p
1
F P = --------------------------------------------------C ip • C
ic
2π • R ic • -----------------------C ip + C ic
(EQ. 41)
The value of the noise filtering capacitor is:
2.04kHz
C ip = 8.148nF ⋅ ----------------------- = 1.041nF
16kHz
(EQ. 51)
The value of Cic is:
C ic = 8.148nF – 1.041nF = 7.1nF
Submit Document Feedback
4
(EQ. 52)
AN1885.0
March 20, 2014
Application Note 1885
The value of Ric is:
1
R ic = ------------------------------------------------------- = 10.96kΩ
2π ⋅ 2.04kHz ⋅ 7.1nF
(EQ. 53)
Select the RC value from the standard value, we have:
Ric = 10kΩ, Cic = 6.8nF, Cip = 1nF. Figure 4 shows the bode plot
of current loop gain, where fs = Fsw.
GAIN (dB)
100
fs
fs
10
2
1.5
5.2k
C NEG = ⎛ 0.00619 ⋅ 0.8 – ----------⎞ --------------------------- ( 6.8nF + 1nF ) = 0.54μF
⎝
390⎠ 0.044 ⋅ 1.9
(EQ. 58)
This equivalent negative capacitor cancels the input filter
capacitor required for EMI filtering. Therefore, the displacement
power factor significantly improves.
For example, refer to the block diagram on page 4 in the
ISL6731A, ISL6731B datasheet CF2+CF3 = 2µF, CF1 = 0.68µF,
when VLINE = 230VAC, fLINE = 50Hz, PO = 750W.
Assuming 95% efficiency under the above test condition, the
resistive component of the line current, which is in phase to
voltage:
50
Po
I a = --------------------------------- = 3.432A
V LINE ⋅ 0.95
0
(EQ. 59)
The reactive current through the input capacitors:
PHASE (deg)
90
fs
fs
10
2
60
I c = V LINE • ( 2π ⋅ f LINE ) • ( C F1 + C F2 + C F3 ) = 0.232A
60
Thus, the displacement power factor is:
45
Ia
PF DIS = ----------------------------------- = 0.9977
2
2
( Ia ) + ( Ic )
30
0
10
3
1×10
100
4
1×10
(EQ. 60)
1×10
5
(EQ. 61)
The reactive current generated by the equivalent negative
capacitor is:
FIGURE 4. BODE PLOT OF THE ACTUAL CURRENT LOOP GAIN
(EQ. 62)
I cneg = V LINE • ( 2π ⋅ f LINE ) • ( C NEG ) = 0.046A
INPUT VOLTAGE SETTING
First, set the BO resistor divider gain, KBO according to Equation
54.
With the equivalent negative capacitor, the total reactive current
reduces to:
Assuming the converter starts at VLINE = 80VRMS, then the BO
resistor divider gain, KBO should be:
I c – I cneg = 0.186A
(EQ. 54)
0.5V
K BO = ------------------------ = 0.00641
80V – 2V
In this design, two 200kΩ resistors in series are used for RIN2.
So, RIN1 is calculated:
0.00641
R IN1 = ------------------------------- ⋅ ( 440kΩ ) = 2.581kΩ
1 – 0.00641
(EQ. 55)
Using resistor from the standard value, RIN1 = 2.49kΩ, the actual
KBO is calculated:
R IN1
K BO = --------------------------------- = 0.00619
R IN1 + R IN2
(EQ. 56)
The displacement power factor increases to:
Ia
PF DIS = -------------------------------------------------------- = 0.9985
2
2
( I a ) + ( I c – I cneg )
(EQ. 64)
VOLTAGE LOOP COMPENSATION
The average boost diode forward current can be approximated
by:
P in
I D ( ave ) = ---------------V OUT
(EQ. 65)
Assuming the input current traces the input voltage perfectly. The
input power is in proportion to (VCOMP - 1V).
NEGATIVE INPUT CAPACITOR GENERATION
The ISL6731A and ISL6731B generate an equivalent negative
capacitance at the input to cancel the input filter capacitance.
Thus, more input capacitors can be used without reducing the
power factor.
The input equivalent negative capacitance is a function of the
current sensing gain, BO resistor divider gain and the
compensation components.
V m ⎞ R SEN
⎛
C NEG = ⎜ K BO ⋅ 0.8 – ----------------⎟ -------------------------- ( C ic + C ip )
V
⎝
OUT⎠ R CS A iDC
Submit Document Feedback
(EQ. 63)
5
⎛
⎞
R SEN
1
0.25
I D ( ave ) = --------------------------------------- • ---------------- • ⎜ ------------------------------------------------⎟ • Δ COMP
⎟
2
R CS ⋅ 0.5 ⋅ R IS V OUT ⎜
⎝ ( ( 2 2 ) ⁄ π ) ⋅ K BO⎠
(EQ. 66)
Where ΔCOMP is the VCOMP - 1V. 1V is the offset voltage.
RIS is the internal current scaling resistor. RIS = 14.2kΩ.
A
I D ( ave ) = ( 2.13 ) ---- • Δ COMP
V
(EQ. 67)
(EQ. 57)
AN1885.0
March 20, 2014
Application Note 1885
VOUT
2.5V
The zero, FZv is calculated:
F CV
F Zv = -----------------------------------------------------------------------------tan ( Φ m + atan ( F CV ⁄ ( F Pv ) ) )
(EQ. 73)
10Hz
F Zv = --------------------------------------------------------------------------------------------------- = 2.389Hz
tan ( 50deg + atan ( ( 10Hz ) ⁄ ( 20Hz ) ) )
(EQ. 74)
RFB2
FB
Gmv
Then the total capacitance used for compensation is calculated:
RFB1
IFB
2
G PS ( i • ( 2πF CV ) ) • G DIV • Gmv
( F CV ⁄ F ZV ) + 1
C vc + C vp = ------------------------------------------------------------------------------------------- • ------------------------------------------2
( 2πF CV )
( F CV ⁄ F PV ) + 1
(EQ. 75)
COMP
Rvc
Thus, the total compensation capacitance is:
Cvp
Cvc
FIGURE 5. OUTPUT VOLTAGE SENSING AND COMPENSATION
Thus, the transfer function from VCOMP to VOUT is:
I D ( ave )
V OUT ( s )
1
G PS ( s ) = ------------------------ = ---------------- ⋅ -------------------Δ COMP
C O ⋅ s Δ COMP
F ZV
C vp = 1233nF • ----------- = 147nF
F PV
1
R vc = ------------------------------------------- = 61.3kΩ
2 ⋅ π ⋅ F ZV ⋅ C VC
(EQ. 69)
Choose components from the standard values. We have
CVP = 150nF, CVC = 1µF, RVC = 62kΩ. The actual bode plot is
shown in Figure 7.
V REF
G DIV = ---------------V OUT
(EQ. 71)
GAIN (dB)
40
The output feedback resistor divider gain, GDIV is:
The compensation gain uses external impedance networks as
shown in Figure 5, ZCOMP(s) is given by:
(EQ. 72)
The targeted crossover frequency, FCV is 10Hz. The high
frequency pole, FPv is required in order to reject the 2 time line
frequency component. FPv = 20Hz. The targeted phase margin is
50°.
20
0
0
90
120 ⋅ Hz
60
60
45
30
0
1
Gmv*Zcomp(s)
GVLOOP(s)
GDIV
-60
10
100
1k
FREQUENCY (Hz)
FIGURE 6. ASYMPTOTIC BODE PLOT OF VOLTAGE LOOP GAIN
Submit Document Feedback
3
ISL6730 and ISL6731 family have excellent power factor
correction capability to achieve low THD and high PF with the
above circuit optimization. To further improve THD at light and
high line condition, Q3, Q4, Q5 and Q6 and two comparators are
added to dynamically change current loop and current sense
gain (refer to Figure 1). This simple analog implementation can
achieve same level of THD and PF performance as DSP control.
-20
1
1 ×10
ADAPTIVE CONTROL
0
-40
100
FIGURE 7. BODE PLOT OF THE ACTUAL VOLTAGE LOOP GAIN
Gps(s)
FCV
10
FREQUENCY (Hz)
40
GAIN (dB)
120 ⋅ Hz
− 20
PHASE (deg)
R vc • C vc • s + 1
1
Z COMP ( s ) = --------------------------------------- • ------------------------------------------------------------( C vc + C vp ) ⋅ s R vc • C vc • C vp
------------------------------------------ • s + 1
C vc + C vp
20
(EQ. 79)
(EQ. 70)
G VLOOP ( s ) = G PS ( s ) • G DIV • Gmv • Z COMP ( s )
FPV
(EQ. 78)
C vc = 1233nF – 147nF = 1086nF
As shown in Figure 5, the voltage loop gain is:
FZV
(EQ. 77)
(EQ. 68)
⎛ I D ( ave )
1 ⎞
2.13
G PS ( s ) = ⎜ ------------------- ⋅ --------------------⎟ = ---------------C
⋅
s
Δ
CO ⋅ s
⎝ O
COMP⎠
60
(EQ. 76)
C vc + C vp = 1233nF
6
The signal Sp controls Q6 (inverted) and Q4. Sp is controlled by
load power level via the voltage level on COMP pin. Sp goes high
at heavy load and low at light load.
AN1885.0
March 20, 2014
Application Note 1885
At light load condition, COMP voltage is low. Sp goes low. Q4
turns off to increase Ric resistance to increase current loop gain
and Q6 turns on to increase current sense gain. The increase of
current loop and sense gain will push crossover frequency higher
to improve THD.
At high line condition, BO voltage is low. Sv goes low. Q5 turns off
to increase Ric resistance to increase current loop gain and Q3
turns off to increase current sense gain. The increase of current
loop and sense gain will push crossover frequency higher to
improve THD.
The signal Sv controls Q3 and Q5. Sv is controlled by line voltage
via the voltage level on BO pin. Sv goes high at low line and low at
high line.
At light load or high line condition, the boost inductor current is
relatively small. The converter runs in discontinuous conduction
mode. In this condition the CCM frequency domain model cannot
be used for analysis. In DCM condition, the current loop will be
inherently stable and thus can be pushed to run in a higher gain
and crossover frequency configuration.
FIGURE 8. PHOTO OF THE EVALUATION BOARD
POWER ANALYZER
ISL6731 EVB
AC SOURCE
Iin
L
A
Io
P2
+
P1
V
VLINE
UUT
LOAD
P4
P3
-
V
VOUT
N
P6
-
+
P7
12V
FIGURE 9. TEST SETUP
Submit Document Feedback
7
AN1885.0
March 20, 2014
1N5406
D1
L1
0u
IDH05S60C
D2
L2
880u
P2
+
-
R3
2M
C35
2.2n
4.7n
C5
C36
2.2n
R27 0.11
R5 0.22
4.7n
C6 D8 D7
S1M S1M
-Isen
FDMS7650DC
3
Q3
2
1
C21
0.1
2
R2
2.2
8
7
6
5
9
TP12
5
2
R13
6.2k
C13
47p
SKIP
BO
3
TP13
ISL28413
-Isen
10k
R49
LOAD_SW
RJ6
R48
6
1
VCC
3k
2.2k
C37
2.2u
5
4
0
10k
R50
R9
Q6A
DMG1026UV-7
2
11
TP5
C7
1u
Q6B
TP4
TP2
GND
2
OVP
7
49.9
TP11
C23
DNP
2.5V
9
FB
gm
COMP
ISL6731A/B
C16
100n
C18
1u
C15
150n
TP1
R19
42.2k
U2C
8 R32 10k
R23
ISL28413
R18
62k
R17
0
R29 150k LINE_SW
10
9
R22
0
C14
470n
P7
1
13
4
+
-
GND
P6
R26
GATE 14
CEQ OTP
3 ISEN I MIRROR
2:1
Gen
PWM
Vin*C
I*= 4*BO*BO I*
gm
5 VIN
C SKIP OPL
3
U2A
C12
DNP
4
VCC
R10
3.3M
U1
VREG Lin.Reg. VCC
UVLO LOGIC
ICOMP
8
4
C4
10n
C11
1n
6
VREG
R46
20k
VCC
12
Q5A
LINE_SW RJ5
0
R21
10K
R8
470k
R11
470k
TP3
C24
1n
1
Q5B
VREG
TP8
10
TP14
2
390k
6
R45
20k
R6
3.3M
C9
1u
C20
47n
11
3
R47 10k
TP15
DMG1026UV-7
4 1
LINE_SW
RJ3
0
R14
10k
C26
2.2n
C8
220n
DZ1
3.3V
R7
10k
TP6
ISL28413
R15
R31
10k
6
7
U2B
VREG
R30
59k
2
5
5
R25
10k Q4A
4 1
Q4B
3
6
C10
6.8n
P3
R4
51k
TP16
R24
VREG 30k
TP17
82k
12
13
U2D
14 LOAD_SW
ISL28413
R20 C25
16k 1n
Application Note 1885
LOAD_SW RJ4
0
C19
0.1
390V
IPW60R125CP
Q1
1
PE
P5
1
1
R28 0.11
F1 15A
450V
C1
270u
2
L4
2.2m
Rcs: (=R5//R27//R28)
= 0.22/2, High Line;
= 0.22/5, Low Line.
DNP
C7a
2
L3
2.2m
1
AC2
C3
680n
DB1
GBU15K-BP
C22
1u
450V
C17
270u
3
6
7
R1
2M
RV1
MOV
12
8
P4
C2
1u
1
UNIVERSAL INPUT
90~265Vac
6
AC1
7
P1
12
Submit Document Feedback
Schematic
AN1885.0
March 20, 2014
Application Note 1885
Bill of Materials
QTY
REFERENCE
DESIGNATOR
2
C1, C17
Cap; TH; Radial
270µ
2
C2, C22
Cap; TH; Radial
1µ
1
C3
Cap; TH; Radial
680n
450V; 20%; Metallized Polyester Panasonic
Film
1
C4
Cap; SM; 0603
10n
16V; 5%; NPO
TDK
2
C5, C6
Cap; TH; Radial
4.7n
Y1; 20%; EMI, Y2-class
TDK
2
C7, C9
Cap; SM; 0603
1µ
50V; 20%; X7R
TDK
1
C8
Cap; SM; 0603
220n
25V; 20%; X7R
TDK
1
C10
Cap; SM; 0603
6.8n
25V; 10%; X7R
TDK
1
C11
Cap; SM; 0603
1n
25V; 10%; X7R
TDK
1
C13
Cap; SM; 0603
47p
16V; 5%; NPO
TDK
1
C14
Cap; SM; 0603
470n
16V; 10%; X7R
TDK
1
C15
Cap; SM; 0603
150n
50V; 10%; X7R
TDK
1
C16
Cap; SM; 0603
100n
50V; 10%; X7R
TDK
1
C18
Cap; SM; 0603
1µ
16V; 10%; X7R
TDK
2
C19, C21
Cap; SM; 1812
0.1
630V; 10%; -
Murata
1
C20
Cap; SM; 0603
47n
25V; 10%; X7R
TDK
2
C24, C25
Cap; SM; 0603
1n
16V; 5%; NPO
TDK
3
C26, C35, C36
Cap; TH; Radial
2.2n
Y1; 20%; EMI,Y2-class
TDK
1
C37
Cap; SM; 0603
2.2µ
50V; 20%; X7R
TDK
1
DB1
Diode; TH; BRU806
GBU15K-BP
800V; 15A; Bridge Rectifier
Diodes Inc
1
DZ1
Zener; SM; SOD323
3.3V
5%; Zener
NXP
1
D1
Diode; TH; DO-201AD
800V; 3A; Standard Recovery
Micro Commercial Co 1N5406-TP
1
D2
Diode; TH; TO-220
600V; 4A; SiC Schottky
Cree
2
D7, D8
1
L2
2
L3, L4
1
Q1
MOSFET; TH; TO-247
IPW60R125CP 650V; ; N-Chan
Infineon
1
Q3
MOSFET; TH; SO-8-EP
FDMS7650DC 650V; ; N-Chan
Fairchild
3
Q4, Q5, Q6
MOSFET; SM;
DMG1026UV-7 60V; 400mA; N-Chan, Dual
Diode Inc
1
RV1
Rv; TH; Radial
MOV
Varistors
2
R1, R3
Res; SM; 1206
2M
5%;
1
R2
Res; SM; 0603
2.2
1%;
1
R4
Res; SM; 0603
51k
1%;
1
R5
Res; TH; Axial
0.22
1W; 5%; WW
2
R6, R10
Res; SM; 1206
3.3M
1%;
R7, R14, R21, R25, Res; SM; 0603
R31, R32, R47,
R49, R50
10k
1%;
9
TYPE/PACKAGE
VALUE
1N5406
IDH05S60C
VOL/TOL/MAT
MANUFACTURER
450V; 20%; ELECT, Aluminum
Panasonic
X2; 20%; EMI, X2-class
EPCOS
MANUFACTURER PART #
EETUQ2W271DA
ECW-F2W684J
CS11-E2GA4722MYNS
GRM43DR72J104KW01L
CS11-E2GA222MYNS
BZX384-B3V3
Diode; SM; SMA
S1M
1kV; 1A; Standard Recovery
Diodes Inc
S1M-13-F
Ind; TH; -
880µ
Core:Magmetics 0077071-A7
HT22; ; AWG16,85T.
-
Intersil Engineering
CMC; TH; -
2.2m
Common Mode Choke
Wurth
7448258022
Submit Document Feedback
9
Panasonic-ECG
ERZV14D391
Yageo
KNP100JR-73-0R22
AN1885.0
March 20, 2014
Application Note 1885
Bill of Materials
(Continued)
QTY
REFERENCE
DESIGNATOR
2
R8, R11
Res; SM; 1206
470k
1%;
1
R9
Res; SM; 0603
3k
1%;
1
R13
Res; SM; 0603
6.2k
1%;
1
R15
Res; SM; 0603
390k
1%;
1
R18
Res; SM; 0603
62k
1%;
1
R19
Res; SM; 0603
42.2k
1%;
1
R20
Res; SM; 0603
16k
1%;
1
R23
Res; SM; 0603
82k
1%;
1
R24
Res; SM; 0603
30k
1%;
1
R26
Res; SM; 0603
49.9
1%;
2
R27, R28
Res; TH; Axial
0.11
2W; 5%; WW
1
R29
Res; SM; 0603
150k
1%;
1
R30
Res; SM; 0603
59k
1%;
2
R45, R46
Res; SM; 0603
20k
1%;
1
R48
Res; SM; 0603
2.2k
1%;
1
U1
IC; SM; SOIC14
ISL6731A/B
1
U2
IC; SM; MSOP14
ISL28413
TYPE/PACKAGE
Submit Document Feedback
10
VALUE
VOL/TOL/MAT
Quad; 2M RRIO OpAmp
MANUFACTURER
MANUFACTURER PART #
Yageo
FKN200JR-73-0R1
Intersil
ISL6731AFBZ or
ISL6731BFBZ
Intersil
ISL28413FVZ
AN1885.0
March 20, 2014
Application Note 1885
PCB Layout
FIGURE 10. TOP LAYER
FIGURE 11. BOTTOM LAYER
Submit Document Feedback
11
AN1885.0
March 20, 2014
Application Note 1885
Assembly Drawing
R1
M4
P1
C6
R3
RV1
C36
C22
C5
C2
L3
L4
M3
AC1
P5 PE
C35
C26
AC2
P4
F1
I SL6731AEVAL2Z
I SL6731BEVAL2Z
Rev. A'
Rev. 6
H1
C3
R8
R11
P6
VCC
R49
C37 C7
Q6
U1
P2
+
C19
DC
-
P3
M2
C14
C23
C18
R31
R17
R26
R25
C24
R47
TP15
R32
U2
R30
R15
M1
R10
R6
TP17
R23
R20
R24
C4
TP4
RJ4
TP16
TP8
C1
TP3
C25
R45
Q5
RJ5
L2
R14
R46
Q4
TP6
C17
C10
C11
R13
C13
RJ6
R21
R48
R9
D1
TP5
R50
RJ3
- I SEN
TP13
C21
R18
R4
R2
TP2
R28
C12
TP11
R27
DZ1
TP1
R5
TP12
D2
Q1
C9
C20
C7A
DB1
D8
D7
GND
P7
R22
C16
R19
C15
R7
C8
Q3
R29
TP14
FIGURE 12. ASSEMBLY ON TOP
Submit Document Feedback
12
AN1885.0
March 20, 2014
Application Note 1885
Performance Curves and Typical Waveforms
98
98
96
94
90VAC-A
264VAC-A
230VAC-B
96
EFFICIENCY (%)
EFFICIENCY (%)
264VAC-B
230VAC-A
115VAC-A
92
115VAC-B
94
92
90VAC-B
90
90
88
88
0
10
20
30
40
50
60
LOAD (%)
70
80
90
0
100
FIGURE 13. EFFICIENCY vs LOAD, ISL6731AEVAL2Z
10
20
30
40
50
60
LOAD (%)
70
80
90
100
FIGURE 14. EFFICIENCY vs LOAD, ISL6731BEVAL2Z
1.00
1.00
115VAC-B
264VAC-A
90VAC-B
90VAC-A
0.95
PF
115VAC-A
0.95
PF
230VAC-A
264VAC-B
230VAC-B
0.90
0.90
0.85
0.85
0
10
20
30
40
50
60
70
80
90
0
100
10
20
30
40
FIGURE 15. POWER FACTOR vs LOAD, ISL6731AEVAL2Z
60
70
80
90
100
FIGURE 16. POWER FACTOR vs LOAD, ISL6731BEVAL2Z
14
14
12
12
264VAC-A
10
50
LOAD (%)
LOAD (%)
10
THD (%)
THD (%)
264VAC-B
230VAC-A
8
115VAC-A
6
8
230VAC-B
6
115VAC-B
90VAC-A
4
90VAC-B
4
2
2
0
0
0
10
20
30
40
50
60
LOAD (%)
70
80
FIGURE 17. THD vs LOAD, ISL6731AEVAL2Z
Submit Document Feedback
13
90
100
0
10
20
30
40
50
60
LOAD (%)
70
80
90
100
FIGURE 18. THD vs LOAD, ISL6731BEVAL2Z
AN1885.0
March 20, 2014
Application Note 1885
Performance Curves and Typical Waveforms
(Continued)
Iin, 2.0A/DIV
Iin, 5.0A/DIV
VLINE, 200V/DIV
VLINE, 200V/DIV
5.0ms/DIV
5.0ms/DIV
FIGURE 19. WAVEFORMS OF LINE CURRENT AND VOLTAGE
(115V/FULL LOAD)
FIGURE 20. WAVEFORMS OF LINE CURRENT AND VOLTAGE
(230V/FULL LOAD)
VDS, 100V/DIV
IL, 2.0A/DIV
VGS, 10V/DIV
5.0µs/DIV
FIGURE 21. SWITCHING WAVEFORMS
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is
cautioned to verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
Submit Document Feedback
14
AN1885.0
March 20, 2014
Similar pages