Download PDF

5
4
3
2
1
SCI_x_ANLG_CH_[0:15]
SCI_x_ANLG_CH_0
SCI_x_ANLG_CH_1
SCI_x_ANLG_CH_2
SCI_x_ANLG_CH_3
SCI_x_ANLG_CH_4
SCI_x_ANLG_CH_5
SCI_x_ANLG_CH_6
SCI_x_ANLG_CH_7
SCI_x_ANLG_CH_8
SCI_x_ANLG_CH_9
SCI_x_ANLG_CH_10
SCI_x_ANLG_CH_11
SCI_x_ANLG_CH_12
SCI_x_ANLG_CH_13
SCI_x_ANLG_CH_14
SCI_x_ANLG_CH_15
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
SCIX_CON_1
54
56
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
AFE/SCI_COM_0
AFE/SCI_COM_1
AFE/SCI_COM_2
AFE/SCI_COM_3
D
GND
GND
SCI_x_SPI_MISO
SCI_x_SPI_MOSI
SCI_x_SPI_CLK
SCI_x_SPI_CS
D
53
55
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
GND
GND
2x26
QRM8-026-02.0-L-D-A
SCI_x_GPIO_[0:3]
P2
AFEx/SCIx_ANLG_VDD
SCI_x_GPIO_3
SCI_x_GPIO_2
SCI_x_GPIO_1
SCI_x_GPIO_0
C
C
AFEx/SCIx_ANLG_VSS
SCI_x_PWR_GOOD
AFE/SCI_x_I2C_SDA
AFE/SCI_x_I2C_SCL
REFERENCE
AFEx/SCIx_REF_VSS
AFEx/SCIx_REF_VDD
MAVRK_SCI_x_MOD_SEL
MAVRK_SCI_x_MOD_IRQ
AVDD_5_5V
SCI_DVDD_3_3V
R1
0.10
R2
0.10
SCI_AVDD_5_5V
DVDD_3_3V
R3
200K
B
B
See MAVRK SCI
Design Guide
(www.ti.com/mavrk)
VDD_AUX_x
SCI_EXT_VDD
Current Sense
C1
10uF
10V
C2
10uF
10V
R5
680
SCI MODULE TO MB INTERFACE
1
6
6F
6E
6D
SCIX_CON_2
1x6 PWR HDR
POWER
UPT-06-03.0-01-L-V
SCI_x_TO_PMU_VIN
TP1
SCI_x_TO_PMU_VIN
D1
GRN
SCI_x_AVIN
A
2
6A
6B
6C
5
5A
5B
5C
4
3F
3E
3D
3
2
2F
2E
2D
4F
4E
4D
4A
4B
4C
Black
3A
3B
3C
Black
2A
2B
2C
1F
1E
1D
1
A
TP3
GND
1A
1B
1C
TP2
GND
5F
5E
5D
TO USE POWER COMING IN
FROM SCREW TERMINALS ON
THE MOTHERBOARD, CONNECT
TO SCI_EXT_VDD
Resistor
LB1
LB2
BOM 1.4
5
4
Title
Approval
THIS PIN CAN BE USED TO POWER THE
MOTHERBOARD. POWER INPUT HERE MUST
BE REGULATED BETWEEN 4.5V AND 5.5V.
SCI-XXXXXX-MVK
3
Designer
XXXX XXXX
Drawn By
XXXX XXXX
Layout
XXXX XXXX
SCI-TEMPLATE-MVK
Size B
EDGE No <Project Number>
Date Friday, August 05, 2011
2
1
Rev 1.4
Page 1 of 3
5
4
3
2
AFEx/SCIx_REF_VDD
Generate Positive Rails
SCI_AVDD_5_5V
U2
R8
1
0 OHM
J1
1
2
3
VIN
SW
C8
10uF
10V
3
EN
LDO Enable Select
8
2
R11
56K
GND
C6
1.0uF
10V
IN OUT
EN 2.5V
GND NR
R7
5
D
0 OHM
4
C7
1.0uF
10V
C5
0.01uF
16V
TPS71725DCK
R12
6
PG
TPS62120DCN
SCI_x_GPIO_3
C4
10uF
10V
1
3
2
AFEx/SCIx_ANLG_VDD
R10
220K
4
SGND
U1
0 OHM
C9
12pF
5
VOUT
C3
10uF
10V
R9
604K
18uH
FB
POWER_ENABLE
L1
7
ANLG_VDD +2.5V
TP4
ANLG_VDD +2.5V
+3V
TP5
R6
D
1
100K
C
C
SCI_AVDD_5_5V
AVSS -3V
R13
U3
R14
10
5
3
C13
0.1uF
10V
4
2
7
11
IN
VIN
EN
VREF
FB
OUT
GND
SW
PS_GND
PPAD
COMP
TPS63700DRC
C18
4700pF
50V
C11
0.22uF
16V
10
Generate Negative Rails
R15
200K
9
C12
D2
6
2
1
10pF
16V
R16
499K
8
AFEx/SCIx_REF_VSS
R17
100K
CDBU0520
C14
10uF
10V
ANLG_VSS -2.5V
-3V
TP7
R18
1
1
0 OHM
0 OHM
C15
10uF
10V
L2
4.7uH
ANLG_VSS -2.5V
TP6
U4
C16
1.0uF
10V
2
3
1
IN OUT
EN
GND FB
R19
5
4
TPS72301DBVT
AFEx/SCIx_ANLG_VSS
C17
2.2uF
6.3V
R20
48.7K
0 OHM
2
C10
10uF
10V
R21
37.4K
B
B
Split Rail Power Circuit
A
A
Title
XJ1
Size B
SCI-TEMPLATE-MVK
EDGE No
XXXXXXX
Rev
1.4
240
Shunt_100
5
4
3
2
Date Friday, August 05, 2011
Page 2 of 3
1
5
4
3
2
1
Generate Positive Rails
D
D
SCI_AVDD_5_5V
Ref+ +5.35V
TP8
Ref+ +5.35V
U5
R22
0 OHM
1
3
2
C19
1.0uF
10V
J2
1
2
3
IN
OUT
EN
GND NR/FB
4
R24
1.80M
TPS71701DCK
LDO Enable Select
AFEx/SCIx_REF_VDD
5
C20
1.0uF
10V
R25
316K
R23
56K
SCI_x_GPIO_3
P1
ANLG_VDD +5V
AFE_LDO_ENABLE
ANLG_VDD +5V
TP9
U6
R26 0 OHM
1
3
2
C
C21
1.0uF
10V
IN
OUT
EN
GND NR/FB
TPS71701DCK
AFEx/SCIx_ANLG_VDD
5
4
R27
0 OHM
R28
1.65M
C
C22
1.0uF
10V
R29
316K
AFEx/SCIx_REF_VSS
AFEx/SCIx_ANLG_VSS
R31
R32
0 OHM
0 OHM
B
B
IF USING SINGLE RAIL CONFIGURATION, CONNECT THESE
TWO SIGNALS DIRECTLY TO ANALOG GROUND BY
REMOVING THE 0 OHM RESISTORS
Single Rail Power Circuit
A
A
Title
XJ2
Size B
SCI-TEMPLATE-MVK
EDGE No
XXXXXXX
Rev
1.3
240
Shunt_100
5
4
3
2
Date Friday, August 05, 2011
Page 3 of 3
1
Similar pages