### an1612

```Application Note 1612
ISL6844 Reference Design: ISL6844EVAL3Z
Introduction
Where:
This document focuses on Intersil’s solution for the flyback
converter. An inexpensive approach with discrete circuitry has
optimal performance are the prime objectives.
POUT = Total output power
Intersil’s superior industry-standard ISL684x family of PWM
controllers would best serve the needs of this design. Some
key features of this family of parts include:
• 40ns peak current sensing
• 1A MOSFET driver
η = Converter’s efficiency, assuming 75%
Fsw = Switching frequency
As a result, the peak magnitizing current = 1.06A
The transformer’s turn ratio can be determined from:
( V out + V F ) ⋅ ( 1 – d 2 )
n = -------------------------------------------------------V IN, MIN ⋅ d MAX
(EQ. 2)
d MAX + d 2 < 1
ISL6844 was selected for its large UVLO hysteresis, UVLO start
threshold, and the fact that the converter has been designed
for a maximum operational duty cycle of 50%, thus protecting
the IC by limiting the duty cycle in case of extreme fault
conditions.
Where:
Specifications
VF = Forward drop across the diode, assuming 0.6V
n = Turns ratio between the primary and the secondary
windings
• Operating Input Voltage: 24V DC ±10%
d2 = Duty cycle of diode conduction time
• Output Voltage: ±15V
d2Tsw is the magnitizing current reset time. Setting d2 to 0.5,
Equation 2 yields the transformer’s turn ratio of 1.
• Output Current: 100mA
D1
• Ripple: 50mVP-P
1
VIN
CIN
• Switching Frequency: 300kHz
n
+15V
COUT1
CS
RS
DS
n
• Topology: DCM Flyback
COUT2
D2
Design Procedure
OUT
-15V
CS
Figure 1 shows a simplified circuit of the solution. It is
assumed that loads are balanced for both positive and
negative outputs. The turn ratio of the auxiliary winding is
chosen to be the same as the secondary winding. Figure 2
shows typical operational waveforms of a flyback converter in
discontinuous conduction mode.
Determine the Maximum Duty Cycle and
Transformer Turn Ratio
RSENSE
VIN
ISL6844
VREG
n
VDD
FB
CAUX
GND
FIGURE 1. SIMPLIFIED CIRCUIT
ISL6844 clamps the duty cycle to 50%. However, in this
converter design, it is assumed that the operating maximum
duty cycle, dmax, will be 35% at the minimum input voltage of
21.6V.
Given the power level, the flyblack converter is designed to
operate in discontinuous conduction mode. The magnitizing
inductance can be calculated using Equation 1:
2
2
V IN, MIN ⋅ d max
L M = η ⋅ ----------------------------------------2 ⋅ P out ⋅ F sw
2
(EQ. 1)
2
21.6 ⋅ 0.35
= 0.75 ⋅ -------------------------------------- = 23.8μH
3
2 ⋅ 3 ⋅ 300 ×10
November 28, 2011
AN1612.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
Application Note 1612
The transformer used in this design is Pulse’s PA3374Nl. It is a
gapped ferrite toroid core, which has the following parameters:
TSW
ILM
Ipk
• Ae = 4.3mm2
• AL = 35nH/n2
• le = 13.1mm
Ipri
dTSW
MOSFET ON
DIODES (D1 AND
D2) OFF
d2TSW
MOSFET OFF
DIODES (D1 AND
D2) ON
• Ve = 56.5mm3
d3TSW
MOSFET OFF
DIODES (D1
AND D2) OFF
This section provides general guideline to calculate the number
of turn and wire size. For more details on designing transformer
Ipk
The number of turns on the primary side, Np, can be determined
from:
L [ uH ] × 1000
-----------------------------------AL
Np =
Isec,1
=
<Iout,1>
(EQ. 5)
23.8 × 1000
------------------------------- = 26.07
35
Therefore, the primary side has 26 turns. With the turn ratio of 1,
the secondary side and the auxiliary primary side also have 26
turns.
Next the calculate the maximum flux density to make sure that it
is below the saturation limit.Where:
Isec,2
L M ⋅ I M, max
B max = -------------------------------Np ⋅ Ae
(EQ. 6)
–6
<Iout,2>
For the operating power level, the wire sizes of the primary,
secondary, and auxiliary windings are selected such that the
current density in each winding is about 0.25335 cm2/A (50
circular mil/A).
FIGURE 2. TYPICAL OPERATIONAL CURRENT WAVEFORMS
Transformer Core Selection
From Figure 2, the RMS current in the transformer primary side
can be calculated from:
d
I rms, pri = I pk ⋅ --3
4
23.8 ×10 ⋅ 1.06
= ------------------------------------------- ×10 = 0.226T
–2
26 ⋅ 4.3 ×10
(EQ. 3)
0.35
= 1.06 ⋅ ----------- = 0.362A
3
The RMS current in each transformer secondary side can also be
computed from:
A w, pri ≥ 0.25335 ⋅ 0.362 = 0.0917cm
2
To simplify transformer winding, AWG#37 is used for all primary,
secondary and auxiliary windings.
Primary MOSFET Selection
The primary MOSFET needs to be able to handle the voltage
stress, given by:
V DSFET = V
IN, MAX
+ [ n × ( V out + V f ) ]
= 26.4 + [ 1 × ( 15 + 0.6 ) ] = 42V
I pk d
I rms, sec = ------- ⋅ -----22
3
(EQ. 7)
(EQ. 8)
(EQ. 4)
As a good design practice, some margin is provided to this peak
stress voltage to accommodate transient spikes and for a good
reliable performance over time. Providing a 30% design margin
as a rule of thumb, the minimum rating on the primary MOSFET
needs to be 54.6V.
1.06 0.5
= ----------- ⋅ -------- ⋅ = 0.216A
2
3
2
AN1612.1
November 28, 2011
Application Note 1612
The RMS current through the MOSFET can be calculated from:
I rms, FET = I pk ⋅ d
--3
(EQ. 9)
P L = W L ⋅ F SW
= 267.4 ×10
0.35
= 1.06 ⋅ ----------- = 0.362A
3
Selecting the conduction loss in the MOSFET to 1% of total output
power, 0.03W. The required MOSFET’s rDS(ON) to achieve the
required conduction loss is shown in Equation 10.
P FET, cond – loss
r DS ( ON ) = ------------------------------------------2
I FET, rms
Average power transferred to the snubber circuit is:
–9
(EQ. 14)
3
⋅ 300 ×10 = 0.08W
To limit peak voltage spikes across the MOSFET to 50V, the
snubber voltage is set to:
V S = peakV MOSFET – V IN, MIN
(EQ. 15)
= 50 – 21.6 = 28.4V
(EQ. 10)
0.03
= ------------------ = 0.229Ω
2
0.362
The average power transferred to the snubber circuit in
Equation 14 is dissipated by the snuuber resistor, so RS is
determined by:
2
VS
R S = ------Pl
Vishay’s SI4436DY is selected in this design.
Output Diode Selection
Schottky diodes are recommended for the output diode due to
their low forward voltage drop. The voltage stress across the
output diode can calculated by:
V Diode = n × V
IN, MAX
+ V OUT
(EQ. 11)
= 1 × 26.4 + 15 = 41.4V
The output capacitance needs to meet the ripple and noise
requirements, and also be able to handle the ripple current.
Assuming ceramic capacitors are used as the output filter, the
voltage ripple from the capacitor’s ESR is negligible. The
minimum capacitance required to meet specifications can be
approximately calculated from Equation 12.
ΔV PP ( 1 – d 2 ) ⋅ T SW
C OUT > --------------- ⋅ ------------------------------------2
I OUT
–3
( 1 – 0.5 )
50 ×10
> ---------------------- ⋅ ----------------------------------3
2
0.1 ⋅ 300 ×10
(EQ. 12)
10µF ceramic capacitors are selected for each output. Design
margin has been provided to account for noise spikes.
Snubber Circuit
When the MOSFET switches off, it interrupts the current that
flows through the transformer leakage inductance. An RCD
snubber circuit is typically used in flyback converters to clamp
voltage spikes on the MOSFET.
Assuming that the transformer leakage inductance is 2% of the
magnitizing inductance, the energy stored in the leakage
inductance during MOSFET’s on-time is:
3
(EQ. 17)
–6
3.33 ×10
= 10 ⋅ --------------------------- = 3.33nF
3
10 ×10
Output Filter
1
2
W L = --- ⋅ L L ⋅ I LM
2
–6
1
= --- ⋅ 0.02 ⋅ 23.8 ×10 ⋅ ( 1.06 ) 2 = 267.4nJ
2
So RS = 10kΩ is selected. Cs is selected such that the RSCS time
constant is substantially longer than the switching period to keep
low ripple voltage on the snubber circuit. A time constant of 10
times the switching period is used for calculation:
T SW
C S ≈ 10 ⋅ -----------RS
Diodes Inc’s B180 are employed in this design.
> 0.42μF
(EQ. 16)
2
28.4
= -------------- = 10.08kΩ
0.08
(EQ. 13)
CS = 3.33nF is used in the design.
Feedback Network
The feedback is being tapped off of the primary auxiliary
winding. This is one of the advantages of selecting the flyback
topology, since the auxiliary winding voltage follows the output.
This scheme was fully exploited, since the load fluctuation is
minimal, and that load regulation does not suffer much at these
power levels. For tighter regulation requirements, an
opto-coupled solution would need to be used, which leads to
Referring to the schematic on page 8, the output voltage can be
set by:
V OUT + V F
R 22
---------- = ----------------------------–1
R 23
V ref
15 + 0.6
= --------------------- – 1 = 5.2
2.514
(EQ. 18)
R23 = 1kΩ and R22 = 5.23kΩ are selected.
The control-to-output transfer function of the DCM flyback
converter is [1]:
R E ⋅ L M ⋅ F SW
1 + s ⋅ ESR ⋅ C
- ⋅ ------------------------------------------------------G vc = K ⋅ -----------------------------------( 1 + s ⋅ 0.5 ⋅ R E ⋅ C E )
2
(EQ. 19)
Where:
RE = Equivalent load resistor reflected to the auxiliary output.
AN1612.1
November 28, 2011
Application Note 1612
CE = Equivalent capacitor reflected to the auxiliary output.
40
ESR = Equivalent series resistance of the output capacitor.
1W TOTAL OUTPUT
K = ISPK(MAX)/VC(MAX).
3W TOTAL OUTPUT
The equivalent load reflected to the auxiliary output can be
estimated from:
2
V aux
R E = ---------------------------------P OUT ( Total )
(EQ. 20)
2
( 15V )
= ------------------- = 75Ω
3W
GAIN (GVC)
20
0
20
The equivalent capacitor reflected to the auxiliary output can be
estimated from:
N S1
N S2
+ ------------- ⋅ C
C E = C aux + ------------- ⋅ C
N aux
N
OUT1
aux
OUT2
1 .10
100
3
1 .10
1 .10
1 .10
5
From Equation 23, the pole of the control-to-output transfer
function for 3W output is located at 202Hz. Setting the
closed-loop’s bandwidth of 10kHz, the feedback compensation
must have a mid-band gain of 3.11 (10dB). The mid-band gain is
determined by
R 24
A mid – band = ---------R 22
(EQ. 22)
(EQ. 24)
Therefore, R24 is selected to be 16.2kΩ.
POUT(MAX) = The maximum power allowed = 4W
The first zero of compensation is set at 1/3 of the crossover
frequency, 3.33kHz. C9 can be calculated from:
VC(MAX) has value of 1.1V, clamped by ISL6844’s internal circuit.
Along with the result from Equation 22, K has a value of 0.97.
1
C 9 = -------------------------------------------------------------------3
3
2 ⋅ π ⋅ 3.33 ×10 ⋅ 16.2 ×10
Replaces K and the results from Equation 21 and Equation 22
into Equation 19, yields
1
G vc = 15.87 ⋅ ---------------------------------------------------–4
( 1 + s ⋅ 7.875 ×10 )
6
FIGURE 3. GAIN OF G VC
(EQ. 21)
The value of ISPK(MAX) can be determined by assuming that the
auxiliary output delivers all of the output power.
4W
2 ⋅ ----------15V
= ------------------- = 1.067A
0.5
4
FREQUENCY (Hz)
15
15
= 1μF + ------ ⋅ 10μF + ------ ⋅ 10μF = 21μF
15
15
P OUT ( MAX )
2 ⋅ -------------------------------V AUX
I SPK ( MAX ) = ----------------------------------------D2
40
10
(EQ. 23
Note that with the low ESR values of the output ceramic
capacitor, the zero due to their ESR is located at the frequency
significantly higher than the switching frequency. As the result,
the impact of capacitor’s ESR is neglected for compensator
design.
(EQ. 25)
= 2.95nF
2.7nF is used for C9.
The second zero of compensation is set at half of the switching
frequency. C10 can be calculated from:
1
C 10 = ------------------------------------------------------------------3
3
2 ⋅ π ⋅ 150 ×10 ⋅ 16.2 ×10
(EQ. 26)
= 65.5pF
68pF is used for C10.
From Equation 20, it shows that when the total output power
reduces, the equivalent load resistor increases. This increases
the DC-gain in Equation 19, also the pole is moved to the lower
frequency.
4
AN1612.1
November 28, 2011
Application Note 1612
Printed Circuit Board
The fixture of the PCB is a 2-layer board with dimensions of 4 by
6 centimeters. All components are surface-mount packages and
are placed in the top layer.
TABLE 1. TERMINAL
TERMINALS
SIGNALS
P1
VIN (Input voltage)
P2
RTN (Input ground return)
P3
+15V (+15V output voltage)
P4
+15V(-15V output voltage)
P5,P6
GND (Output ground)
Reference
[1] Dixon, Lloyd H., “Closing the Feedback Loop”, Unitrode Power
Supply Design Seminar, slup068, 1984.
FIGURE 4. EVALUATION BOARD PHOTO (TOP SIDE)
FIGURE 5. EVALUATION BOARD PHOTO (BOTTOM SIDE)
5
AN1612.1
November 28, 2011
Application Note 1612
Typical Performance Curves
FIGURE 6. START UP AT NO LOAD
FIGURE 7. START UP AT FULL LOAD
FIGURE 8. OUTPUT RIPPLES AT NO LOAD
FIGURE 9. OUTPUT RIPPLES AT FULL LOAD
17.5
OUTPUT VOLTAGES (V)
EFFICIENCY (%)
85
80
75
70
65
60
55
50
45
40
0
0.5
1.0
1.5
2.0
2.5
TOTAL OUTPUT POWER (W)
FIGURE 10. EFFICIENCY
6
3.0
3.5
17.0
16.5
VOUTP
16.0
15.5
15.0
VOUTN
14.5
0
0.5
1.0
1.5
2.0
2.5
TOTAL OUTPUT POWER (W)
IOUTP = IOUTN
3.0
3.5
FIGURE 11. OUTPUT VOLTAGE REGULATIONS
AN1612.1
November 28, 2011
Application Note 1612
Typical Performance Curves
(Continued)
FIGURE 12. OVER CURRENT RESPONSE
7
AN1612.1
November 28, 2011
Schematic
C13
1
2
2
1
R11
5.1
1nF/2kv
D4
1
1
10
1
1
1
C16
0.1uF
R25
4.02k
1
P5
RTN
1
C17
0.1uF
1
C18
0.1uF
2
C24
10uF
1
2
C14
0.1uF
2
2
1
2
R26
4.02k
1
2
1
C8
1uF
2
2
D5
8
R15
D1
+15V
P6
RTN
P4
-15V
B180
2
BAT54
2
U1
7
2
R10
5.1
1
C15
5
2.2uF
R6
1
R5
1k
2
100
1
2
2
1
2
R1
0.82ohm
VDD
FB
OUT
CS
GND
RTCT
1
2
C6
150pF
16.2k
1
R22
10k
2
3
4
1
2
R4
10k
1
COMP
ISL6844
1
DNP
10uF
1
2
Q2
SI4436DY
1
D7
BZT52C18
C11
2
6
VREF
C9
2.7nF
2
1
1
8
1
R23
2k
2
VREF
R24
1
C10
68pF
2
2
R3
12.1k
C12
220pF
2
1
Application Note 1612
Vin-
C23
10uF
1
2
BAT46W
4
21
1
2
2
6
7
D2
BAT46W
D3
1
R14
6.49k
1
2
3
1
2
CS
3.3nF
2
1
C4
1uF
P2
RS
10k
1
C3
10uF
2
8
POWER INPUT
24V
P3
1
1
B180
2
Vin+
1
1
5
1
1
2
2
1
T1
2
P1
AN1612.1
November 28, 2011
Application Note 1612
Bill of Materials
REF DES
QTY
PART NUMBER
U1
1
ISL6844IUZ
IC, PWM Controller
Q2
1
SI4436DY
MOSFET, N-channel, 60V
D1
1
BAT54WS
Schottky Diode, 30V
SOD323F
Diodes Inc.
D2, D3
2
BAT46W
Schottky Diode, 100V
SOD123
Diodes Inc.
D4, D5
2
B180
Schottky Diode, 80V, 1A
SMA
Diodes Inc.
D7
DNP
BZT52C18
Zener Diode 18V
SMA
T1
1
PA3374NL
Transformer, Custom
C3
1
C5750X7R1H106K
Capacitor, ceramic, X7R, 10µF, 20%,
50V
SM_2210
Generic
C4
1
Capacitor, ceramic, X7R, 1.0µF, 20%,
50V
SM_0805
Generic
C6
1
Capacitor, ceramic, X5R, 150pF, 20%,
50V
SM_0603
Generic
C8
1
Capacitor, ceramic, X5R, 1.0µF, 20%,
25V
SM_0805
Generic
C9
1
Capacitor, ceramic, X5R, 2.7nF, 20%,
50V
SM_0603
Generic
C10
1
Capacitor, ceramic, X5R, 68pF, 20%, 50V
SM_0603
Generic
C11
1
Capacitor, ceramic, X5R, 10µF, 20%,
25V
SM_1206
Generic
C12
1
Capacitor, ceramic, X7R, 220pF, 20%,
50V
SM_0603
Generic
C13
1
Capacitor, ceramic, X7R, 1000pF, 10%,
2kV
SM_1808
TDK
C14, C16, C17,
C18
4
Capacitor, ceramic, X7R, 100nF, 10%,
50V
SM_0603
Generic
CS
1
Capacitor, ceramic, X7R, 3.3nF, 20%,
50V
SM_0805
Generic
C15
1
Capacitor, ceramic, X7R, 2.2µF, 20%,
10V
SM_0603
Generic
C4520X7R3D102K
DESCRIPTION
PACKAGE
MSOP-8
SOP-8
VENDOR
Intersil
Vishay
Diodes Inc.
Pulse
C23, C24
2
Capacitor, ceramic, X5R, 10µF, 10%, 25V
SM_1812
Generic
R1
1
Resistor, 0.82Ω, 1%, 1/4W
SM_1206
Generic
R3
1
Resistor, 12.1kΩ, 1%, 1/16W
SM_0603
Generic
R4, R22
2
Resistor, 10kΩ, 5%, 1/16W
SM_0603
Generic
R5
1
Resistor, 1kΩ, 1%, 1/16W
SM_0603
Generic
R6
1
Resistor, 100Ω, 1%, 1/16W
SM_0603
Generic
R10, R11
2
Resistor, 5.1Ω, 1%, 1/16W
SM_0603
Generic
R14
1
Resistor, 6.49kΩ, 1%, 1/16W
SM_0603
Generic
R15
1
Resistor, 10Ω, 1%, 1/16W
SM_0603
Generic
RS
1
Resistor, 10kΩ, 5%, 1/4W
SM_1206
Generic
R23
1
Resistor, 2kΩ, 1%, 1/16W
SM_0603
Generic
R24
1
Resistor, 16.2kΩ, 5%, 1/16W
SM_0603
Generic
R25, R26
2
Resistor, 4.02kΩ, 5%, 1/16W
SM_0603
Generic
9
AN1612.1
November 28, 2011
Application Note 1612
ISL6844EVAL3Z Printed Circuit Board Layers
FIGURE 1. ISL6844EVAL3Z - TOP LAYER (SILKSCREEN)
FIGURE 2. ISL6844EVAL3Z - TOP LAYER (COMPONENT SIDE)
FIGURE 3. ISL6844EVAL3Z - BOTTOM LAYER (SOLDER SIDE)
FIGURE 4. ISL6844EVAL3Z - BOTTOM LAYER (SILKSCREEN)
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is
cautioned to verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
10
AN1612.1
November 28, 2011
```