DATASHEET

DATASHEET
Power Factor Correction Controllers
ISL6731A, ISL6731B
The ISL6731A and ISL6731B are active power factor
correction (PFC) controller ICs that use a boost topology. The
controllers are suitable for AC/DC power systems up to 2kW
and over the universal line input.
The ISL6731A and ISL6731B operate in Continuous Current
Mode (CCM). Accurate input current shaping is achieved with a
current error amplifier. A patent pending breakthrough
negative capacitance technology minimizes zero crossing
distortion and reduces the magnetic components size. The
small external components result in lower design cost without
sacrificing performance.
The internally clamped 12.5V gate driver delivers 1.5A peak
current to the external power MOSFET. The ISL6731A and
ISL6731B provide a highly reliable system that is fully
protected. Protection features include cycle-by-cycle
overcurrent, over power limit, over-temperature, input
brownout, output overvoltage and undervoltage protection.
The ISL6731A and ISL6731B provide excellent power
efficiency and transitions into a power saving skip mode
during light load conditions, thus improving efficiency
automatically. The ISL6731A and ISL6731B can be shut down
by pulling the FB pin below 0.5V or grounding the BO pin.
Two switching frequency options are provided. The ISL6731B
switches at 62kHz, and the ISL6731A switches at 124kHz.
• Reduced component size requirements
- Enables smaller, thinner AC/DC adapters
- Choke and cap size can be reduced
- Lower cost of materials
• Excellent power factor and THD over line and load
- CCM mode with negative capacitance generator for
smaller EMI filter and improved performance
- Built-in current amplifier with flexibility of gain change
• Better light-load efficiency
- Automatic pulse skipping with programmable threshold
- Programmable or automatic shutdown
• Highly reliable design
- Cycle-by-cycle current limit
- Input average power limit
- OVP and OTP protection
- Input brownout protection
• Small 14 Ld SOIC package
Applications
• Desktop computer AC/DC adaptor
• Laptop computer AC/DC adaptor
Related Literature
• AN1884, "ISL6731AEVAL1Z and ISL6731BEVAL1Z: Boost
CCM PFC for 300W Universal Input Adaptors"
• AN1885, “ISL6731AEVAL2Z and ISL6731BEVAL2Z: High
Performance Boost CCM PFC Front End for Server Power
Applications”
• TV AC/DC power supply
• AC/DC brick converters
100
VI
VLINE
Features
+
VOUT
95
VCC
ISEN
GATE
ICOMP
VIN
OVP
ISL6731A FB
COMP
GND
BO
SKIP VREG
EFFICIENCY (%)
90
85
80
February 13, 2015
FN8582.1
1
ISL6731A, NON-SKIP
75
70
65
60
FIGURE 1. TYPICAL APPLICATION
ISL6731A, SKIP
0
20
40
60
OUTPUT POWER (%)
80
100
FIGURE 2. PFC EFFICIENCY
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2014, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL6731A, ISL6731B
Pin Configuration
ISL6731A, ISL6731B
(14 LD SOIC)
TOP VIEW
NC 1
14 GATE
GND 2
13 NC
ISEN 3
12 VCC
ICOMP 4
11 VREG
VIN 5
10 SKIP
BO 6
9 FB
OVP 7
8 COMP
Pin Descriptions
PIN #
I/O
SYMBOL
1, 13
-
NC
2
-
GND
Ground pin. All voltage levels refer to this pin.
3
I
ISEN
Current sense pin. The current through this pin is proportional to the inductor current.
4
I/O
ICOMP
5
I
VIN
Input voltage sense. This pin provides the reference voltage to shape inductor current. Connect this pin to a resistor divider
from the rectified input voltage. The resistor divider ratio is used to adjust the phase lag between input voltage and the
input current. The phase lag is required to compensate the phase lead generated by the EMI filter.
6
I/O
BO
This pin should be decoupled to GND with a minimum 0.1µF ceramic capacitor. The BO pin is a voltage follower, which will
follow the DC voltage of the VIN pin. The BO pin is internally tied to GND through a resistor RIS. The decoupling capacitor
provides ripple filtering. When the voltage at the BO pin (VBO) drops below brownout voltage threshold, the controller
enters shutdown mode and the gate drive is disabled. The BO pin will be disabled when the FB pin drops below the enabling
threshold.
7
I
OVP
Overvoltage protection pin. Connect this pin to a resistor divider from the output. The resistor divider sets the OVP set point.
When the OVP pin voltage exceeds 104.5% of the reference voltage VREF, OVP is triggered and the gate drive is disabled.
8
I/O
COMP
Output of the error amplifier. The voltage of the COMP pin sets the input power. During start-up, a small charge current will
slowly ramp up the voltage of the COMP pin.
9
I
FB
Voltage feedback pin. Connect this pin to a resistor divider from the output. The resistor divider sets the output voltage.
When the FB pin voltage exceeds 104% of VREF, OVP is triggered and gate drive is disabled. When the FB pin drops below
10% of VREF, the device is put into shutdown mode. There is an internal pull-down current source for open loop protection.
10
I/O
SKIP
This pin has dual functions. Connecting this pin to ground disables the light load skip function. An internal 20μA current
sources out of this pin. Connect a resistor from this pin to the ground to set the average power trip point. The converter
exits the skip mode when either the VFB drops below 88% of VREF, or the ISEN current goes above 29μA.
11
-
VREG
Output of internal regulator. The voltage having a ±2% tolerance over line, load and operating temperature. Bypass to GND
with a 47nF low ESR capacitor. VREG can source up to 10mA. This pin is not recommended for usage other than bypass.
12
I
VCC
Power supply pin. The VCC pin should be decoupled to GND with a minimum 0.1µF ceramic capacitor.
14
O
GATE
Push-pull gate drive for the external MOSFET. Output voltage is clamped at 12.5V. This pin provides typically 2A sink and
1.5A source capability.
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DESCRIPTION
Not Connected. Must be floating.
Current error amplifier output pin.
2
FN8582.1
February 13, 2015
ISL6731A, ISL6731B
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP.
RANGE (°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL6731AFBZ
ISL 6731AFBZ
-40 to +125
14 Ld SOIC
M14.15
ISL6731BFBZ
ISL 6731BFBZ
-40 to +125
14 Ld SOIC
M14.15
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6731A, ISL6731B. For more information on MSL please see techbrief
TB363.
TABLE 1. KEY DIFFERENCES IN FAMILY OF ISL6731
VERSION
ISL6731A
ISL6731B
Switching Frequency
124kHz
62kHz
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FN8582.1
February 13, 2015
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Block Diagram
VI
EMI CHOKE
D
LF
VLINE
CF2
CF3
VOUT
L
CF1
COUT
Q1
Lm
DF1
RCS
4
DF2
CREG
VCC
2:1
RSEN
ISEN
LINEAR
REGULATOR
UVLO
VCC
GATE
I OC
I CS > -------------2
I CS
CONTROL
LOGIC
GND
OTP
PWM
COMP
SKIP
Vro2
ROV1
OVP
CEQ GEN.
R IS ¥ I ISEN
V CS = ---------------------------------2
ICOMP
IREF
Gmi
RIS
OSCILLATOR
SOFT-START
ENABLE
0.25 ¥ VIN
----------------------------COMPB
2
BO
RIN2
ROV2
Vro1
Vref
VIN
COMPB
SKIP
CLAMP
COMP-1V
RFB2
OVERPOWER
LIMIT
FB
Gmv
20µA
RIN1
SKIP
BO
FN8582.1
February 13, 2015
CBO
IFB
COMP
RFB1
ISL6731A, ISL6731B
CURRENT
MIRROR
VREG
Typical 300W Application Schematic
D1
IN5406
TP9
P2
2
1
R28 0.22
R27 0.22
R5 0.22
2.2n 2.2n
C5 C6
C21
0.1
R4
51k
C19
C1 0.1
270u
450V
390V
3
R2
2.2
RV1
MOV /DNP
2
C3
680n
Q1
1
SPP20N60C3
P3
GND
C8
220n
D8 D7
S1M S1M
47n
C20
R23
3.3M
6
3
2
1
13
C9
TP7
DNP 1u
DNP
VCC
VREG
GATE
C11
TP8
R8
R24
1n
C7
470k
U1
3.3M
6.8n
1u
VREG Lin.Reg. VCC
C10
GATE 14
UVLO LOGIC
4 ICOMP
R9
TP6
R11
3k
GND 2
ICOMP
CEQ OTP
470k
3 ISENI MIRROR
Gen
2:1
TP5 ISEN
OVP 7
PWM
Vin*C
I*= 4*BO*BO I*
gm
VIN
C23
2.5V
5 VIN
1n
C SKIP OPL
TP3
9
FB
gm
+
SKIP
COMP
BO
R13
C13
VCC
ISL6731A/B
5.76k
47p
R21
TP4 69.8K
TP2
25k
R22
DNP
2N7002
BO
COMP
Q2
1
DNP
DNP P8
C15
R18
150n
C14
62k
DNP
C17
470n
R20
1n
10k
DNP
C18
P9
1u
DNP
R14
30k
11
C12
DNP
DZ1
3.3V
TP10
3.3M
R6
C26
2.2n
R10
3.3M
DNP
TP11
VCC
OVP
42.2k
R25
R26
49.9
TP1
GND
FB
R17
0
8
3
+
470n
DC+
C3D04060A
12
R3
2M
DB1
GBU806
VOUT
1
C16
100n
R19
42.2k
P6
P7
ISL6731A, ISL6731B
PE
P5
2.2n
C36
L3
2.2m
4
2.2n
C35
1
AC2
L4
2.2m
D2 2
TP12
GATE1
C22
470n
L2
1.5m
L1
0u
10
P4
R1
2M
C2
4
5
UNIVERSAL INPUT
90~265Vac
2
F1 8A
3
AC1
2
P1
1
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Application Schematics
FN8582.1
February 13, 2015
(Continued)
Typical 85W Application Schematic
S3KB-TP
D1
S3KB-TP
S3KB-TP
D5
R2
2.2
D6
R9
2.1k
C10
6.8n
4
C20
47n
C9
1u
Vin*C
I*= 4*BO*BO
CEQ OTP
Gen
PWM
C SKIP OPL
+
-
C13
220p
R10
3.3M
GATE 14
VCC
GND 2
OVP 7
GND
2.5V
VIN
SKIP
BO
6
R13
5.76k
I* gm
10
5
R6
3.3M
U1
VREG Lin.Reg. VCC
UVLO LOGIC
ICOMP
3 ISENI MIRROR
2:1
TP10
DZ1
3.3V
VCC
12
R14
5.36k
11
R8
470k R11
470k
C11
470p
C8
220n
C14
470n
FB 9
gm
COMP
ISL6731A
69.8K
R22
R18
68k
C18
2.2u
C16
1n
C15
100n
R19
42.2k
P6
P7
ISL6731A, ISL6731B
D8 D7
S1M S1M
P3
R4
51k
R28
0.22
S3KB-TP
S3KB-TP
C7
1u
390V
2
R3
2M
C1
56u
450V
1
3
4
CMT1
L4
P2
1
Q1
C3
330n
1
AC2
TP9
IPP60R600C6
C2
100n
P4
R1
2M
1
13
6
UNIVERSAL INPUT
90~265Vac
VOUT
DC+
D2
8
F1 3.15A
1
2
AC1
3
P1
C3D04060E
3
2.2m L2
D4
D3
2
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Application Schematics
FN8582.1
February 13, 2015
ISL6731A, ISL6731B
Absolute Maximum Ratings
Thermal Information
VCC to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +28V
GATE to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +18V
VIN, BO, ISEN, FB, OVP, ICOMP, SKIP, VREG and
COMP to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.3V
ESD Rating
Human Body Model (Tested per JESD22-A114) . . . . . . . . . . . . . . .2.5kV
Machine Model (Tested per JESD22-A115). . . . . . . . . . . . . . . . . . . . 200V
Charged Device Model (Tested per JESD-C101E) . . . . . . . . . . . . . . . . 1kV
Latch-Up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
SOIC Package (Notes 4, 5) . . . . . . . . . . . . .
77
38
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
VCC to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V to + 20V
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. For JC, the “case temp” location is taken at the package top center.
Electrical Specifications
-40°C to +125°C.
PARAMETER
Operating Conditions: VCC = 15V, TA = +25°C. Boldface limits apply across the operating temperature range,
SYMBOL
TEST CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8)
UNITS
VCC SUPPLY CURRENT
Start-Up Current
ISTART
VFB = 1V, VCC < VCC(ON)
73
106
139
µA
Standby Current
ISTDN
VFB = GND, VCC > VCC (ON)
179
237
295
µA
VFB = 2.5V, COMP = SKIP*0.25 +1V
580
690
850
µA
GATE is floating
3.0
3.7
4.5
mA
Skip Mode Current
ICCSKIP
Operating Current (Note 6)
ICC
VCC UVLO
UVLO Rising Threshold
VCC(ON)
9
10
11
V
UVLO Falling Threshold
VCC(OFF)
6.7
7.5
8.3
V
UVLO Threshold Hysteresis
VCC(HYS)
2.5
V
REGULATOR VOLTAGE VREG
Overall Accuracy
VREG
IREG = 0 to -10mA, VCC = 15V, load capacitor = 47nF
5.1
5.4
5.6
V
30
50
70
mA
fSW = 124kHz for ISL6731A and
fSW = 62kHz for ISL6731B
94.8
96.5
Free Running Frequency, ISL6731A
TA = -40°C to +125°C, VIN = 0.6V
95.5
107
117
kHz
Free Running Frequency, ISL6731A
TA = -40°C to +125°C, VIN = 2.5V
111
125
138
kHz
Free Running Frequency, ISL6731B
TA = -40°C to +125°C, VIN = 0.6V
43.5
54
63.7
kHz
Free Running Frequency, ISL6731B
TA = -40°C to +125°C, VIN = 2.5V
56.5
64
70.7
kHz
1.33
1.46
1.59
V
Current Limit
PWM CONVERTERS
Maximum Duty Cycle
%
OSCILLATOR
PWM Ramp Amplitude
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7
FN8582.1
February 13, 2015
ISL6731A, ISL6731B
Electrical Specifications
-40°C to +125°C. (Continued)
PARAMETER
Operating Conditions: VCC = 15V, TA = +25°C. Boldface limits apply across the operating temperature range,
SYMBOL
TEST CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8)
UNITS
2.33
4.46
Ω
0.3
0.45
V
GATE DRIVER
Gate Drive Pull-Down Resistance
VCC = 15V, IGATE = 15mA
Gate Drive Pull-Up Voltage Drop
VCC = 9V, IGATE = 15mA
0.15
Gate Drive Max. Sourcing/Sinking
Current
1.5
A
Rise Time
CO = 2.2nF, VCC = 15V, gate voltage rise time from 10% to
90% of VGC
34
62
ns
Fall Time
CO = 2.2nF, VCC = 15V, gate voltage fall time from 10% to
90% of VGC
34
57
ns
Gate Clamp Voltage
VGC
10.5
12
13.5
V
VREF
2.48
2.5
2.52
V
VOLTAGE REFERENCE
Reference Voltage
Feedback Pin Pull-Down Current
IFB
65
nA
Rising Threshold to Enable Converter
FB_EN
280
300
320
mV
Falling Threshold to Disable Converter
FB_DIS
190
202
214
mV
Enable Hysteresis
FB_Hys
100
mV
VOLTAGE ERROR AMPLIFIER
Error Amp Transconductance
Gmv
50
ISource/Sink
77
104
13
µA/V
µA
COMP Offset Voltage
VCOMP_OFF
0.95
1.01
1.07
V
COMP Soft-Start Enable Voltage
VCOMP_EN
0.58
0.64
0.75
V
INPUT VOLTAGE SENSING
VIN Leakage Current
9
nA
MULTIPLIER GAIN
GMUL
COMP = 2.5V, VIN = 1.0V, BO = 1.0V, ISEN = 50µA
0.196
0.25
0.296
V/V
CURRENT ERROR AMPLIFIER
Current DC Gain
AIDC
IICOMP/IISEN
1.6
1.9
2.2
A/A
Error Amp Transconductance
Gmi
IICOMP = ±20µA
205
268
331
µA/V
ICOMP Source/Sink Current (Note 7)
60
Current Sensing Input Offset
µA
-3
2
7
mV
-23
-20
-17
µA
LIGHT LOAD EFFICIENCY ENHANCEMENT AND OVERPOWER PROTECTION
Skip Current Reference (Note 7)
ISKIP
VSKIP = 2V
Skip Falling Threshold
VSKIP_THf
450
498
550
mV
Skip Rasing Threshold
VSKIP_THr
570
616
690
mV
COMP Upper Limit
VCUL
3.53
3.85
4.17
V
COMP Valid Range
VCUL-1V
2.5
2.83
3.16
V
FB Exit Threshold Voltage
VFB_EXIT
Fraction of VREF, IISEN = 0µA
87
88
89
%
ISEN Exit Threshold Current
ISEN_EXIT
VFB = 2.5V
-38
-29
-20
µA
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FN8582.1
February 13, 2015
ISL6731A, ISL6731B
Electrical Specifications
-40°C to +125°C. (Continued)
PARAMETER
Operating Conditions: VCC = 15V, TA = +25°C. Boldface limits apply across the operating temperature range,
SYMBOL
TEST CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8)
UNITS
BROWNOUT DETECTION
Brownout Rising Threshold
VBO_R
478
494
510
mV
Brownout Falling Threshold
VBO_F
387
401
415
mV
OVERVOLTAGE PROTECTION
Overvoltage Protection, FB pin
VRO1
Fraction of VREF; ~1µs noise filter
103
104.1
106
%
Overvoltage Protection, OVP pin
VRO2
Fraction of VREF; ~1µs noise filter
103
104.2
106
%
-197
-177
-159
µA
OVERCURRENT PROTECTION
Overcurrent Threshold
IOC
THERMAL SHUTDOWN
Shutdown Temperature (Note 7)
160
°C
Thermal Shutdown Hysteresis (Note 7)
25
°C
NOTES:
6. This is the VCC current consumed when the device is active but not switching. Does not include gate drive current.
7. Limits should be considered typical and are not production tested.
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified.
100.50
101.0
100.25
100.5
FSW NORMALIZED (%)
VFB NORMALIZED (%)
Typical Performance Curves
100.00
99.75
VIN = 2.5V
100.0
99.5
VIN = 0.6V
99.50
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
FIGURE 3. FEEDBACK ACCURACY
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9
100
120
140
99.0
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
140
FIGURE 4. FSW vs TEMPERATURE, VCC = 15V
FN8582.1
February 13, 2015
ISL6731A, ISL6731B
Typical Performance Curves
(Continued)
105
101
FSW NORMALIZED (%)
AIDC NORMALIZED (%)
100
100
99
98
95
90
85
80
97
-40
-20
0
20
40
60
80
100
120
75
140
0
0.5
1.0
1.5
2.0
2.5
3.0
VIN (V)
TEMPERATURE (°C)
FIGURE 5. AIDC vs TEMPERATURE
FIGURE 6. FSW vs VIN, TA = +25°C
VCC CURRENT NORMALIZED (%)
UVLO THRESHOLD NORMALIZED (%)
102
101
HYSTERESIS
100
UP
THRESHOLD
99
DOWN
THRESHOLD
98
-40
-20
0
20
40
60
80
100
120
102
101
100
ICC
(GATE FLOATING)
99
98
-40
140
ISTART
-20
0
20
TEMPERATURE (°C)
40
60
80
100
120
140
TEMPERATURE (°C)
FIGURE 7. UVLO THRESHOLDS vs TEMPERATURE
FIGURE 8. VCC SUPPLY CURRENT vs TEMPERATURE
GATE DRIVE TIMING NORMALIZED (%)
112
110
108
FALL TIME
106
104
102
RISE TIME
100
98
96
-40
-20
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
FIGURE 9. GATE DRIVE TIMING vs TEMPERATURE (LOAD = 2.2nF)
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FN8582.1
February 13, 2015
ISL6731A, ISL6731B
Functional Description
VCC Undervoltage Lockout (UVLO)
The ISL6731A and ISL6731B start automatically once the
voltage at VCC exceeds the UVLO threshold.
Shutdown
When the VFB pin is below 0.2V, the controller is disabled and
the PWM output driver is tri-stated. When disabled, the IC power
will be reduced. During shutdown, the COMP pin is discharged to
GND and the controller is disabled. The Over-Temperature
Protection (OTP) is still alive to prevent the controller from
starting up in a high temperature ambient condition.
In the event that the FB pin is disconnected from the feedback
resistors, the FB pin is pulled to ground by an internal current
source IFB. When the FB pin voltage drops below 0.2V, the gate
driver is disabled. The ISL6731A or ISL6731B enters shutdown
mode.
Soft-Start
The COMP pin is released once the soft-start operation begins. A
13µA current sources out to the RC network connected from the
COMP pin until the FB pin voltage reaches 90% of the reference
voltage.
Switching is inhibited when the COMP pin voltage is below 1V.
When the COMP pin reaches 1V, the current error amplifier and
the gate driver are activated and the converter starts switching.
During UVLO, brownout and shutdown, the COMP is pulled to the
ground.
Input Voltage Sensing
The VIN pin is needed to sense the rectified input voltage. The
sensed semi-sinusoidal waveform is needed to shape the
inductor current, which helps achieves unity power factor. At the
same time, the voltage on the VIN pin is used to generate the
negative capacitive element at the input. This will cancel the
input filter capacitor, CF. Canceling the effect of CF will increase
the displacement power factor and alleviate the zero crossing
distortion, which is related to the distortion power factor.
The BO pin also utilizes the VIN resistor divider for voltage
sensing. Set the resistor divider ratio to satisfy the brownout
requirement.
First, calculate the resistor divider ratio, KBO.
V BORMAX
K BO = ------------------------------------------V RMSmin – 2V F
(EQ. 1)
Where VF is the forward voltage drop of the bridge rectifier and
the voltage drop of DF1; DF2.
Then, select the RIN2 based on the highest reasonable resistance
value. Then select the RIN1 based upon the desirable minimum
RMS value of the line voltage for the PFC operation.
K BO
R IN1 = ---------------------  R IN2
1 – K BO
(EQ. 2)
Inductor Current Sensing
The current sensing of the converter has two purposes. One is to
force the inductor current to track the input semi-sinusoidal
waveform. The other purpose is for overcurrent protection. Refer to
Figure 11 for the current sensing scheme. The sensed current ICS
is in proportion to the inductor current, IL as described in
Equation 3:
1 R CS
I CS = ---  ----------------  I L
2 R SEN
(EQ. 3)
where:
RCS is the current sensing resistor with low value in the return
path to the bridge rectifier.
RSEN is the current scaling resistor connected between ISEN to
the RCS.
VI
VOUT
L
Q1
RCS
CURRENT
MIRROR
EMI CHOKE
RSEN
VLINE
CF3
2:1
I CS
CF2
Lm
ISEN
I CS > 0.5 I OC
DF1
DF2
FIGURE 11. INDUCTOR CURRENT SENSING SCHEME
RIN2
A high value RCS renders more accurate current sensing. It is
recommended to use the RCS to render 120mV peak voltage at
the maximum line voltage during full load condition.
VIN
BO
RIN1
COUT
CF1
CBO
120mV  V RMSMAX  
R CS  ------------------------------------------------------------2  P Omax
FIGURE 10. INPUT VOLTAGE SENSING SCHEMATIC
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11
(EQ. 4)
Where is the efficiency of the converter at the maximum line
input with full load.
FN8582.1
February 13, 2015
ISL6731A, ISL6731B
Since the RCS sees the average input current, high value RCS
generates high power dissipation on the RCS. Use a reasonable
RCS according to the resistor power rating. The worst-case power
dissipation occurs at the input low line when input current is at
its maximum. Power dissipation by the resistor is:
(EQ. 5)
P RCS =  I RMSMAX  2  R CS
IRMSMAX is the maximum input RMS current at the minimum
input line voltage, VRMSmin.
Select the RSEN according to the peak current limit requirement.
The resistor is sized for an overload current 25% more than the
peak inductor peak current.
Negative Input Capacitor Generation
The patent pending negative capacitor generation capability of
ISL6731A and ISL6731B allow the capacitor CF2 to be moved
from before the bridge rectifier (Figure 12) to after the bridge
rectifier (Figure 13). Thus, a smaller, lower cost CF2 can be used.
The change in topology reduces the size of the EMI filter.
Furthermore, CF1 can be increased thus decreasing the size of LF
(Figure 13).
LF
CF3
BRIDGE RECFIFIER
CF1
CF2
The ISL6731A and ISL6731B can further reduce EMI filter size by
lowering the differential noise power density. The reduction is
achieved by switching frequency modulation.
The frequency varies with the VIN pin. The switching frequency
reaches the peak value when the VIN pin voltage is 2V as shown
in Figure 6. The peak value of ISL6731A is 124kHz, and the
ISL6731B is 62kHz.
Output Voltage Regulation
(Patent Pending)
VLINE
Adjusting the negative CEQ can be achieved by adjusting the
current compensation network.
Frequency Modulation
where:
EMI CHOKE
The equivalent negative capacitor is a function of the input
voltage divider ratio, KBO, the current sensing gain and current
compensation error integration gain.
The output voltage is sensed through a resistor divider. The
middle point of the resistor divider is fed to the FB pin. The
resistor divider ratio sets the output voltage. The
transconductance error amplifier generates a current in
proportion to the difference between the FB pin and the 2.5V
internal reference. The PFC is stabilized by the compensation
network that is connected from the COMP pin to the ground.
The voltage of the COMP sets the input average power by
determining the amplitude of the current reference. To keep the
harmonic distortion to a minimum, it is desirable to set the
control bandwidth much lower than twice of the line frequency.
The recommended voltage loop bandwidth is 10Hz.
During start-up, the compensation capacitors and the charging
current from the error amplifier sets the input power increase
rate. Thus, soft-start is achieved.
Lm
FIGURE 12. TYPICAL PFC INPUT FILTER CIRCUIT
The COMP is discharged during shutdown and fault conditions.
BRIDGE RECFIFIER
EMI CHOKE
VLINE
CF3
Light Load Efficiency Enhancement
LF
CF2
CF1
Lm
FIGURE 13. LOW COST PFC INPUT FILTER CIRCUIT
For applications where the output power is above 500W, the
negative capacitance helps to improve the power factor
dramatically. Refer to Table 2 for the recommended filtering
capacitor to be placed after the bridge rectifier, CF1.
TABLE 2. RECOMMENDED FILTERING CAPACITOR
CF1
PO < 100W
Typical
C(µF)/100W
0.68
100W < PO < 500W PO > 500W
0.33
0.22
For PC, adaptor and TV applications, it is desirable to achieve
high efficiency at light load conditions and low standby current.
The ISL6731A and ISL6731B can enter light load skip mode
automatically. The skip mode trigger threshold is adjustable by
the SKIP pin. A 20µA current source out of the SKIP pin sets the
voltage on the pin via a resistor connected between the pin and
ground. Connecting this pin to ground disables the light load skip
function.
The voltage error amplifier output, COMP, is an indicator of the
average input power level. The controller compares the V(COMP)
and V(SKIP). If V(COMP)-1V is less than V(SKIP)*0.25, the PFC
controller stops gate switching and the COMP pin voltage is
clamped to V(SKIP)+0.6V.
The controller exits skip mode when VFB drops to 88% (typical) of
the reference voltage or when the sensed returned current
exceeds 29µA.
Additional CF1 may be used to accommodate the use of small
boost inductor or to eliminate the differential mode filter inductor
as long as the equipment meets the power factor or goal.
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FN8582.1
February 13, 2015
ISL6731A, ISL6731B
Protection Circuits
Input Brownout, BO Protection
Brownout occurs when there is a drop in the line voltage. The BO
pin is a dual function pin. The BO pin detects the brownout
condition and shuts down the gate driver and controller. During
normal operation, the BO pin is used to compensate the effect of
the input line voltage change on the voltage loop. To keep the
harmonic distortion low, the corner frequency formed by the RBO
and CBO should be lower than 6Hz.
Figure 14 shows the critical power components; Q1, D and COUT.
To minimize the voltage overshoot, the interconnecting wires
indicated by heavy lines should be part of the ground or the
power plane in a printed circuit board. The components shown in
Figure 14 should be located as close together as possible. Please
note that the capacitors CVCC and CO each represent numerous
physical capacitors. Locate the ISL6731A or ISL6731B within 2
inches of the MOSFET, Q1. The circuit traces for the MOSFETs’
gate and source connections from the ISL6731A and ISL6731B
must be sized to handle up to 1.5A peak current.
D
The BO pin is the output of the average voltage of the rectified
voltage. The PFC controller is turned off when the BO pin drops
below 0.4V. This protects the PFC power stage to enable
operation at or below brownout condition for long periods of
time. The controller resumes operation when the BO pin returns
to 0.5V.
L
The BO pin is usually connected to GND through a capacitor, CBO.
To avoid distortion on the VIN pin, select CBO so that:
GATE
(EQ. 6)
C BO » 0.22F
VCC
Overcurrent Protection
The peak current limit function prevents the inductor from
saturation. The gate driver turns off when the current goes above
the current limit set point.
Overpower Protection
The overpower protection is implemented by limiting the COMP
pin voltage higher than 3.85V (typical).
Overvoltage Protection
If the voltage on the FB pin exceeds the reference voltage VREF by
about 4%, the gate driver is turned off.
If the voltage on the OVP pin exceeds the VREF by about 4.5%, the
gate driver is turned off.
The controller resumes normal operation after both OVP and FB
pin drops below VREF.
Over-Temperature Protection
The ISL6731A and ISL6731B are protected against
over-temperature conditions. When the junction temperature
exceeds +160°C, the PWM shuts down. Normal operation is
resumed when the junction temperature decreases below +135°C.
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using wide,
short printed circuit traces. The critical components should be
located as close together as possible using ground plane
construction or single point grounding.
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COUT
Q1
13
CVCC
FIGURE 14. CRITICAL CURRENT POWER COMPONENTS
Component Selection Guidelines
A 300W, universal input, PFC converter design is provided for
demonstration. The design method is for a continuous current
mode power factor correction boost converter with the
ISL6731B. The switching frequency is 62kHz.
Tables 3 shows the design parameters.
TABLE 3. CONVERTER DESIGN PARAMETERS
PARAMETER
CONDITIONS
MIN
TYP
MAX UNIT
VLINE
90
115/230 265
VAC
FLINE
47
63
Hz
300
W
POMAX
Maximum Output Power
THOLD
Hold Up Time
Efficiency
VLINE = 115VAC
20
ms
92
%
BOOST INDUCTOR SELECTION
First, calculate the maximum input RMS current, IINMAX.
P OMAX
I INMAX = ----------------------------------  V RMSmin
(EQ. 7)
Where is the converter efficiency at VRMSmin. PF is the power
factor at VRMSmin.
300W
I INMAX = ---------------------------- = 3.62A
0.92  90V
(EQ. 8)
Assuming the current is sinusoidal and the peak-to-peak ripple at
line is 40%.
FN8582.1
February 13, 2015
ISL6731A, ISL6731B
The forward power loss on the diode is:
The boost inductor, LBST, is given in Equations 9 and 10:
2  V RMSmin
2V RMSmin

L BST  ----------------------------------------------------------------   1 – ---------------------------------------
V OUT
0.4  F sw  2  I INMAX 

90V
2  90V
L BST  ------------------------------------------------------   1 – ------------------------ = 654H
0.4  64kHz  3.62 A 
390V 
(EQ. 9)
(EQ. 20)
P FD = 0.77A  0.9V = 0.692W
(EQ. 21)
The CREE C3D10060A SiC Schottky diode is selected.
(EQ. 10)
Choose inductance of 1.5mH, consider the µr will decrease at high
current for a powder core inductor. The peak current of the
inductor is the sum of the average peak inductor current and half
of the peak-to-peak ripple current. Select and design the boost
inductor as given by Equation 11. The ISL6731A and ISL6731B
provides peak current limit function that can prevent the boost
inductor saturation. Assuming 25% margin is given to the OCP
threshold, select and design the boost inductor with saturation
current given by Equation 11 with 25% margin.
I LPeak =
I
2  I INMAX   1 + -----

2
(EQ. 11)
I LPeak =
1.786A
2  3.88A   1 + ------------------- = 6.017A

2 
(EQ. 12)
INPUT RECTIFIER
The reverse recovery loss on the diode can be calculated. The
QRR is found from the diode datasheet. QRR = 25nC.
The reverse recover loss on the diode can be estimated:
1
P RRD = ---  Q
 V OUT  F
4
RR
sw
(EQ. 22)
1
P RRD = ---  25nC  390V  62kHz = 0.156W
4
(EQ. 23)
The total power loss on the diode is:
(EQ. 24)
P D = P FD + P RRD =  0.692 + 0.156 W = 0.848W
MOSFET POWER DISSIPATION
The power dissipation on the MOSFET is from two different types
of losses; the conduction loss and the switching loss.
For the MOSFET, the worst case is at minimum line input voltage.
The maximum average input current is calculated:
2  2  I INMAX
I INAVE  max  = -----------------------------------------
P FD = I OUT  max   V F
First, the drain-to-source RMS current is calculated:
(EQ. 13)
8 2 V RMSmin
I DS  max  = I INMAX 1 – -----------  -------------------------V
3
(EQ. 25)
8 2 90V
I DS  max  = 3.623A 1 – -----------  -------------- = 3.081A
3 390V
(EQ. 26)
OUT
2  2  3.62A
I INAVE  max  = -------------------------------------- = 3.3A

(EQ. 14)
Select the bridge diode using Equation 15 and sufficient reverse
breakdown voltage. Assuming the forward voltage, VF,BR, is 1V
across each rectifier diode. The power loss of the rectifier bridge
can be calculated:
P BR = 2  V F BR  I INAVE  MAX 
(EQ. 15)
P BR = 2  1V  3.3A = 6.524W
(EQ. 16)
(EQ. 27)
2
P COND = I DS  max   r DS  on 
2
(EQ. 28)
P COND = 3.3A  0.285 = 2.71W
The switching loss of the MOSFET consists of three parts: the
turn-on loss, the turn-off loss and the diode reverse recovery loss.
INPUT CAPACITOR SELECTION
Refer to Table 2 for the recommended input filter capacitor value.
0.33
C F1 = 300W  ----------- = 0.99F
100
The MOSFET, SPP20N60C3 is selected.
(EQ. 17)
From the MOSFET datasheet, the typical switching losses curves
are provided.
When RG = 3.6Ω, ID = 6A, EON = 0.013mJ, EOFF = 0.020mJ.
This is the recommended capacitor used after the diode bridge.
For better power factor, less capacitance can be used. To lower
the input filter inductor size, more capacitance can be used.
The switching loss due to transition is calculated:
P SW =  E ON + E OFF   F
sw
(EQ. 29)
One 0.68µF capacitors is used for CF1.
P SW =  0.013mJ + 0.020mJ   64kHz = 2.09W
(EQ. 30)
BOOST DIODE SELECTION
The boost diode loss is determined by the diode forward voltage
drop, VF and the output average current. The maximum output
current is:
The loss caused by COSS can be estimated as:
2
2
P OSS = --- C oss  V OUT  F
3
sw
(EQ. 31)
P OMAX
I OUT  max  = -------------------V OUT
(EQ. 18)
From the MOSFET datasheet, the COSS = 197pF when
VOUT = 390V.
300W
I OUT  max  = ---------------- = 0.77A
390V
(EQ. 19)
2
2
P OSS = --- 197pF  390V  64kHz = 1.28W
3
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14
(EQ. 32)
FN8582.1
February 13, 2015
ISL6731A, ISL6731B
THE TOTAL LOSS ON THE MOSFET
P COND + P SW + P
OSS
= 2.71W + 2.09W + 1.28W = 6.08W (EQ. 33)
OUTPUT CAPACITOR SELECTION
The output capacitor, CO, is required to hold the output above
300V during one line cycle. For capacitors with 20% tolerance,
the tolerance should be taken into consideration. Thus, the
output capacitance should be greater than:
2  T HOLD  P
1
OMAX
C O  ----------------------------------------------------  ----------------1 – 0.2
V2
– V2
OUT
(EQ. 34)
HOLD
2  20ms  300W
C O  ----------------------------------------------  1.25 = 242F
2
 390  –  300V  2
(EQ. 35)
V OUT
8 2
I CORMS  max  = I OUT  max  -----------  -------------------------- – 1
3 V RMSmin
(EQ. 36)
8 2 390V
I CORMS  max  = 0.77A -----------  -------------- – 1 = 1.577A
3
90V
(EQ. 37)
(EQ. 42)
2
(EQ. 43)
P RCSMAX = 3.623A  0.073 = 0.963W
The resistor, RSEN sets the overcurrent protection limit. From
Equation 3, RSEN should be greater than:
R CS  I LPeak   1 + 0.2 
R SEN  ----------------------------------------------------------------2  0.5 I OC
(EQ. 44)
Where |x| stands for the ABS(x) function, IOC is the overcurrent
threshold.
It is important to make sure the output peak-to-peak ripple is
less than the minimum OVP threshold as specified in the table
on “Electrical Specifications” on page 7. The ESR of the capacitor
at 2 times of line frequency is found in the capacitor datasheet.
The ESR is 737mΩ at 100Hz.
2
(EQ. 38)
O
Select RSEN from available standard value resistors, the selected
RSEN is 3kΩ
The input current shaping is achieved by comparing the sensed
current signal to the sensed input voltage signal. The current error
amplifier (Gmi), together with the current compensation network,
adjusts the duty cycle so that the inductor current traces the
sensed rectified voltage. Thus, unity power factor is achieved.
The compensation network consists of the Trans-Conductance
error amplifier (Gmi) and the impedance network (ZICOMP). The
goal of the compensation network is to provide a closed loop
transfer function with the sufficient 0dB crossing frequency
(f0dB) and adequate phase margin. Phase margin is the
difference between the open loop phase at f0dB and 180°. The
following equations relate the compensation network’s poles,
zeros and gain to the components (Ric, Cic and Cip) in Figure 15.
VI
2
 4  50Hz  270F  0.77  + 1
V Opp = 0.77A  -------------------------------------------------------------------------------------------- = 9.6V
 2  50Hz   270F  0.8
VOUT
L
Q1
(EQ. 39)
COUT
CF1
The minimum OVP threshold is 103% of the nominal output
value. The maximum output peak-to-peak ripple should be less
than 6% of the nominal value, which is 23.4VP-P.
RCS
CURRENT
MIRROR
CURRENT SENSING RESISTORS
(EQ. 41)
R CS = 0.073
I
CS
ISEN
(EQ. 40)
While a large RCS renders better current sensing accuracy, larger
RCS also incurs higher power dissipation. Select three 0.22Ω
resistors in parallel as RCS.
2:1
RSEN
Please refer to Equation 4 for calculation of the current sensing
resistor RCS.
120mV  265V  0.92
R CS  ------------------------------------------------------- = 0.069
2  300W
(EQ. 45)
CURRENT LOOP COMPENSATION
Select the proper capacitor according to the hold time and ripple
RMS current requirement. The actual capacitance is 270µF.
line
2
P RCSMAX = I INMAX  R CS
0.073  6.017A  1.2
R SEN  ----------------------------------------------------------- = 2.9k
2  90A
Calculate the ripple RMS current through the capacitor:
 4f line  C O  ESR  + 1
V Opp = I OUT  max   ---------------------------------------------------------------------- 2f
  C  0.8
The maximum power dissipation on the RCS occurs at low line and
full load condition. The maximum power dissipation is calculated:
ICOMP
Gmi
Ric
Cic
IREF
RIS
Cip
FIGURE 15. INDUCTOR CURRENT SENSING SCHEME
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FN8582.1
February 13, 2015
ISL6731A, ISL6731B
120
FZ
100
Thus, the current loop compensation zero is:
GILOOP (s)
80
GAIN (dB)
Where M is the phase margin, which is 20°. FP = 6kHz. This is
an aggressive example to fulfill a tight THD for light load.
FP
14kHz
F Z = ---------------------------------------------------------------------------- = 0.78kHz
14kHz


tan atan ------------------ + 20deg
 6kHz 


Gid (s)
60
Gci (s)
40
The total compensation capacitance is calculated:
FC
20
2

A IDC R CS 
V OUT
1 +  fc  fz  
C ip + C ic =   ---------------------------------------  --------------  ----------------  ------------------------------ (EQ. 54)

2 V
2
R SEN
+


f

1
f
m
L


2f

c p 
 BST
c
0
Gsm
-20
-40
(EQ. 53)
10
100
1k
10k
100k
FREQUENCY (Hz)
FIGURE 16. ASYMPTOTIC BODE PLOT FOR CURRENT LOOP GAIN
1
F Z = -----------------------------------2  R ic  C
(EQ. 46)
ic
C ip + C ic = 7.345nF
(EQ. 55)
fz
C ip =  C ip + C iC  ---fp
(EQ. 56)
The value of the noise filtering capacitor is:
0.78kHz
C ip = 7.345nF  ----------------------- = 0.958nF
6Hz
1
F P = --------------------------------------------------C ip  C
ic
2  R ic  -----------------------C ip + C ic
(EQ. 47)
(EQ. 57)
The value of Cic is:
(EQ. 58)
C ic = 7.345nF – 0.958nF = 6.378nF
Use the following guidelines for locating the poles and zeros of
the compensation network.
Near the crossover frequency, the transfer function from duty
cycle to inductor current is well approximated by Equation 48:
V OUT
G id  s  = ---------------------L BST  s
(EQ. 48)
The value of Ric is:
1
R ic = -------------------------------------------------------------- = 31.85k
2  0.78kHz  6.378nF
Select the RC value from the standard value, we have:
Ric = 30kΩ, Cic = 6.8nF, Cip = 1nF. Figure 17 shows the actual
bode plot of current loop gain.
The compensation gain uses external impedance networks as
shown in Figure 15, Gci(s) is given by:
(EQ. 49)
100
GAIN (dB)
s
---------------------- + 1
2    FZ
1
G ci  s  = Gmi ------------------------------------  --------------------------------s
 C ic + C ip   s
----------------------- + 1
2    FP
(EQ. 59)
FZ
FP
FZ
FP
50
0
The current gain and modulation gain Gsm is:
(EQ. 50)
where Vm is the amplitude of the PWM carrier. The open loop
gain of the current loop is:
G ILOOP  s  = G id  s   G sm  G ci  s 
(EQ. 51)
It is recommended to set the crossover frequency, FC from 1/10
to 1/6 of the switching frequency with a phase margin of 60°. A
high frequency pole, FP, is set at 1/2 of the switching frequency
for ripple filtering. In this example, we set the FC at 14kHz.
FC
F Z = -------------------------------------------------------

 F C
tan  atan  ------- +  M
F


 P
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90
PHASE (°)
Rcs Ris 1
Gsm = ---------------  --------- --------Rsen 2 Vm
60
60
45
30
0
10
100
1k
10k
100k
FREQUENCY (Hz)
FIGURE 17. BODE PLOT OF THE ACTUAL CURRENT LOOP GAIN
(EQ. 52)
16
FN8582.1
February 13, 2015
ISL6731A, ISL6731B
INPUT VOLTAGE SETTING
With the equivalent negative capacitor, the total reactive current
reduces to:
First, set the BO resistor divider gain, KBO according to
Equations 1 and 2.
Assuming the converter starts at VLINE = 80VRMS, then the BO
resistor divider gain, KBO, should be:
(EQ. 60)
0.5V
K BO = ------------------------ = 0.00641
80V – 2V
In this design, two 470kΩ resistors in series are used for RIN2.
Therefore, RIN1 is calculated:
0.00641
R IN1 = -------------------------------   0.94M  = 6.065k
1 – 0.00641
(EQ. 61)
The displacement power factor increases to:
Ia
PF DIS = -------------------------------------------------------- = 0.9958
2
2
 I a  +  I c – I cneg 
(EQ. 70)
VOLTAGE LOOP COMPENSATION
The average boost diode forward current can be approximated by:
P in
I D  ave  = ---------------V OUT
We choose RIN1 = 5.76kΩ, the actual KBO is calculated:
R IN1
K BO = --------------------------------- = 0.00609
R IN1 + R IN2
(EQ. 69)
I c – I cneg = 0.126A
(EQ. 62)
NEGATIVE INPUT CAPACITOR GENERATION
The ISL6731A and ISL6731B generate an equivalent negative
capacitance at the input to cancel the input filter capacitance.
Thus, more input capacitors can be used without reducing the
power factor.
The input equivalent negative capacitance is a function of the
current sensing gain, BO resistor divider gain and the
compensation components.
V m  R SEN

C NEG =  K BO  0.8 – ---------------- --------------------------  C ic + C ip 
V

OUT R CS A iDC
(EQ. 71)
Assuming the input current traces the input voltage perfectly. The
input power is in proportion to (VCOMP - 1V).


R SEN
1
0.25
I D  ave  = ---------------------------------------  ----------------   ------------------------------------------------   COMP

2
R CS  0.5  R IS V OUT 
   2 2      K BO
(EQ. 72)
Where COMP is the VCOMP - 1V. 1V is the offset voltage.
RIS is the internal current scaling resistor. RIS = 14.2kΩ.
A
I D  ave  = 0.749 ----   COMP
V
(EQ. 73)
(EQ. 63)
VOUT
2.5V
1.5
3k
C NEG =  0.00609  0.8 – ---------- ---------------------------  6.8nF + 1nF  = 0.17F

390 0.073  1.9
(EQ. 64)
FB
This equivalent negative capacitor cancels the input filter
capacitor required for EMI filtering. Therefore, the displacement
power factor significantly improves.
For example, CF1 = 0.68µF, CF2 = CF3 = 0.47µF, using the low
cost EMI filter shown in Figure 13. When VLINE = 230VAC,
fLINE = 50Hz, PO = 300W.
Assuming 95% efficiency under the above test condition, the
resistive component of the line current, which is in phase to voltage:
Po
I a = --------------------------------- = 1.373A
V LINE  0.95
RFB2
Gmv
IFB
RFB1
COMP
Rvc
Cvp
Cvc
(EQ. 65)
FIGURE 18. OUTPUT VOLTAGE SENSING AND COMPENSATION
The reactive current through the input capacitors:
I c = V LINE   2  f LINE    C F1 + C F2 + C F3  = 0.14A
(EQ. 66)
Thus, the transfer function from VCOMP to VOUT is:
I D  ave 
V OUT  s 
1
G PS  s  = ------------------------ = ----------------  ------------------- COMP
C O  s  COMP
(EQ. 74)
Thus, the displacement power factor is:
Ia
PF DIS = ----------------------------------- = 0.9948
2
2
 Ia  +  Ic 
(EQ. 67)
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17
(EQ. 75)
As shown in Figure 18, the voltage loop gain is:
The reactive current generated by the equivalent negative
capacitor is:
I cneg = V LINE   2  f LINE    C NEG  = 0.015A
 I D  ave 
1 
0.749
G PS  s  =  -------------------  -------------------- = ---------------CO  s
 C O  s  COMP
G VLOOP  s  = G PS  s   G DIV  Gmv  Z COMP  s 
(EQ. 76)
(EQ. 68)
FN8582.1
February 13, 2015
ISL6731A, ISL6731B
The output feedback resistor divider gain, GDIV is:
V REF
G DIV = ---------------V OUT
(EQ. 77)
Choose components from the standard values. We have
CVP = 150nF, CVC = 1µF, RVC = 62kΩ. The actual bode plot is
shown in Figure 20.
40
R vc  C vc  s + 1
1
Z COMP  s  = ---------------------------------------  ------------------------------------------------------------ C vc + C vp   s R vc  C vc  C vp
------------------------------------------  s + 1
C vc + C vp
(EQ. 78)
GAIN (dB)
The compensation gain uses external impedance networks as
shown in Figure 18, ZCOMP(s) is given by:
The targeted crossover frequency, FCV is 7.5Hz. The high
frequency pole, FPV, is required in order to reject the 2 time line
frequency component. FPV = 20Hz. The targeted phase margin
is 50°.
FZV
FPV
GmV*ZCOMP (s)
40
Gps (s)
FCV
GAIN (dB)
20
0
120Hz
20
0
0
-20
90
PHASE (°)
60
FCV
FCV
120Hz
60
60
45
30
0
1
10
100
1k
FREQUENCY (Hz)
-20
GVLOOP (s)
FIGURE 20. BODE PLOT OF THE ACTUAL VOLTAGE LOOP GAIN
GDIV
-40
-60
1
100
10
1k
FREQUENCY (Hz)
FIGURE 19. ASYMPTOTIC BODE PLOT OF VOLTAGE LOOP GAIN
The zero, FZv is calculated:
F CV
F Zv = ------------------------------------------------------------------------------tan   m + atan  F CV   F PV   
(EQ. 79)
7.5Hz
F Zv = ----------------------------------------------------------------------------------------------------- = 2.648Hz
tan  50deg + atan   7.5Hz    20Hz   
(EQ. 80)
Then the total capacitance used for compensation is calculated:
2
G PS  i   2F CV    G DIV  Gmv
 F CV  F ZV  + 1
C vc + C vp = -------------------------------------------------------------------------------------------  ------------------------------------------2
 2F CV 
 F CV  F PV  + 1
(EQ. 81)
Thus, the total compensation capacitance is:
(EQ. 82)
C vc + C vp = 1127nF
F ZV
C vp = 1127nF  ----------- = 149nF
F PV
(EQ. 83)
C vc = 1127nF – 149.1nF = 977nF
(EQ. 84)
1
R vc = ------------------------------------------- = 61.5k
2    F ZV  C VC
(EQ. 85)
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FN8582.1
February 13, 2015
ISL6731A, ISL6731B
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
CHANGE
February 13, 2015
FN8582.1
Recommended operating conditions on page 7: changed VCC to GND value from “15V to +20V ‘to “12V to
+20V’.
Updated Equations 38 and 39 on page 15.
March 25, 2014
FN8582.0
Initial Release
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FN8582.1
February 13, 2015
ISL6731A, ISL6731B
Package Outline Drawing
M14.15
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 1, 10/09
8.65
A 3
4
0.10 C A-B 2X
6
14
DETAIL"A"
8
0.22±0.03
D
6.0
3.9
4
0.10 C D 2X
0.20 C 2X
7
PIN NO.1
ID MARK
5
0.31-0.51
B 3
(0.35) x 45°
4° ± 4°
6
0.25 M C A-B D
TOP VIEW
0.10 C
1.75 MAX
H
1.25 MIN
0.25
GAUGE PLANE C
SEATING PLANE
0.10 C
0.10-0.25
1.27
SIDE VIEW
(1.27)
DETAIL "A"
(0.6)
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSEY14.5m-1994.
3. Datums A and B to be determined at Datum H.
(5.40)
4. Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
5. The pin #1 indentifier may be either a mold or mark feature.
(1.50)
6. Does not include dambar protrusion. Allowable dambar protrusion
shall be 0.10mm total in excess of lead width at maximum condition.
7. Reference to JEDEC MS-012-AB.
TYPICAL RECOMMENDED LAND PATTERN
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FN8582.1
February 13, 2015
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