DATASHEET

HIP2060
TM
60V, 10A Half Bridge Power MOSFET Array
April 1998
Features
Description
• Two 10A Power MOS N-Channel Transistors
The HIP2060 is a power half-bridge MOSFET array that consists of two matched N-Channel enhancement-mode MOS
transistors. The advanced Intersil PASIC2 process technology used in this product utilizes efficient geometries that provides outstanding device performance and ruggedness.
• Output Voltage to 60V
• rDS(ON) . . . . . 0.135Ω Max Per Transistor at VGS = 15V
• rDS(ON) . . . . . . 0.15Ω Max Per Transistor at VGS = 10V
The HIP2060 is designed to integrate two power devices in
one chip thus providing board layout area and heat sink savings for applications such as Motor Controls, Uninterruptable
Power Supplies, Switch Mode Power Supplies, Voice Coil
Motors, and Class D Power Amplifier.
• Pulsed Current . . . . . . . . . . . . . . . .25A Each Transistor
• Avalanche Energy . . . . . . . . . . 100mJ Each Transistor
• Grounded Tab Eliminates Heat Sink Isolation
Ordering Information
PART NUMBER
TEMP.
RANGE (oC)
PACKAGE
Symbol
PKG.
NO.
HIP2060AS1
-40 to 125
5 Ld SIP
Z5.067C
HIP2060AS2
-40 to 125
5 Ld Gullwing SIP
Z5.067A
HIP2060AS3
-40 to 125
5 Ld SIP
Z5.067B
DRAIN1
GATE1
NOTE: When ordering use the entire part number.
5
Z1
D1
1
SOURCE1 = DRAIN2
4
GATE2
Z2
2
SOURCE2
3, TAB
Packages
JEDEC TS-001AA (ALTERNATE VERSION)
HIP2060 AS1
54
3
2
JEDEC MO-169
HIP2060 AS2
1
1 GATE1
2 GATE2
3 SOURCE2
4 SOURCE1-DRAIN2
5 DRAIN1
(TAB)
Z5.067B (SIP)
HIP2060 AS3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1
FN3983.5
HIP2060
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified
HIP2060
60
UNITS
V
Drain-Gate Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR
60
V
Gate-Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
±20
V
Continuous Source-Drain Diode Current (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISD
10
A
Pulsed Drain Current, each Output, all Outputs on (Notes 1, 2) . . . . . . . . . . . . . . . . . . . . . . . IDM
25
A
Continuous Drain-Source Voltage Over Operating Junction and Case Temperature Range . . . . . VDS
Continuous Drain Current, each Output, all Outputs on (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . IDS
10
A
Single Pulse Avalanche Energy (Note 3) Refer to UIS Curve . . . . . . . . . . . . . . . . . . . . . . . . . EAS
100
mJ
Continuous Power Dissipation at TC = 25oC (Infinite Heatsink). . . . . . . . . . . . . . . . . . . . . . . . . PD
46
W
Continuous Power Dissipation, Derate above TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0.37
W/oC
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .θJA
60
oC/W
Operating Case Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TC
-40 to 125
oC
Junction and Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
-40 to 150
oC
Lead Temperature (For Soldering, 10s)(Lead Tips Only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
300
oC
Continuous Drain1-Source2 Voltage Over Operating Junction Temperature Range. . . . . . VD1S2
60
V
NOTES:
1. Pulse width limited by maximum junction temperature.
2. Drain current limited by package construction.
3. VDD = 25V, Start TJ = 25oC, L = 1.5mH, RGS = 50Ω, R = 0. See Figures 2, 12, and 13.
Electrical Specifications
TC = 25oC, Unless Otherwise Specified
PARAMETER
Drain-Source Breakdown Voltage
SYMBOL
BVDSS
TEST CONDITIONS
ID = 100µA, VGS = 0V
TC = -40oC to
125oC
TC = 25oC
MIN
TYP
MAX
UNITS
60
-
-
V
-
70
-
V
1.5
2.3
2.7
V
Gate Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA
Drain1-Source2 Breakdown Voltage
(Across D1)
BVD1S2
ID1S2 = 1µA,
VG1S1, VG2S2 = 0V
TC = 25oC
-
105
-
V
Zero Gate Voltage Drain Current
IDSS
VDS = 60V
VGS = 0V
TC = 25oC
-
-
1
µA
Drain1-Source2 Current (Through D1)
ID1S2
VD1S2 = 60V
VG1S1 = 0V, VG2S2 = 0V
TC = 25oC
-
0.3
1
µA
TC = 125oC
-
1
-
µA
ID = 10A, VGS = 15V
-
0.9
1.25
V
ID = 10A, VGS = 10V
-
1.1
1.5
V
Drain-Source On-State Voltage
(Note 4)
VDS(ON)
Forward Gate Current, Drain Short
Circuited to Source
IGSSF
VDS = 0V, VGS = 20V
-
-
100
nA
Reverse Gate Current, Drain Short
Circuited to Source
IGSSR
VDS = 0V, VGS = -20V
-
-
-100
nA
Drain-Source On Resistance (Note 4)
Forward Transconductance (Note 4)
rDS(ON)
gfs
VGS = 15V, ID = 10A
TC = 25oC
-
0.09
0.135
Ω
VGS = 15V, ID = 10A
TC = 125oC
-
0.15
0.21
Ω
VGS = 10V, ID = 10A
TC = 25oC
-
0.11
0.15
Ω
VGS = 10V, ID = 10A
TC = 125oC
-
0.19
0.25
Ω
-
4.5
-
S
VDS = 15V, ID = 5A
2
HIP2060
Electrical Specifications
TC = 25oC, Unless Otherwise Specified (Continued)
PARAMETER
Turn-On Delay Time (Note 5)
SYMBOL
MIN
TYP
MAX
UNITS
-
4
-
ns
-
5
-
ns
td(OFF)
-
12
-
ns
tf
-
6
-
ns
-
10.5
12.0
nC
-
1.4
2.0
nC
-
4.9
5.5
nC
-
230
-
pF
td(ON)
Rise Time (Note 5)
tr
Turn-Off Delay Time (Note 5)
Fall Time (Note 5)
Total Gate Charge (Note 5)
Qg(TOT)
Gate-Source Charge (Note 5)
Qgs
Gate-Drain Charge (Note 5)
Qgd
Short-Circuit Input Capacitance,
Common Source
CISS
TEST CONDITIONS
VDD = 30V, RL = 3Ω
ID = 10A, VGS = 10V, RG = 50Ω
See Figure 14
VDS = 50V, VGS = 10V, ID = 10A
See Figures 16 and 17
VDS = 25V, VGS = 0V, f = 1MHz
Short-Circuit Output Capacitance,
Common Source for Upper FET
COSS(U)
-
150
-
pF
Short Circuit Output Capacitance
Common Source for Lower FET
COSS(L)
-
225
-
pF
Short-Circuit Reverse Transfer
Capacitance, Common Source
CRSS
-
40
-
pF
Thermal Resistance Junction to Case
RθJC
-
-
2.7
oC/W
Thermal Resistance Junction to Ambient
RθJA
-
-
60
oC/W
MIN
TYP
MAX
UNITS
ISD = 10A, VGS = 0V
-
1.05
1.25
V
Source-Drain Diode Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
SOURCE-TO-DRAIN DIODE SPECIFICATIONS (Across Z1 and Z2)
Forward Voltage (Note 4)
VSD
Reverse Recovery Time (Across Z1)
trr(S1-D1)
ISD = 10A, dISD/dt = 100A/µs
-
50
-
ns
Reverse Recovery Time (Across Z2)
trr(S2-D2)
ISD = 10A, dISD/dt = 100A/µs
-
75
-
ns
ISD = 10A, VGS = 0V
-
8.5
9.5
V
ISD = 10A, dISD/dt = 100A/µs
-
200
-
ns
VGS = 10V, ID = 10A, TC = 25oC
-
90
-
%
SOURCE2-TO-DRAIN1 DIODE SPECIFICATIONS D (Across D1)
Forward Voltage (Note 4)
VSD
Reverse Recovery Time
trr
DEVICE MATCHING
Drain-Source On Resistance Match
rDS(ON)M
NOTES:
4. Pulse test: Pulse Width ≤ 300µs, Duty Cycle ≤ 2%.
5. Independent of operating temperature.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
3
HIP2060
Typical Performance Curves
50
TC = 25oC
IAS, AVALANCHE CURRENT (A)
ID, DRAIN CURRENT (A)
50
10µs
10
100µs
10
5
1ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
1
0.5
10ms
STARTING TC = 125oC
5
DC
5
10
50
VDS, DRAIN-TO-SOURCE VOLTAGE (V)
1
STARTING TC = 25oC
1
0.001
100
20
VGS = 15V
25oC
-40oC
VDS = 15V
VGS = 10V
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
VGS = 12V
15
VGS = 8V
10
5
PULSE DURATION = 300µs, TC = 25oC
0
0
2
4
6
8
15
150oC
10
5
0
0
10
VDS, DRAIN-TO-SOURCE VOLTAGE (V)
NORMALIZED BVDSS
NORMALIZED rDS(ON)
1.0
0.5
75
125
8
10
ID = 100µA
1.5
25
6
1.2
2.0
-25
4
FIGURE 4. TRANSFER CHARACTERISTICS
PULSE DURATION = 300µs, VGS = 10V, ID = 10A
0
-75
2
VGS, GATE-TO-SOURCE VOLTAGE (V)
FIGURE 3. SATURATION CHARACTERISTICS
2.5
1
FIGURE 2. UNCLAMPED INDUCTIVE-SWITCHING
FIGURE 1. SAFE-OPERATING AREA CURVE
20
0.01
0.1
tAV, TIME IN AVALANCHE (ms)
1.1
1.0
0.9
0.8
-75
175
TJ, JUNCTION TEMPERATURE (oC)
-25
25
75
125
175
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 5. NORMALIZED rDS(ON) vs JUNCTION TEMPERATURE
FIGURE 6. NORMALIZED BVDSS vs JUNCTION TEMPERATURE
4
HIP2060
Typical Performance Curves
(Continued)
16
2.0
VGS, GATE-SOURCE VOLTAGE (V)
NORMALIZED VGS(TH)
VGS = VDS, ID = 250µA
1.5
1.0
0.5
0
-75
-25
25
75
125
12
ID = 10A, TC = 25 oC
8
4
0
175
VDS = 50V
VDS = 30V
VDS = 20V
5
0
TJ, JUNCTION TEMPERATURE (oC)
10
ID, DRAIN CURRENT (A)
CRSS
COSS(U)
COSS(L)
CISS
200
0
VGS = 15V
VGS = 10V
8
6
4
2
0
5
10
15
20
0
25
25
50
VDS, DRAIN-TO-SOURCE VOLTAGE (V)
FIGURE 9. CAPACITANCE vs VOLTAGE
ZθJC, NORMALIZED THERMAL RESPONSE
C, CAPACITANCE (pF)
800
400
20
12
VGS = 0V, f = 1MHz, TC = 25oC
600
15
FIGURE 8. GATE-SOURCE VOLTAGE vs GATE CHARGE
FIGURE 7. NORMALIZED VGS(TH) vs JUNCTION
TEMPERATURE
1000
10
Q, GATE CHARGE (nC)
TC = 25oC
D = 1.0
0.5
0.2
0.1
0.1
0.05
0.02
0.01
SINGLE PULSE
0.01
10-5
150
FIGURE 10. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
10
1
75
100
125
TC, CASE TEMPERATURE (oC)
NOTES:
1. DUTY FACTOR, D = t1/t2
2. PEAK TJ = PDM x (ZθJC) +TC
10-3
10-2
10-1
10o
10-4
t1, RECTANGULAR PULSE DURATION (s)
101
FIGURE 11. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
5
HIP2060
Test Circuits and Waveforms
tP
VDS
0
IAS
+
DUT
-
VGS
VDD
ID
tP
0V
10V
VGS
L
RG
tAV
ID
0
BVDSS
VDS
0.01Ω
0
FIGURE 12. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 13. UNCLAMPED ENERGY WAVEFORMS
tON
VDD
tOFF
td(ON)
td(OFF)
tr
VDS
RL
tf
90%
90%
VDS
VGS
10%
10%
DUT
90%
0V
RGS
50%
VGS
50%
PULSE WIDTH
10%
FIGURE 14. RESISTIVE SWITCHING TEST CIRCUIT
CURRENT
REGULATOR
+
15V
BATTERY -
0.2µF
FIGURE 15. RESISTIVE SWITCHING WAVEFORMS
+VDS
QG
SAME TYPE
AS DUT
10V
25kΩ
0.1µF
QGS
VG
DUT
0
QGD
IGS
CHARGE
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. BASIC GATE CHARGE WAVEFORM
6
HIP2060
1µF
0.22µF
0.22µF
UF 4002
RL = 8Ω
30µH
+36V
0.47µF
3.9Ω
0.22µF
+12V
BHB
BHO
HEN
BHS
DIS
BLO
VSS
BLS
OUT
VDD
IN+
VCC
IN-
ALS
HDEL
ALO
LDEL
AHS
AHB
AHO
10Ω
30µH
1µF
10Ω
HIP2060
+12V
10Ω
10Ω
HIP4080A
100Ω
ILIM
100kΩ
100kΩ
0.22µF
HIP2060
UF 4002
0.22µF
∑
+
0.1Ω
0.001µF
FEEDBACK
+
AUDIO INPUT
250kHz
FIGURE 18. 70W SWITCHING AUDIO AMPLIFIER APPLICATION CIRCUIT
Device Model Netlist for HIP2060 Half Bridge Power MOSFET Array
.SUBCKT HIP2060 1 2 3 4 5
X1
6 1 7 3 HIP2060_1
LS1 5 6 7.5n
X2 7 2 8 3 HIP2060_1
LS2 7 4 7.5n
LS3 8 3 7.5n
.ENDS
.SUBCKT HIP2060_1 3 2 11 9
MOS1
4 2 1 1 NMOS1
JFET
10 1 4 J1
D1
5 6 D1
DBODY
1 10 D2
DBREAK 10 7 D3
DSUB
9 3 D4
VBREAK 7 1
DC 90
C21
2 1
850P
C23
2 10 50P
C24
2 4
1350P
RDRAIN 3 10 1.5e-03
RSOURCE 1 11 17.5e-03
FDSCHRG 4 2 VMEAS 1.0
E41
5 11 4 1 1.0
VPINCH 6 8 DC 10.0
VMEAS 8 11 DC 0.0
.MODEL NMOS1 NMOS LEVEL=3 (VTO=2.75 TOX=5e-08 KP=3.150e-03 PHI=0.65 GAMMA=2.55
+ VMAX=6.42e+07 NSUB=4.33e+16 THETA=0.60973 ETA=0.0015 KAPPA=1.275 L=1u W=5950u)
.MODEL J1 NJF (VTO=-15.0 BETA=10.736 LAMBDA=1.15e-02 P1.MODEL D1 D (IS=1.0e-15 N=0.03 RS=1.0)
.MODEL D2 D (IS=3.0e-13 RS=2.5e-03 TT=20N CJO=350e-12)
.MODEL D3 D (IS=1.0e-13 N=1.0 RS=2.0)
.MODEL D4 D (IS=1.0e-13 RS=2.0e-03 CJO=197e-12)
.ENDS
NOTE: For further discussion of the PSPICE PowerFET Macromodel consult “Spicing-up SPICE II Software for Power MOSFET Modeling”,
Intersil Application Note AN8610.
7
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