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1-888-I
100V, 2A Peak, High Frequency Half-Bridge Drivers with
Rising Edge Delay Timer
HIP2122, HIP2123
Features
The HIP2122 and HIP2123 are 100V, high frequency, half-bridge
MOSFET driver ICs. They are based on the popular ISL2100A and
ISL2101A half-bridge drivers. Like the ISL2100A, two logic
inputs, LI and HI, control both bridge outputs, LO and HO. All logic
inputs are VDD tolerant.
• 9 Ld TDFN “B” Package Compliant with 100V Conductor
Spacing Guidelines per IPC-2221
These drivers have a programmable dead-time to insure
break-before-make operation between the high-side and low-side
drivers. The dead-time is adjustable up to 220ns. The internal
logic does not prevent both outputs from turning on
simultaneously if both inputs are high simultaneously for a time
greater than the programmed delay.
A single PWM logic input controls both bridge outputs (HO, LO).
An enable pin (EN), when low, drives both outputs to a low state.
All logic inputs are VDD tolerant and the HIP2122 has CMOS
inputs with hysteresis for superior operation in noisy
environments.
The HIP2122 has hysteretic inputs with thresholds that are
proportional to VDD. The HIP2123 has 3.3V logic/TTL compatible
inputs.
Two package options are provided. The 10 lead 4x4 DFN package
has standard pinouts. The 9 lead 4x4 DFN package omits pin 2 to
comply with 100V conductor spacing per IPC-2221.
HALF
BRIDGE
• Break-Before-Make Dead-Time Prevents Shoot-through and is
adjustable up to 220ns
• Bootstrap Supply Max Voltage to 114VDC
• Wide Supply Voltage Range (8V to 14V)
• Supply Undervoltage Protection
• CMOS Compatible Input Thresholds with Hysteresis (HIP2122)
• 1.6/1 Typical Output Pull-up/Pull-down Resistance
• On-Chip 1Ω Bootstrap Diode
Applications
• Telecom Half-Bridge DC/DC Converters
• UPS and Inverters
• Motor Drives
• Class-D Amplifiers
• Forward Converter with Active Clamp
Related Literature
• FN7668, HIP2120, HIP2121 “100V, 2A Peak, High Frequency
Half-Bridge Drivers with Adjustable Dead Time Control and
PWM Input”
100V MAX
VDD
HB
HI
HO
LI
PWM
CONTROLLER
SECONDARY
CIRCUITS
HS
RDT
VSS
LO
EPAD
FEEDBACK
WITH
ISOLATION
DEADTIME (ns)
HIP2122, HIP2123
200
160
140
120
100
80
60
40
20
8
FIGURE 1. TYPICAL APPLICATION
December 23, 2011
FN7670.0
1
16
24
32
RDT (kΩ)
40 48 56 64 80
FIGURE 2. DEAD-TIME vs TIMING RESISTOR
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
HIP2122, HIP2123
Block Diagram
VDD
HB
HIP2122,
HIP2123
UNDER
VOLTAGE
HO
LEVEL
SHIFT
HS
HIP2122
HIP2122/23
HO
DELAY
RDT
UNDER
VOLTAGE
OPTIONAL INVERSION
FOR FUTURE PART
NUMBERS
LO
LO
DELAY
HIP2122
EPAD IS
ELECTRICALLY
ISOLATED
HIP2122/23
VSS
EPAD
Pin Configurations
HIP2122, HIP2123
(9 LD 4X4 TDFN)
TOP VIEW
HIP2122, HIP2123
(10 LD 4X4 TDFN)
TOP VIEW
VDD
1
10 LO
HB
2
9
VSS
HO
3
8
LI
HB
3
HS
4
7
HI
HO
NC
5
6
RDT
HS
EPAD
2
VDD
10 LO
1
9
VSS
8
LI
4
7
HI
5
6
RDT
EPAD
FN7670.0
December 23, 2011
HIP2122, HIP2123
Pin Descriptions
9 LD TDFN 10 LD TDFN SYMBOL
DESCRIPTION
1
1
VDD
Positive supply voltage for lower gate driver. Decouple this pin with a ceramic capacitor to VSS.
3
2
HB
High-side bootstrap supply voltage referenced to HS. Connect the positive side of bootstrap capacitor to this pin.
Bootstrap diode is on-chip.
4
3
HO
High-side output. Connect to gate of high-side power MOSFET.
5
4
HS
High-side source connection. Connect to source of high-side power MOSFET. Connect the negative side of
bootstrap capacitor to this pin.
8
8
LI
Low side driver input. For LI = 1, LO = 1 after programmed delay time; for LI = 0, LO = 0 with minimal delay.
7
7
HI
High side driver input. For HI = 1, HO = 1 after programmed delay time; for Hi = 0, HO = 0 with minimal delay.
9
9
VSS
Negative supply input, which will generally be ground.
10
10
LO
Low-side output. Connect to gate of low-side power MOSFET.
-
5
NC
No Connect. This pin is isolated from all other pins.
6
6
RDT
A resistor connected between this pin and VSS adds additional delay time to the normal rising edge propagation
delay.
-
-
EPAD
Exposed pad. Connect to ground or float. The EPAD is electrically isolated from all other pins.
Ordering Information
PART NUMBER
(Notes 1, 2, 4)
PART
MARKING
INPUT
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
HIP2122FRTAZ
HIP 2122AZ
CMOS
- 40 to +125
10 Ld 4x4 TDFN
L10.4x4
HIP2123FRTAZ
HIP 2123AZ
3.3V/TTL
- 40 to +125
10 Ld 4x4 TDFN
L10.4x4
HIP2122FRTBZ (Note 3)
HIP 2122BZ
CMOS
- 40 to +125
9 Ld 4x4 TDFN
L9.4x4
HIP2123FRTBZ (Note 3)
HIP 2123BZ
3.3V/TTL
- 40 to +125
9 Ld 4x4 TDFN
L9.4x4
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
PbHfree products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. “B” package option has alternate pin assignments for compliance with 100V Conductor Spacing Guidelines per IPC-2221. Note that Pin 2 is omitted
for additional spacing.
4. For Moisture Sensitivity Level (MSL), please see device information page for HIP2122, HIP2123. For more information on MSL please see tech brief
TB363.
3
FN7670.0
December 23, 2011
HIP2122, HIP2123
Table of Contents
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Maximum Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
ESD Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Switching Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Selecting the Boot Capacitor Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Transients on HS Node . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PC Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
EPAD Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4
FN7670.0
December 23, 2011
HIP2122, HIP2123
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VDD, VHB - VHS (Notes 5, 6) . . . . . . . . . . . . . . . -0.3V to 18V
LI and HI Input Voltage (Note 6) . . . . . . . . . . . . . . . . . . .-0.3V to VDD + 0.3V
Voltage on LO (Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to VDD + 0.3V
Voltage on HO (Note 6) . . . . . . . . . . . . . . . . . . . . . VHS - 0.3V to VHB + 0.3V
Voltage on HS (Continuous) (Note 6) . . . . . . . . . . . . . . . . . . . . . -1V to 110V
Voltage on HB (Note 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118V
Average Current in VDD to HB Diode . . . . . . . . . . . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
JA (°C/W)
JC (°C/W)
10 Ld TDFN (Notes 7, 8) . . . . . . . . . . . . . . .
42
4
9 Ld TDFN (Notes 7, 8) . . . . . . . . . . . . . . . .
42
4
Max Power Dissipation at +25°C in Free Air
10 Ld TDFN (Notes 7, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0W
9 Ld TDFN (Notes 7, 8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1W
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Maximum Recommended Operating
Conditions
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V to 14V
Voltage on HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to 100V
Voltage on HS . . . . . . . . . . . . . . . . . . . . . .(Repetitive Transient) -5V to 105V
Voltage on HB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VHS + 8V to VHS + 14V and
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD - 1V to VDD + 100V
HS Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <50V/ns
ESD Ratings
Human Body Model Class 2 (Tested per JESD22-A114E). . . . . . . . . . 3000V
Machine Model Class B (Tested per JESD22-A115-A). . . . . . . . . . . . . . 300V
Charged Device Model Class IV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. The HIP2122 and HIP2123 are capable of derated operation at supply voltages exceeding 14V. Figure 20 shows the high-side voltage derating curve
for this mode of operation.
6. All voltages referenced to VSS unless otherwise specified.
7. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
8. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
VDD = VHB = 12V, VSS = VHS = 0V, RDT = 0K, PWM= 0V, No Load on LO or HO, Unless Otherwise Specified.
Boldface limits apply over the operating temperature range, -40°C to +125°C.
TA = +25°C
PARAMETERS
SYMBOL
TEST CONDITIONS
TA = -40°C to +125°C
MIN
TYP
MAX
MIN (Note 9) MAX (Note 9)
UNITS
SUPPLY CURRENTS
VDD Quiescent Current
VDD Operating Current
IDD80
RDT = 80k
-
470
850
-
900
µA
IDD8k
RDT = 8k
-
1.0
2.1
-
2.2
mA
IDDO80k
f = 500kHz, RDT = 80k
-
2.5
3
-
3
mA
IDDO8k
f = 500kHz, RDT = 8k
-
3.4
4
-
4
mA
Total HB Quiescent Current
IHB
LI = HI = 0V
-
65
115
-
150
µA
Total HB Operating Current
IHBO
f = 500kHz
-
2.0
2.5
-
3
mA
HB to VSS Current, Quiescent
IHBS
LI = HI = 0V; VHB = VHS = 114V
-
0.05
1.5
-
10
µA
HB to VSS Current, Operating
IHBSO
f = 500kHz; VHB = VHS = 114V
-
1.2
1.5
-
1.6
mA
INPUT PINS
Low Level Input Voltage
Threshold
VIL
HIP2122 (CMOS)
3.7
4.4
-
2.7
-
Low Level Input Voltage
Threshold
VIL
HIP2123 (3.3V/TTL)
1.4
1.8
-
1.2
-
High Level Input Voltage
Threshold
VIH
HIP2122 (CMOS)
-
6.54
7.93
5.3
8.2
High Level Input Voltage
Threshold
VIH
HIP2123 ((3.3V/TTL)
-
1.8
2.2
-
2.4
5
V
V
V
V
FN7670.0
December 23, 2011
HIP2122, HIP2123
Electrical Specifications
VDD = VHB = 12V, VSS = VHS = 0V, RDT = 0K, PWM= 0V, No Load on LO or HO, Unless Otherwise Specified.
Boldface limits apply over the operating temperature range, -40°C to +125°C.
TA = +25°C
PARAMETERS
SYMBOL
TEST CONDITIONS
TA = -40°C to +125°C
MIN
TYP
MAX
-
2.2
-
-
-
V
RI
-
210
-
100
500
k
VDD Rising Threshold
VDDR
6.8
7.3
7.8
6.5
8.1
V
VDD Threshold Hysteresis
VDDH
-
0.6
-
-
-
V
HB Rising Threshold
VHBR
6.2
6.9
7.5
5.9
7.8
V
HB Threshold Hysteresis
VHBH
-
0.6
-
-
-
V
Input Voltage Hysteresis
VIHYS
Input Pull-down Resistance
HIP2122 (CMOS)
MIN (Note 9) MAX (Note 9)
UNITS
UNDERVOLTAGE PROTECTION
BOOTSTRAP DIODE
Low Current Forward Voltage
VDL
IVDD-HB = 100mA
-
0.6
0.7
-
0.8
V
High Current Forward Voltage
VDH
IVDD-HB = 100mA
-
0.7
0.9
-
1
V
Dynamic Resistance
RD
IVDD-HB = 100mA
-
0.8
1
-
1.5

LO GATE DRIVER
Low Level Output Voltage
VOLL
ILO = 100mA
-
0.25
0.4
-
0.5
V
High Level Output Voltage
VOHL
ILO = -100mA, VOHL = VDD - VLO
-
0.25
0.4
-
0.5
V
Peak Pull-Up Current
IOHL
VLO = 0V
-
2
-
-
-
A
Peak Pull-Down Current
IOLL
VLO = 12V
-
2
-
-
-
A
Low Level Output Voltage
VOLH
IHO = 100mA
-
0.25
0.4
-
0.5
V
High Level Output Voltage
VOHH
IHO = -100mA, VOHH = VHB - VHO
-
0.25
0.4
-
0.5
V
Peak Pull-Up Current
IOHH
VHO = 0V
-
2
-
-
-
A
Peak Pull-Down Current
IOLH
VHO = 12V
-
2
-
-
-
A
HO GATE DRIVER
6
FN7670.0
December 23, 2011
HIP2122, HIP2123
Switching Specifications
VDD = VHB = 12V, VSS = VHS = 0V, RDT = 0k, No Load on LO or HO, Unless Otherwise Specified.
TJ = +25°C
PARAMETERS
(see “Timing Diagram”)
SYMBOL
TEST
CONDITIONS
TJ = -40°C to +125°C
MIN
TYPE
MAX
MIN
(Note 9)
MAX
(Note 9)
UNITS
HO Turn-Off Propagation Delay
HI Falling to HO Falling
tPLHO
-
32
50
-
60
ns
LO Turn-Off Propagation Delay
LO Falling to LO Falling
tPLLO
-
32
50
-
60
ns
Minimum Dead-Time Delay (see Note 10)
HO Falling to LO Rising
tDTHLmin
RDT = 80k,
HI 1 to 0, LI 0 to 1
15
35
50
10
60
ns
Minimum Dead-Time Delay (see Note 10)
LO Falling to HO Rising
tDTLHmin
RDT = 80k
Li 1 to 0, HI 0 to 1
15
25
50
10
60
ns
Maximum Dead-Rising Delay (see Note 10)
HO Falling to LO rising
tDTHLmax
RDT = 8k,
HI 1 to 0, LI 0 to 1
150
220
300
-
-
ns
Maximum Dead-Time Delay (see Note 10)
LO Falling to HO Rising
tDTLHmax
RDT = 8k,
Li 1 to 0, HI 0 to 1
150
220
300
-
-
ns
CL = 1nF
-
10
-
-
-
ns
CL = 0.1mF
-
0.5
0.6
-
0.8
µs
-
10
-
-
-
ns
Either Output Rise/Fall Time
(10% to 90%/90% to 10%)
tRC,tFC
Either Output Rise/Fall Time
(3V to 9V/9V to 3V)
tR,tF
Bootstrap Diode Turn-On or Turn-Off Time
tBS
NOTES:
9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits are established by
characterization and are not production tested.
10. Dead-Time is defined as the period of time between the LO falling and HO rising or between HO falling and LO rising when the LI and HI inputs
transition simultaneously.
Timing Diagram
LI
LO
tDT
tDT
90%
90%
HO 10%
10%
HI
tR
tPL
tPH
tF
tR AND tF FOR LO ARE NOT
SHOWN FOR CLARITY
EN
7
FN7670.0
December 23, 2011
HIP2122, HIP2123
Typical Performance Curves
10.0
10.0
T = -40°C
IDDO (mA)
IDDO (mA)
T = -40°C
T = +25°C
1.0
T = +25°C
1.0
T = +125°C
T = +150°C
T = +125°C
T = +150°C
0.1
10k
0.1
100k
10k
1M
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 3. HIP2122 IDD OPERATING CURRENT vs FREQUENCY
FIGURE 4. HIP2123 IDD OPERATING CURRENT vs FREQUENCY
10.0
10.0
T = -40°C
T = +150°C
1.0
IHBSO (mA)
IHBO (mA)
1M
T = +25°C
T = +150°C
0.1
1.0
T = -40°C
T = +25°C
0.1
T = +125°C
0.01
10k
100k
0.01
10k
1M
T = +125°C
100k
FIGURE 5. IHB OPERATING CURRENT vs FREQUENCY
FIGURE 6. IHBS OPERATING CURRENT vs FREQUENCY
300
200
VOHL, VOHH (mV)
VOLL, VOLH (mV)
VDD = VHB = 14V
250
200
150
VDD = VHB = 8V
100
VDD = VHB = 14V
150
100
VDD = VHB = 8V
VDD = VHB = 12V
50
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
VDD = VHB = 12V
50
-50
0
50
100
150
TEMPERATURE (°C)
FIGURE 7. HIGH LEVEL OUTPUT VOLTAGE vs TEMPERATURE
8
-50
0
50
100
150
TEMPERATURE (°C)
FIGURE 8. LOW LEVEL OUTPUT VOLTAGE vs TEMPERATURE
FN7670.0
December 23, 2011
HIP2122, HIP2123
Typical Performance Curves
(Continued)
0.70
6.7
0.65
VDDR
6.3
6.1
VDDH, VHBH (V)
VDDR, VHBR (V)
6.5
VHBR
5.9
5.7
5.3
-50
0
50
TEMPERATURE (°C)
100
0
50
tLPLH
45
tHPLH
35
tLPHL
30
tHPHL
0
50
100
150
50
150
tLPLH
40
tHPLH
30
tHPHL
25
-50
0
tMON, tMOFF (ns)
tMON
6.5
6.0
tMOFF
5.5
5.0
4.5
0
50
100
150
TEMPERATURE (°C)
FIGURE 13. HIP2122 DELAY MATCHING vs TEMPERATURE
9
50
100
150
TEMPERATURE (°C)
7.5
7.0
tLPHL
35
FIGURE 12. HIP2123 PROPAGATION DELAYS vs TEMPERATURE
8.0
tMON, tMOFF (ns)
100
45
TEMPERATURE (°C)
FIGURE 11. HIP2122 PROPAGATION DELAYS vs TEMPERATURE
4.0
-50
50
TEMPERATURE (°C)
55
tLPLH, tLPHL, tHPLH, tHPHL (ns)
tLPLH, tLPHL, tHPLH, tHPHL (ns)
VDDH
FIGURE 10. UNDERVOLTAGE LOCKOUT HYSTERESIS vs
TEMPERATURE
55
25
-50
0.50
0.40
-50
150
FIGURE 9. UNDERVOLTAGE LOCKOUT THRESHOLD vs
TEMPERATURE
40
0.55
0.45
5.5
VHBH
0.60
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
-50
tMON
tMOFF
0
50
100
150
TEMPERATURE (°C)
FIGURE 14. HIP2123 DELAY MATCHING vs TEMPERATURE
FN7670.0
December 23, 2011
HIP2122, HIP2123
(Continued)
3.5
4.5
3.0
4.0
3.5
2.5
IOHL, IOHH (A)
IOHL, IOHH (A)
Typical Performance Curves
2.0
1.5
1.0
2.0
1.5
0.5
0
2
4
6
8
VLO, VHO (V)
10
0
12
FIGURE 15. PEAK PULL-UP CURRENT vs OUTPUT VOLTAGE
120
110
100
90
80
70
60
50
40
30
20
10
0
IDD
IHB
0
5
10
VDD, VHB (V)
15
320
300
280
260
240
220
200
180
160
140
120
100
80
60
40
20
0
20
FIGURE 17. HIP2122 QUIESCENT CURRENT vs VOLTAGE
0
0.10
100
1.10-4
1.10-5
1.10-6
6
VLO, VHO (V)
8
10
12
IHB
120
1.10-3
4
IDD
1.00
0.01
2
5
10
VDD, VHB (V)
15
20
FIGURE 18. HIP2123 QUIESCENT CURRENT vs VOLTAGE
VDD TO VSS VOLTAGE (V)
FORWARD CURRENT (A)
0
FIGURE 16. PEAK PULL-DOWN CURRENT vs OUTPUT VOLTAGE
IDD, IHB (µA)
IDD, IHB (µA)
2.5
1.0
0.5
0
3.0
80
60
40
20
0
0.3
0.4
0.5
0.6
0.7
0.8
FORWARD VOLTAGE (V)
FIGURE 19. BOOTSTRAP DIODE I-V CHARACTERISTICS
10
12
13
14
15
16
VHS TO VSS VOLTAGE (V)
FIGURE 20. VHS VOLTAGE vs VDD VOLTAGE
FN7670.0
December 23, 2011
HIP2122, HIP2123
Functional Description
Functional Overview
The HIP2122/23 have independent control inputs, LI and HI, for
each output; LO and HO. When LI is low, LO is low and likewise,
when HI is low, HO is low. The output negative transitions occur
with minimal (and fixed) propagation delays.
of the high-side FET, the high-side UV lockout may engage
resulting with an unexpected operation.
Application Information
Selecting the Boot Capacitor Value
The positive transitions of each output are delayed by the
programmed delay as set by RDT. With 80k, the delay is
nominally 25ns. With 8k, the delay is nominally 220ns. Resistors
values less than 8k and greater than 80k are not recommended.
The delay time as a function of RDT is approximately
tDT(ns) = 2/RDT.
The boot capacitor value is chosen not only to supply the internal
bias current of the high-side driver but also, and more
significantly, to provide the gate charge of the driven FET without
causing the boot voltage to sag excessively. In practice, the boot
capacitor should have a total charge that is about 20 times the
gate charge of the driven power FET for approximately a 5% drop
in voltage after the charge has been transferred from the boot
capacitor to the gate capacitance.
Delaying the rising edge but not the falling edge of each output is
the technique that prevents shoot-thru. Please note that there is
no logic that prevents both outputs from being on if both inputs
are on simultaneously.
The following parameters are required to calculate the value of
the boot capacitor for a specific amount of voltage droop. In this
example, the values used are arbitrary. They should be changed
to comply with the actual application.
When the PWM input transitions, it is necessary to insure that
both bridge FETS are not on at the same time to prevent
shoot-through currents (break before make). The programmable
dead time forces both outputs to be off before either of the
bridge FETs is driven on. An 8kΩ resistor connected between RDT
and VSS results in a nominal dead time of 250ns. An 80kΩ
results with a minimum nominal dead time of 50ns. Resistors
values less than 8k and greater than 80k are not recommended.
Dead-time as a function of RDT is nominally tDT(ns) = 2/RDT.
The high-side driver bias is established by the boot capacitor
connected between HB and HS. The charge on the boot capacitor
is provided by the internal boot diode that is connected to VDD.
The current path to charge the boot capacitor occurs when the
low-side bridge FET is on. This charge current is limited in
amplitude by the inherent resistance of the boot diode and by the
drain-source voltage of the low-side FET. Assuming that the on
time of the low-side FET is sufficiently long to fully charge the
boot capacitor, the boot voltage will charge very close to VDD
(less the boot diode drop and the low-side FET on voltage).
When the HI input transitions high, the high-side bridge FET is
driven on after the delay time. Because the HS node is connected
to the source of the high-side FET, the HS node will rise almost to
the level of the bridge voltage (less the conduction voltage across
the bridge FET). Because the boot capacitor voltage is referenced
to the source voltage of the high-side FET, the HB node is VDD
volts above the HS node and the boot diode is reversed biased.
Because the high-side driver circuit is referenced to the HS node,
the HO output is now approximately VHB + VBRIDGE above
ground.
During the low to high transition of the HS node, the boot
capacitor sources the necessary gate charge to fully enhance the
high-side bridge FET gate. After the gate is fully charged, the boot
capacitor no longer sources the charge to the gate but continues
to provide bias current to the high-side driver. It is clear that the
charge of the boot capacitor must be substantially larger than
the required charge of the high-side FET and high-side driver
otherwise the boot voltage will sag excessively. If the boot
capacitor value is too small for the required maximum of on-time
11
VDD = 10V
VDD can be any value between 7 and 14VDC
VHB = VDD - 0.6V = VHO High side driver bias voltage (VDD - boot diode
voltage) referenced to VHS
Period = 1ms
This is the longest expected switching period
IHB = 100µA
Worst case high side driver current when
xHO = high
(this value is specified for VDD = 12V but the
error is not significant)
RGS = 100kΩ
Gate-source resistor
(usually not needed)
Ripple = 5%
Desired ripple voltage on the boot capacitor
(larger ripple is not recommended)
Igate_leak = 100nA
From the FET vendor’s datasheet
Qgate80V = 64nC
From Figure 21
VGS, GATE-TO-SOURCE VOLTAGE (V)
The enable pin, EN, when low, drives both outputs to a low state.
12
ID = 33A
VDS = 80V
10
VDS = 50V
8
VDS = 20V
6
4
2
0
0
10
20
30
40
50
60
70
80
QG TOTAL GATE CHARGE (nC)
FIGURE 21. TYPICAL GATE CHARGE OF A POWER FET
The following equations calculate the total charge required for
the Period. This equation assumes that all of the parameters are
constant during the period duration. The error is insignificant if
the ripple is small.
FN7670.0
December 23, 2011
HIP2122, HIP2123
Qc = Qgate80V + Period x (IHB + VHO/RGS + Igate_leak)
L is the total parasitic inductance of the low-side FET drainsource path and di/dt is the rate at which the high-side FET is
turned off. With the increasing power levels of power supplies
and motor, clamping this transient become more and more
significant for the proper operation of the HIP2122/23.
Cboot = Qc/(Ripple * VDD)
Cboot = 0.52µF
If the gate to source resistor is removed (RGS is usually not
needed or recommended), then:
Cboot = 0.33µF
HO
Typical Application Circuit
IN D U C T IV E
LO AD
HS
+
Figure 23 is an example of how the HIP2122/23 can be
configured for a half bridge power supply application.
LO
-
Depending on the application, the switching speed of the bridge
FETs can be reduced by adding series connected resistors
between the xHO outputs and the FET gates. Gate-Source
resistors are recommended on the low Side FETs to prevent
unexpected turn-on of the bridge should the bridge voltage be
applied before VDD. Gate-source resistors on the high side FETs
are not usually required if low-side gate-source resistors are
used. If relatively small gate-source resistors are used on the
high-side FETs, be aware that they will load the boot capacitor,
which will then require a larger value for the boot capacitor.
+
VSS
FIGURE 22. PARASITIC INDUCTANCE CAUSES TRANSIENTS ON HS
NODE
There are several ways of reducing the amplitude of this
transient. If the bridge FETs are turned off more slowly to reduce
di/dt, the amplitude will be reduced but at the expense of more
switching losses in the FETs. Careful PCB design will also reduce
the value of the parasitic inductance. However, these two
solutions by themselves may not be sufficient. Figure 22
illustrates a simple method for clamping the negative transient.
A fast PN junction, 1A diode is connected between xHS and VSS
as shown. It is important that this diode be placed as close as
possible to the xHS and VSS pins to minimize the parasitic
inductance of this current path. Because this clamping diode is
essentially in parallel with the body diode of the low side FET, a
small value resistor is necessary to limit current when the body
diode of the low side bridge FET is conducting during the dead
time.
Transients on HS Node
An important operating condition that is frequently overlooked by
designers is the negative transient on the xHS pins that occurs
when the high side bridge FET turns off. The Absolute Maximum
transient allowed on the xHS pin is -6V but it is wise to minimize
the amplitude to lower levels. This transient is the result of the
parasitic inductance of the low-side drain-source conductor on
the PCB. Even the parasitic inductance of the low-side FET
contributes to this transient.
Please note that a similar transient with a positive polarity occurs
when the low-side FET turns off. This is less frequently a problem
because xHS node is floating up toward the bridge bias voltage.
The Absolute Max voltage rating for the xHS node does need to
be observed when the positive transient occurs.
When the high-side bridge FET turns off (see Figure 22), because
of the inductive characteristics of the load, the current that was
flowing in the high-side FET (blue) must rapidly commutate to
flow through the low side FET (red). The amplitude of the
negative transient impressed on the xHS node is (di/dt x L) where
8-15V
VDD
HB
HI
DRIVER
PWM
CONTROLLER
EN
RDT
LOGIC
PWM
100V MAX
HO
HS
LO
DRIVER
LO
VSS
ISL78420
FIGURE 23. TYPICAL HALF BRIDGE APPLICATION
12
FN7670.0
December 23, 2011
HIP2122, HIP2123
Power Dissipation
The dissipation of the HIP2122/23 is dominated by the gate
charge required by the driven bridge FETs and the switching
frequency. The internal bias and boot diode also contribute to the
total dissipation but these losses are usually insignificant
compared to the gate charge losses.
• When practical, minimize impedances in low level signal
circuits; the noise, magnetically induced on a 10k resistor, is
10x larger than the noise on a 1k resistor.
• Be aware of magnetic fields emanating from transformers and
inductors. Core gaps in these structures are especially bad for
emitting flux.
The calculation of the power dissipation of the HIP2122/23 is
very simple.
• If you must have traces close to magnetic devices, align the
traces so that they are parallel to the flux lines.
Gate Power (for the HO and LO outputs):
• The use of low inductance components, such as chip resistors
and chip capacitors is recommended.
Pgate = 4 x Qgate x Freq x VDD
where
Qgate is the charge of the driven bridge FET at VDD, and
Freq is the switching frequency.
Boot diode dissipation:
Idiode_avg = Qgate x Freq
Pdiode = Idiode_avg x 0.6V
where 0.6V is the diode conduction voltage
• Use decoupling capacitors to reduce the influence of parasitic
inductors. To be effective, these capacitors must also have the
shortest possible lead lengths. If vias are used, connect several
paralleled vias to reduce the inductance of the vias.
• It may be necessary to add resistance to dampen resonating
parasitic circuits. The most likely circuit will be the HO and LO
outputs. In PCB designs with long leads on the LI and HI inputs,
it may also be necessary to add series resistors with the LI and
HI inputs.
Pbias = Ibias x VDD
• Keep high dv/dt nodes away from low level circuits. Guard
banding can be used to shunt away dv/dt injected currents
from sensitive circuits. This is especially true for the PWM
control circuits.
where Ibias is the internal bias current of the HIP2122/23 at the
switching frequency
• Avoid having a signal ground plane under a high dv/dt circuit.
This will inject high di/dt currents into the signal ground paths.
Total Power Dissipation:
• Do power dissipation and voltage drop calculations of the
power traces. Most PCB/CAD programs have built in tools for
calculation of trace resistance.
Bias current:
Ptotal = Pgate + Pdiode + Pbias
Operating Temperatures:
Tj = Ptotal x JA + Tamb
where Tj is the junction temperature at the operating air
temperature, Tamb, in the vicinity of the part.
• Large power components (Power FETs, Electrolytic capacitors,
power resistors, etc.) will have internal parasitic inductance,
which cannot be eliminated. This must be accounted for in the
PCB layout and circuit design.
Tj = Ptotal x JC + TPCB
• If you simulate your circuits, consider including parasitic
components.
where Tj is the junction temperature with the operating
temperature of the PCB, TPCB, measured where the EPAD is
soldered.
EPAD Design Considerations
PC Board Layout
The AC performance of the HIP2122/23 depends significantly on
the design of the PC board. The following layout design
guidelines are recommended to achieve optimum performance
from the HIP2122/23:
The thermal pad of the HIP2122/23 is electrically isolated. It’s
primary function is to provide heat sinking for the IC. It is
recommended to tie the EPAD to VSS(GND).
The following is an example of how to use vias to remove heat
from the IC substrate.
• Understand well how power currents flow. The high amplitude
di/dt currents of the bridge FETs will induce significant voltage
transients on the associated traces.
• Keep power loops as short as possible by paralleling the
source and return traces.
• Use planes where practical; they’re usually more effective than
parallel traces.
• Planes can also be non-grounded nodes.
• Avoid paralleling high di/dt traces with low level signal lines.
High di/dt will induce currents in the low level signal lines.
13
FN7670.0
December 23, 2011
HIP2122, HIP2123
EPAD
GND
PLANE
EPAD
GND
PLANE
FIGURE 24. PCB VIA PATTERN
BOTTOM
LAYER
COMPONENT
LAYER
FIGURE 24. TYPICAL PCB PATTERN FOR THERMAL VIAS
Depending on the amount of power dissipated by the HIP2122/23,
it may be necessary, to connect the EPAD to one or more ground
plane layers. A via array, within the area of the EPAD, will conduct
heat from the EPAD to the GND plane on the bottom layer. If inner
PCB layers are available, it is also be desirable to connect these
additional layers with the plated-through vias.
The number of vias and the size of the GND planes required for
adequate heatsinking is determined by the power dissipated by
the HIP2122/23, the air flow, and the maximum temperature of
the air around the IC.
It is important that the vias have a low thermal resistance for
efficient heat transfer. Do not use “thermal relief” patterns to
connect the vias.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
December 23, 2011
FN7670.0
CHANGE
Initial Release
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on
intersil.com: HIP2122, HIP2123
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff
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Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
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14
FN7670.0
December 23, 2011
HIP2122, HIP2123
Package Outline Drawing
L9.4x4
9 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 1/10
3.2 REF
4.00
A
PIN #1 INDEX AREA
6X 0.80 BSC
6
B
4
1
9X 0 . 40 ± 0.100
6
PIN 1
INDEX AREA
4.00
2.20
1.2 REF
0.15
(4X)
9
5
0.10 M C A B
0.05 M C
4 9 X 0.30
TOP VIEW
3.00
BOTTOM VIEW
(3.00)
SEE DETAIL "X"
0 .75
(9 X 0.60)
0.10 C
BASE PLANE
SEATING PLANE
0.08 C
SIDE VIEW
(3.80)
C
(2.20)
(1.2)
4
0 . 2 REF
C
0 . 00 MIN.
0 . 05 MAX.
(9X 0.30)
(6X 0.8)
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. E-Pad is offset from center.
5. Tiebar (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
15
FN7670.0
December 23, 2011
HIP2122, HIP2123
Package Outline Drawing
L10.4x4
10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 1/08
3.2 REF
4.00
A
PIN #1 INDEX AREA
8X 0.80 BSC
6
B
5
1
10X 0 . 40
6
PIN 1
INDEX AREA
4.00
2.60
0.15
(4X)
10
6
0.10 M C A B
0.05 M C
4 10 X 0.30
TOP VIEW
3.00
BOTTOM VIEW
( 3.00 )
SEE DETAIL "X"
0 .75
( 10 X 0.60 )
0.10 C
BASE PLANE
SEATING PLANE
0.08 C
SIDE VIEW
( 3.80)
C
( 2.60)
0 . 2 REF
C
( 8X 0 . 8 )
0 . 00 MIN.
0 . 05 MAX.
( 10X 0 . 30 )
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
16
FN7670.0
December 23, 2011
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