DATASHEET

HIP4080A
®
Data Sheet
July 2004
80V/2.5A Peak, High Frequency Full Bridge
FET Driver
The HIP4080A is a high frequency, medium voltage Full
Bridge N-Channel FET driver IC, available in 20 lead plastic
SOIC and DIP packages. The HIP4080A includes an input
comparator, used to facilitate the “hysteresis” and PWM
modes of operation. Its HEN (high enable) lead can force
current to freewheel in the bottom two external power
MOSFETs, maintaining the upper power MOSFETs off.
Since it can switch at frequencies up to 1MHz, the HIP4080A
is well suited for driving Voice Coil Motors, switching power
amplifiers and power supplies.
HIP4080A can also drive medium voltage brush motors, and
two HIP4080As can be used to drive high performance
stepper motors, since the short minimum “on-time” can
provide fine micro-stepping capability.
Short propagation delays of approximately 55ns maximize
control loop crossover frequencies and dead-times which
can be adjusted to near zero to minimize distortion, resulting
in precise control of the driven load.
The similar HIP4081A IC allows independent control of all 4
FETs in a Full Bridge configuration.
FN3658.7
Features
• Drives N-Channel FET Full Bridge Including High Side
Chop Capability
• Bootstrap Supply Max Voltage to 95VDC
• Drives 1000pF Load at 1MHz in Free Air at +50°C with
Rise and Fall Times of Typically 10ns
• User-Programmable Dead Time
• Charge-Pump and Bootstrap Maintain Upper Bias
Supplies
• DIS (Disable) Pin Pulls Gates Low
• Input Logic Thresholds Compatible with 5V to 15V Logic
Levels
• Very Low Power Consumption
• Undervoltage Protection
• Pb-Free Available as an Option
Applications
• Medium/Large Voice Coil Motors
• Full Bridge Power Supplies
• Switching Power Amplifiers
The Application Note for the HIP4080A is AN9404.
• High Performance Motor Controls
Ordering Information
• Noise Cancellation Systems
PART
NUMBER
TEMPERATURE
RANGE (°C)
HIP4080AIPZ
(Note 1)
-40 to +85
20 Ld PDIP
(Pb-Free)
E20.3
HIP4080AIP
-40 to +85
20 Ld PDIP
E20.3
HIP4080AIB
-40 to +85
20 Ld SOIC
M20.3
HIP4080AIBZ
(Note 1)
-40 to +85
20 Ld SOIC
(Pb-Free)
M20.3
PACKAGE
PKG.
DWG. #
• Battery Powered Vehicles
• Peripherals
• U.P.S.
Pinout
HIP4080A
(PDIP, SOIC)
TOP VIEW
NOTES:
1. Intersil Pb-Free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-Free products are MSL
classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J Std-020B.
BHB
1
HEN
2
19 BHS
DIS
3
18 BLO
VSS
4
17 BLS
OUT
5
16 VDD
2. Add “T” suffix for Tape and Reel packing option. HIP4080AIP not
available in Tape and Reel.
IN+
6
15 VCC
1
20 BHO
IN-
7
14 ALS
HDEL
8
13 ALO
LDEL
9
12 AHS
AHB 10
11 AHO
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Harris Corporation 1995, Copyright Intersil Americas Inc. 2003, 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HIP4080A
Application Block Diagram
80V
12V
BHO
BHS
HEN
LOAD
BLO
DIS
HIP4080A
IN+
ALO
AHS
IN-
AHO
GND
Functional Block Diagram
GND
(1/2 HIP4080A)
HIGH VOLTAGE BUS ≤ 80VDC
AHB
10
UNDERVOLTAGE
CHARGE
PUMP
LEVEL SHIFT
AND LATCH
DRIVER
11
CBS
AHS
VDD 16
HEN
AHO
12
2
TURN-ON
DELAY
DBS
DIS
3
15
OUT
5
IN+
6
IN_
7
HDEL
8
LDEL
9
DRIVER
TURN-ON
DELAY
+
-
VCC
ALO
13
ALS
14
VSS 4
2
TO VDD (PIN 16)
CBF
+12VDC
BIAS
SUPPLY
HIP4080A
Typical Application (Hysteresis Mode Switching)
80V
1 BHB
BHO 20
2 HEN
BHS 19
DIS
3 DIS
BLO 18
4 VSS
5 OUT
6 IN+
6V
7 ININ
8 HDEL
HIP4080A/HIP4080
12V
9 LDEL
LOAD
BLS 17
VDD 16
VCC 15
12V
ALS 14
ALO 13
AHS 12
10 AHB
AHO 11
GND
+
6V
GND
3
HIP4080A
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VDD and VCC . . . . . . . . . . . . . . . . . . . . -0.3V to 16V
Logic I/O Voltages . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V
Voltage on AHS, BHS . . . -6.0V (Transient) to 80V (25°C to 125°C)
Voltage on AHS, BHS . . . -6.0V (Transient) to 70V (-55°C to 125°C)
Voltage on ALS, BLS . . . . . . . -2.0V (Transient) to +2.0V (Transient)
Voltage on AHB, BHB . . . . . . VAHS, BHS -0.3V to VAHS, BHS +VDD
Voltage on ALO, BLO. . . . . . . . . . . . .VALS, BLS -0.3V to VCC +0.3V
Voltage on AHO, BHO . . . . . . VAHS, BHS -0.3V to VAHB, BHB +0.3V
Input Current, HDEL and LDEL . . . . . . . . . . . . . . . . . . -5mA to 0mA
Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns
All Voltages relative to VSS, unless otherwise specified.
Thermal Resistance (Typical, Note 3)
θJA (°C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
85
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
Maximum Power Dissipation at +85°C
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .470mW
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .530mW
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Max. Junction Temperature. . . . . . . . . . . . . . . . . . +125°C
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300°C
(For SOIC - Lead Tips Only)
Operating Conditions
Supply Voltage, VDD and VCC . . . . . . . . . . . . . . . . . . +9.5V to +15V
Voltage on ALS, BLS . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +1.0V
Voltage on AHB, BHB . . . . . . . .VAHS, BHS +5V to VAHS, BHS +15V
Input Current, HDEL and LDEL . . . . . . . . . . . . . . . .-500µA to -50µA
Operating Ambient Temperature Range . . . . . . . . . .-40°C to +85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K, and
TA = +25°C, Unless Otherwise Specified
TJ = - 40°C
TO +125°C
TJ = +25°C
PARAMETERS
MIN
TYP
MAX
MIN
MAX
UNITS
IN- = 2.5V, Other Inputs = 0V
8
11
14
7
14
mA
Outputs switching f = 500kHz, No Load
9
12
15
8
15
mA
IN- = 2.5V, Other Inputs = 0V,
IALO = IBLO = 0
-
25
80
-
100
µA
f = 500kHz, No Load
1
1.25
2.0
0.8
3
mA
IN- = 2.5V, Other Inputs = 0V,
IAHO = IBHO = 0,
VDD = VCC =VAHB = VBHB = 10V
-50
-25
-11
-60
-10
µA
IAHBO,
IBHBO
f = 500kHz, No Load
0.62
1.2
1.5
0.5
1.9
mA
IHLK
VBHS = VAHS = 80V,
VAHB = VBHB = 93V
-
0.02
1.0
-
10
µA
IAHB = IAHB = 0, No Load
11.5
12.6
14.0
10.5
14.5
V
Over Common Mode Voltage Range
-10
0
+10
-15
+15
mV
IIB
0
0.5
2
0
4
µA
IOS
-1
0
+1
-2
+2
µA
CMVR
1
-
VDD
-1.5
1
VDD
-1.5
V
SYMBOL
TEST CONDITIONS
SUPPLY CURRENTS AND CHARGE PUMPS
VDD Quiescent Current
IDD
VDD Operating Current
IDDO
VCC Quiescent Current
ICC
VCC Operating Current
ICCO
AHB, BHB Quiescent Current Qpump Output Current
IAHB, IBHB
AHB, BHB Operating Current
AHS, BHS, AHB, BHB Leakage Current
VAHB VAHS
VBHB VBHS
AHB-AHS, BHB-BHS Qpump
Output Voltage
INPUT COMPARATOR PINS: IN+, IN-, OUT
Offset Voltage
VOS
Input Bias Current
Input Offset Current
Input Common Mode Voltage Range
4
HIP4080A
Electrical Specifications
VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K, and
TA = +25°C, Unless Otherwise Specified (Continued)
TJ = - 40°C
TO +125°C
TJ = +25°C
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNITS
10
25
-
10
-
V/mV
Voltage Gain
AVOL
OUT High Level Output Voltage
VOH
IN+ > IN-, IOH = -250µA
VDD
-0.4
-
-
VDD
- 0.5
-
V
OUT Low Level Output Voltage
VOL
IN+ < IN-, IOL = +250µA
-
-
0.4
-
0.5
V
Low Level Output Current
IOL
VOUT = 6V
6.5
14
19
6
20
mA
High Level Output Current
IOH
VOUT = 6V
-17
-10
-3
-20
-2.5
mA
Low Level Input Voltage
VIL
Full Operating Conditions
-
-
1.0
-
0.8
V
High Level Input Voltage
VIH
Full Operating Conditions
2.5
-
-
2.7
-
V
-
35
-
-
-
mV
INPUT PINS: DIS
Input Voltage Hysteresis
Low Level Input Current
IIL
VIN = 0V, Full Operating Conditions
-130
-100
-75
-135
-65
µA
High Level Input Current
IIH
VIN = 5V, Full Operating Conditions
-1
-
+1
-10
+10
µA
Low Level Input Voltage
VIL
Full Operating Conditions
-
-
1.0
-
0.8
V
High Level Input Voltage
VIH
Full Operating Conditions
2.5
-
-
2.7
-
V
-
35
-
-
-
mV
INPUT PINS: HEN
Input Voltage Hysteresis
Low Level Input Current
IIL
VIN = 0V, Full Operating Conditions
-260
-200
-150
-270
-130
µA
High Level Input Current
IIH
VIN = 5V, Full Operating Conditions
-1
-
+1
-10
+10
µA
IHDEL = ILDEL = -100µA
4.9
5.1
5.3
4.8
5.4
V
TURN-ON DELAY PINS: LDEL AND HDEL
LDEL, HDEL Voltage
VHDEL,V
GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, AND BHO
Low Level Output Voltage
VOL
IOUT = 100mA
0.7
0.85
1.0
0.5
1.1
V
High Level Output Voltage
VCC - VOH
IOUT = -100mA
0.8
0.95
1.1
0.5
1.2
V
Peak Pullup Current
IO+
VOUT = 0V
1.7
2.6
3.8
1.4
4.1
A
Peak Pulldown Current
IO-
VOUT = 12V
1.7
2.4
3.3
1.3
3.6
A
Under Voltage, Rising Threshold
UV+
8.1
8.8
9.4
8.0
9.5
V
Under Voltage, Falling Threshold
UV-
7.6
8.3
8.9
7.5
9.0
V
Under Voltage, Hysteresis
HYS
0.25
0.4
0.65
0.2
0.7
V
5
HIP4080A
Switching Specifications VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 10K,
CL = 1000pF, and TA = +25°C, Unless Otherwise Specified
TJ = - 40°C
TO +125°C
TJ = +25°C
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
MIN
MAX UNITS
Lower Turn-off Propagation Delay (IN+/IN- to ALO/BLO)
TLPHL
-
40
70
-
90
ns
Upper Turn-off Propagation Delay (IN+/IN- to AHO/BHO)
THPHL
-
50
80
-
110
ns
Lower Turn-on Propagation Delay (IN+/IN- to ALO/BLO)
TLPLH
-
40
70
-
90
ns
Upper Turn-on Propagation Delay (IN+/IN- to AHO/BHO)
THPLH
-
70
110
-
140
ns
Rise Time
TR
-
10
25
-
35
ns
Fall Time
TF
-
10
25
-
35
ns
Turn-on Input Pulse Width
TPWIN-ON
50
-
-
50
-
ns
Turn-off Input Pulse Width
TPWIN-OFF
40
-
-
40
-
ns
Disable Turn-off Propagation Delay
(DIS - Lower Outputs)
TDISLOW
-
45
75
-
95
ns
Disable Turn-off Propagation Delay
(DIS - Upper Outputs)
TDISHIGH
-
55
85
-
105
ns
TDLPLH
-
45
70
-
90
ns
TREF-PW
240
380
500
200
600
ns
TUEN
-
480
630
-
750
ns
Disable to Lower Turn-on Propagation Delay
(DIS - ALO and BLO)
Refresh Pulse Width (ALO and BLO)
Disable to Upper Enable (DIS - AHO and BHO)
HEN-AHO, BHO Turn-off, Propagation Delay
THEN-PHL
RHDEL = RLDEL = 10K
-
40
70
-
90
ns
HEN-AHO, BHO Turn-on, Propagation Delay
THEN-PLH
RHDEL = RLDEL = 10K
-
60
90
-
110
ns
TRUTH TABLE
INPUT
OUTPUT
IN+ > IN-
HEN
U/V
DIS
ALO
AHO
BLO
BHO
X
X
X
1
0
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
0
1
1
0
0
1
0
0
1
0
0
1
1
0
0
0
0
0
1
0
X
X
1
X
0
0
0
0
6
HIP4080A
Pin Descriptions
PIN
NUMBER
SYMBOL
1
BHB
B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap
diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30µA out of this pin to
maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.
2
HEN
High-side Enable input. Logic level input that when low overrides IN+/IN- (Pins 6 and 7) to put AHO and BHO drivers
(Pins 11 and 20) in low output state. When HEN is high AHO and BHO are controlled by IN+/IN- inputs. The pin can
be driven by signal levels of 0V to 15V (no greater than VDD).
3
DIS
DISable input. Logic level input that when taken high sets all four outputs low. DIS high overrides all other inputs.
When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of 0V to
15V (no greater than VDD).
4
VSS
Chip negative supply, generally will be ground.
5
OUT
OUTput of the input control comparator. This output can be used for feedback and hysteresis.
6
IN+
Noninverting input of control comparator. If IN+ is greater than IN- (Pin 7) then ALO and BHO are low level outputs
and BLO and AHO are high level outputs. If IN+ is less than IN- then ALO and BHO are high level outputs and BLO
and AHO are low level outputs. DIS (Pin 3) high level will override IN+/IN- control for all outputs. HEN (Pin 2) low level
will override IN+/IN- control of AHO and BHO. When switching in four quadrant mode, dead time in a half bridge leg
is controlled by HDEL and LDEL (Pins 8 and 9).
7
IN-
Inverting input of control comparator. See IN+ (Pin 6) description.
8
HDEL
High-side turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the turn-on delay of
both high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEL resistor guarantees no
shoot-through by delaying the turn-on of the high-side drivers. HDEL reference voltage is approximately 5.1V.
9
LDEL
Low-side turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the turn-on delay of
both low-side drivers. The high-side drivers turn-off with no adjustable delay, so the LDEL resistor guarantees no
shoot-through by delaying the turn-on of the low-side drivers. LDEL reference voltage is approximately 5.1V.
10
AHB
A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap
diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30µA out of this pin to
maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.
11
AHO
A High-side Output. Connect to gate of A High-side power MOSFET.
12
AHS
A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of
bootstrap capacitor to this pin.
13
ALO
A Low-side Output. Connect to gate of A Low-side power MOSFET.
14
ALS
A Low-side Source connection. Connect to source of A Low-side power MOSFET.
15
VCC
Positive supply to gate drivers. Must be same potential as VDD (Pin 16). Connect to anodes of two bootstrap diodes.
16
VDD
Positive supply to lower gate drivers. Must be same potential as VCC (Pin 15). De-couple this pin to VSS (Pin 4).
17
BLS
B Low-side Source connection. Connect to source of B Low-side power MOSFET.
18
BLO
B Low-side Output. Connect to gate of B Low-side power MOSFET.
19
BHS
B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of
bootstrap capacitor to this pin.
20
BHO
B High-side Output. Connect to gate of B High-side power MOSFET.
DESCRIPTION
7
HIP4080A
Timing Diagrams
THPHL
TDT
TLPLH
U/V = DIS 0
HEN 1
IN+ > INALO
AHO
BLO
BHO
TLPHL
THPLH
TR
TF
(10% - 90%) (90% - 10%)
TDT
FIGURE 1. BISTATE MODE
THEN-PHL
THEN-PLH
U/V = DIS 0
HEN
IN+ > INALO
AHO
BLO
BHO
FIGURE 2. HIGH SIDE CHOP MODE
TDLPLH
TDIS
TREF-PW
U/V or DIS
HEN
IN+ > INALO
AHO
BLO
BHO
TUEN
FIGURE 3. DISABLE FUNCTION
8
HIP4080A
Typical Performance Curves
VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL =
100K, and TA = +25°C, Unless Otherwise Specified
13
14.0
IDD SUPPLY CURRENT (mA)
IDD SUPPLY CURRENT (mA)
12.5
12.0
10.0
8.0
6.0
4.0
12.0
11.5
11.0
10.5
2.0
8
10
12
10
14
200
400
600
800
SWITCHING FREQUENCY (kHz)
VDD SUPPLY VOLTAGE (V)
FIGURE 4. QUIESCENT IDD SUPPLY CURRENT vs VDD
SUPPLY VOLTAGE
1000
FIGURE 5. IDDO NO-LOAD IDD SUPPLY CURRENT vs
FREQUENCY (kHz)
+125°C
20.0
ICC SUPPLY CURRENT (mA)
FLOATING SUPPLY BIAS CURRENT (mA)
5.0
15.0
10.0
5.0
0.0
+75°C
4.0
+25°C
0°C
3.0
-40°C
2.0
1.0
0.0
0
100
200 300
400
500
600
700
800
900 1000
0
100 200
SWITCHING FREQUENCY (kHz)
FIGURE 6. SIDE A, B FLOATING SUPPLY BIAS CURRENT vs
FREQUENCY (LOAD = 1000pF)
400
500
600
700
800
900 1000
FIGURE 7. ICCO, NO-LOAD ICC SUPPLY CURRENT vs
FREQUENCY (kHz) TEMPERATURE
2.5
COMPARATOR INPUT CURRENT (µA)
FLOATING SUPPLY BIAS CURRENT (mA)
300
SWITCHING FREQUENCY (kHz)
2
1.5
1
0.5
0
200
400
600
800
SWITCHING FREQUENCY (kHz)
1000
FIGURE 8. IAHB, IBHB NO-LOAD FLOATING SUPPLY BIAS
CURRENT vs FREQUENCY
9
1.0
0.5
-40
-20
0
20
40
60
80
100
JUNCTION TEMPERATURE (°C)
FIGURE 9. COMPARATOR INPUT CURRENT IL vs
TEMPERATURE AT VCM = 5V
120
HIP4080A
Typical Performance Curves
VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL =
100K, and TA = +25°C, Unless Otherwise Specified (Continued)
-180
LOW LEVEL INPUT CURRENT (µA)
LOW LEVEL INPUT CURRENT (µA)
-90
-100
-110
-120
-50
-25
0
25
50
75
100
-190
-200
-210
-220
-230
-40
125
-20
0
JUNCTION TEMPERATURE (°C)
60
80
100
120
FIGURE 11. HEN LOW LEVEL INPUT CURRENT IIL vs
TEMPERATURE
80
15.0
PROPAGATION DELAY (ns)
NO-LOAD FLOATING CHARGE PUMP VOLTAGE (V)
40
JUNCTION TEMPERATURE (°C)
FIGURE 10. DIS LOW LEVEL INPUT CURRENT IIL vs
TEMPERATURE
14.0
13.0
12.0
11.0
70
60
50
40
30
10.0
-40
-20
0
20
40
60
80
100
-40
120
-20
JUNCTION TEMPERATURE (°C)
20
40
60
80
100
120
FIGURE 13. UPPER DISABLE TURN-OFF PROPAGATION
DELAY TDISHIGH vs TEMPERATURE
80
PROPAGATION DELAY (ns)
525
500
475
450
425
-50
0
JUNCTION TEMPERATURE (°C)
FIGURE 12. AHB - AHS, BHB - BHS NO-LOAD CHARGE PUMP
VOLTAGE vs TEMPERATURE
PROPAGATION DELAY (ns)
20
70
60
50
40
30
-25
0
25
50
75
100
125 150
JUNCTION TEMPERATURE (°C)
FIGURE 14. DISABLE TO UPPER ENABLE TUEN
PROPAGATION DELAY vs TEMPERATURE
10
-40
-20
0
20
40
60
80
100
120
JUNCTION TEMPERATURE (°C)
FIGURE 15. LOWER DISABLE TURN-OFF PROPAGATION
DELAY TDISLOW vs TEMPERATURE
HIP4080A
Typical Performance Curves
VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL =
10K, and TA = +25°C, Unless Otherwise Specified
80
70
PROPAGATION DELAY (ns)
REFRESH PULSE WIDTH (ns)
450
425
400
375
60
50
40
30
350
-50
-25
0
25
50
75
100
20
-40
125 150
-20
JUNCTION TEMPERATURE (°C)
40
60
80
100
120
FIGURE 17. DISABLE TO LOWER ENABLE TDLPLH
PROPAGATION DELAY vs TEMPERATURE
90.0
PROPAGATION DELAY (ns)
90.0
PROPAGATION DELAY (ns)
20
JUNCTION TEMPERATURE (°C)
FIGURE 16. TREF-PW REFRESH PULSE WIDTH vs
TEMPERATURE
80.0
70.0
60.0
50.0
80.0
70.0
60.0
50.0
40.0
40.0
-40
-20
0
20
40
60
80
100
JUNCTION TEMPERATURE (°C)
-40
120
0
20
40
60
80
100
120
FIGURE 19. UPPER TURN-ON PROPAGATION DELAY THPLH
vs TEMPERATURE
90.0
PROPAGATION DELAY (ns)
90.0
80.0
70.0
60.0
50.0
80.0
70.0
60.0
50.0
40.0
40.0
-40
-20
JUNCTION TEMPERATURE (°C)
FIGURE 18. UPPER TURN-OFF PROPAGATION DELAY THPHL
vs TEMPERATURE
PROPAGATION DELAY (ns)
0
-20
0
20
40
60
80
100
JUNCTION TEMPERATURE (°C)
120
FIGURE 20. LOWER TURN-OFF PROPAGATION DELAY TLPHL
vs TEMPERATURE
11
-40
-20
0
20
40
60
80
100
JUNCTION TEMPERATURE (°C)
120
FIGURE 21. LOWER TURN-ON PROPAGATION DELAY TLPLH
vs TEMPERATURE
HIP4080A
Typical Performance Curves
VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL =
13.5
13.5
12.5
12.5
TURN-ON RISE TIME (ns)
GATE DRIVE FALL TIME (ns)
100K, and TA = +25°C, Unless Otherwise Specified
11.5
10.5
9.5
8.5
-40
-20
0
20
40
60
80
100
11.5
10.5
9.5
8.5
-40
120
-20
0
JUNCTION TEMPERATURE (°C)
FIGURE 22. GATE DRIVE FALL TIME TF vs TEMPERATURE
60
80
100
120
1500
1250
5.5
VCC - VOH (mV)
HDEL, LDEL INPUT VOLTAGE (V)
40
FIGURE 23. GATE DRIVE RISE TIME TR vs TEMPERATURE
6.0
5.0
1000
750
-40°C
0°C
500
4.5
+25°C
250
4.0
-40
-20
0
20
40
60
80
100
+75°C
+125°C
0
10
120
12
JUNCTION TEMPERATURE (°C)
FIGURE 25. HIGH LEVEL OUTPUT VOLTAGE, VCC - VOH vs
BIAS SUPPLY AND TEMPERATURE AT 100µA
3.5
GATE DRIVE SINK CURRENT (A)
1500
1250
1000
750
-40°C
500
0°C
+25°C
250
0
14
BIAS SUPPLY VOLTAGE (V)
FIGURE 24. VLDEL, VHDEL VOLTAGE vs TEMPERATURE
VOL (mV)
20
JUNCTION TEMPERATURE (°C)
+75°C
+125°C
10
3.0
2.5
2.0
1.5
1.0
0.5
0.0
12
BIAS SUPPLY VOLTAGE (V)
14
FIGURE 26. LOW LEVEL OUTPUT VOLTAGE VOL vs BIAS
SUPPLY AND TEMPERATURE AT 100µA
12
6
7
8
9
10
11
12
13
14
15
16
VCC, VDD, VAHG, VBHB (V)
FIGURE 27. PEAK PULLDOWN CURRENT IO- BIAS SUPPLY
VOLTAGE
HIP4080A
Typical Performance Curves
VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL =
100K, and TA = +25°C, Unless Otherwise Specified (Continued)
500
LOW VOLTAGE BIAS CURRENT (mA)
GATE DRIVE SINK CURRENT (A)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
6
7
8
9
10
11
12
13
14
15
200
100
10,000
50
3,000
20
1,000
10
100
5
2
1
0.5
0.2
0.1
16
1
2
VCC, VDD, VABH, VBHB (V)
FIGURE 28. PEAK PULLUP CURRENT IO+ vs SUPPLY
VOLTAGE
10
20
50
100
200
500 1000
FIGURE 29. LOW VOLTAGE BIAS CURRENT IDD AND ICC
(LESS QUIESCENT COMPONENT) vs
FREQUENCY AND GATE LOAD CAPACITANCE
9
BIAS SUPPLY VOLTAGE, VDD (V)
1000
500
LEVEL-SHIFT CURRENT (µA)
5
SWITCHING FREQUENCY (kHz)
200
100
50
20
UV+
8.8
8.6
UV8.4
8.2
10
10
20
50
100
200
500
1000
50
25
0
25
SWITCHING FREQUENCY (kHz)
FIGURE 30. HIGH VOLTAGE LEVEL-SHIFT CURRENT vs
FREQUENCY AND BUS VOLTAGE
DEAD-TIME (ns)
120
90
60
30
10
50
100
150
200
HDEL/LDEL RESISTANCE (kΩ)
250
FIGURE 32. MINIMUM DEAD-TIME vs DEL RESISTANCE
13
75
100
125
150
FIGURE 31. UNDERVOLTAGE LOCKOUT vs TEMPERATURE
150
0
50
TEMPERATURE (°C)
IN2 IN1
POWER SECTION
+12V
14
B+
1
U2
2
2
R29
JMPR1
+
C6
JMPR5
CONTROL LOGIC
SECTION
HIP4080A/81A
U1
OUT/BLI
JMPR2
4 V
SS
5 OUT/BLI
IN+/ALI
U2
6
JMPR3
HEN/BHI
CD4069UB
11
U2
JMPR4
3
IN-/AHI
3
2
2
CW
CD4069UB
9 LDEL
10 AHB
R34
R33
10
C8
Q1
3
C4
2
R22
1
BLS 17
16
V
DD
1
CW
1
AHS
AHO
Q3
3
L1
AO
2
+12V
R23
6 IN+/ALI V
15
CC
7 IN-/AHI
ALS 14
8 HDEL ALO
13
CD4069UB
5
CR2
1
1
Q2
L2
C1
BO
C2
3
2
12
R24
11
1
CR1
Q4
3
C3
CX
CY
R30
R31
C5
COM
ALS
BLS
NOTES:
1. DEVICE CD4069UB PIN 7 = COM. PIN 14 = +12V.
2. COMPONENTS L1, L2, C1, C2, CX, CY, R30, R31, ARE NOT
SUPPLIED. REFER TO APPLICATION NOTE FOR HELP IN
DETERMINING JMPR1 - JMPR4 JUMPER LOCATIONS.
FIGURE 33. HIP4080A EVALUATION PC BOARD SCHEMATIC
HIP4080A
U2
12
R21
1 BHB
BHO 20
2 HEN/BHI BHS 19
3 DIS
BLO 18
CD4069UB
13
DRIVER SECTION
C1
R26
COM
C8
C6
R28
JMPR5
R29
C7
B+
+
CR2
R32
+
R27
15
+12V
GND
AO
Q1
C4
BHO
U1
Q3
1
R22
1
JMPR1
JMPR2
JMPR3
JMPR4
I
O
IN2
ALS
ALO
C2
Q2
R23
Q4
1
1
R21
CY
CX
FIGURE 33. HIP4080A EVALUATION BOARD SILKSCREEN
R31
R34
R30
CR1
R33
BLS
C3
C5
ALS
AHO
LDEL
HDEL
O
L2
L1
BLO
BLS
BO
HIP4080A
IN1
HIP4080/81
R24
DIS
U2
HIP4080A
Dual-In-Line Plastic Packages (PDIP)
E20.3 (JEDEC MS-001-AD ISSUE D)
N
20 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
1 2 3
INCHES
N/2
-B-
-AD
E
BASE
PLANE
-C-
A2
SEATING
PLANE
A
L
D1
e
B1
D1
A1
eC
B
0.010 (0.25) M
C A B S
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.210
-
5.33
4
A1
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
B
0.014
0.022
0.356
0.558
-
C
L
B1
0.045
0.070
1.55
1.77
8
eA
C
0.008
0.014
C
D
0.980
1.060
eB
NOTES:
0.005
-
0.13
-
5
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
0.100 BSC
eA
0.300 BSC
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
eB
-
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication No. 95.
L
0.115
N
7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
16
5
E
1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
0.355
26.9
D1
e
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
0.204
24.89
20
2.54 BSC
7.62 BSC
0.430
-
0.150
2.93
20
6
10.92
7
3.81
4
9
Rev. 0 12/93
HIP4080A
Small Outline Plastic Packages (SOIC)
M20.3 (JEDEC MS-013-AC ISSUE C)
20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
N
INCHES
INDEX
AREA
0.25(0.010) M
H
B M
E
-B1
2
3
L
SEATING PLANE
-A-
h x 45o
A
D
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
A1
0.0040
0.0118
0.10
0.30
-
B
0.014
0.019
0.35
0.49
9
C
0.0091
0.0125
0.23
0.32
-
D
0.4961
0.5118
12.60
13.00
3
E
0.2914
0.2992
7.40
7.60
4
e
-C-
e
µα
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
B S
MILLIMETERS
0.050 BSC
1.27 BSC
-
H
0.394
0.419
10.00
10.65
-
h
0.010
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
N
α
20
0o
20
8o
0o
7
8o
Rev. 1 1/02
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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17
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