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1-888-IN
Triple Output, Low-Noise LDO Regulator
with Integrated Reset Circuit
The ISL6412 is an ultra low noise triple output LDO regulator
with microprocessor reset circuit and is optimized for
powering wireless chip sets. The IC accepts an input voltage
range of 3.0V to 3.6V and provides three regulated output
voltages: 1.8V (LDO1), 2.8V (LDO2), and another ultra-clean
2.8V (LDO3). On chip logic provides sequencing between
LDO1 and LDO2 for the BBP/MAC and the I/O supply
voltage outputs. LDO3 features ultra low noise that does not
typically exceed 30µV RMS to aid VCO stability. High
integration and the thin Quad Flat No-lead (QFN) package
makes the ISL6412 an ideal choice to power many of today’s
small form factor industry standard wireless cards such as
PCMCIA, mini-PCI and Cardbus-32.
The ISL6412 uses an internal PMOS transistor as the pass
device. The ISL6412 also integrates a reset function, which
eliminates the need for the additional reset IC required in
WLAN applications. The IC asserts a RESET signal
whenever the VIN supply voltage drops below a preset
threshold, keeping it asserted for a time set by a capacitor to
GND after VIN has risen above the reset threshold. FAULT1
indicates the loss of regulation on LDO1.
PART
MARKING
TEMP.
RANGE
(°C)
PACKAGE
PKG.
DWG. #
ISL6412IR
ISL6412IR
-40 to +85 16 Ld 4x4 QFN L16.4x4
ISL6412IR-TK
ISL6412IR
-40 to +85 16 Ld 4x4 QFN L16.4x4
ISL6412IR-T5K ISL6412IR
-40 to +85 16 Ld 4x4 QFN L16.4x4
ISL6412IRZ
(Note 2)
-40 to +85 16 Ld 4x4 QFN L16.4x4
(Pb-free)
6412IRZ
ISL6412IRZ-TK 6412IRZ
(Notes 1, 2)
FN9067.1
Features
• Small DC/DC Converter Size
- Three LDOs and Reset Circuitry in a Low-Profile
4x4mm QFN Package
• High Output Current
- LDO1, 1.8V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330mA
- LDO2, 2.8V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225mA
- LDO3, 2.8V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125mA
• Ultra-Low Dropout Voltage
- LDO2, 2.8V. . . . . . . . . . . . . . . . 125mV (typ.) at 225mA
- LDO3, 2.8V. . . . . . . . . . . . . . . . 100mV (typ.) at 125mA
• Ultra-Low Output Voltage Noise
- <30VRMS (typ.) for LDO3 (VCO Supply)
• Stable with Small Ceramic Output Capacitors
• Extensive Protection and Monitoring Features
- Over current protection
- Short circuit protection
- Thermal shutdown
- FAULT indicator
• Logic-Controlled Shutdown Pin
• Integrated Microprocessor Reset Circuit
- Programmable Reset Delay
Ordering Information
PART
NUMBER
ISL6412
-40 to +85 16 Ld 4x4 QFN L16.4x4
(Pb-free)
• Proven Reference Design for a Total WLAN System
Solution
• QFN Package
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Product Outline
- Near Chip-Scale Package Footprint Improves PCB
Efficiency and Is Thinner in Profile
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• PRISM® 3 Chipsets – ISL37106P
NOTES:
1. Tape and Reel available. Add “-T” suffix for Tape and Reel Packing
Option
2. Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
1
• WLAN Cards
- PCMCIA, Cardbus32, MiniPCI Cards
- Compact Flash Cards
• Liberty Chipset
• Hand-Held Instruments
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004, 2007. All Rights Reserved. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL6412
Pinout
NC
FAULT1
VIN
VIN
ISL6412 (16 LD QFN)
TOP VIEW
16
15
14
13
CT
2
11
CC1
SHDN
3
10
OUT2
NC
4
9
CC2
5
6
7
8
GND
OUT1
GND3
12
CC3
1
OUT3
RESET
Typical Application Schematic
+3.3V
VIN
RESET
CT
SHDN
NC
14
VIN
13
VIN
ISL6412
+1.8V
VOUT1
12
OUT1
11
CC1
10
OUT2
9
CC2
OUT3
CC3
GND3
GND
C8
0.01F
1
2
3
4
FAULT1
NC
16
15
+ C4
3.3F
+2.8V
VOUT2
C6
0.033F
C2
3.3F
C1
3.3F
5
6
7
8
C5
0.033F
+2.8V
VOUT3
C3
3.3F
C7
0.033F
Typical Bill Of Materials
REFERENCE
DESIGNATOR
VALUE
PACKAGE
MANUFACTURER
MANUFACTURER’S
PART NUMBER
C1, C2, C3, C4
3.3µF, X7R
1206
TDK
C3216X7R1A106M
C5, C6, C7
0.033µF, X7R
0603
TDK/ANY
C1608X7R1A333K
C8
0.01µF, X7R
0603
TDK/ANY
C1608X7R1A103K
U1
ISL6412IR
QFN16
Intersil
ISL6412IR
2
FN9067.1
March 20, 2007
ISL6412
Functional Block Diagram
BAND GAP REF.
1.2V
+
-
FAULT1
13
VIN
14
OUT1
12
CC1
11
LDO1
VREF
15
VIN
WINDOW
COMP
EN
EN
THERMAL SHUTDOWN
150°C
LDO2
VIN
CONTROL
LOGIC
OUT2
VREF
EN
EN
EN
OUT2
CC2
CC2
3
10
9
SHDN
LDO3
2
VIN
CT
RESET
VREF
EN
1
RESET
OUT3
EN
OUT3
CC3
CC3
8
GND
3
5
GND3
6
7
FN9067.1
March 20, 2007
ISL6412
Absolute Maximum Ratings
Thermal Information
VIN, SHDN to GND/GND3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V
SET, CC, FAULT to GND/GND3 . . . . . . . . . . . . . . . . . -0.3V to 7.0V
Output Current (Continuous)
LDO1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330mA
LDO2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225mA
LDO3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125mA
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance (Typical)
JA (°C/W)
JC (°C/W)
QFN Package (Notes 3, 4) . . . . . . . .
46
9
Maximum Junction Temperature (Plastic Package) -55°C to +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C
Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
4. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
VIN = +3.3V, Compensation Capacitor = 33nF, TA = +25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
3.0
3.3
3.6
V
GENERAL SPECIFICATIONS
VIN Voltage Range
Operating Supply Current
IOUT = 0mA
-
830
1125
A
Shutdown Supply Current
SHDN = GND
-
5
10
A
SHDN Input Threshold
VIH, VIN = 3V to 3.6V
2.0
-
-
V
VIL, VIN = 3V to 3.6V
-
-
0.4
V
145
150
160
°C
-
20
-
°C
-
120
-
s
2.4
2.45
2.6
V
-
1.8
-
V
Thermal Shutdown Temperature (Note 7)
Thermal Shutdown Hysteresis (Note 7)
Start-up Time (Note 7)
COUT = 10F, VOUT = 90% of final
value
Input Undervoltage Lockout
Rising 75mV Hysteresis
LDO1 SPECIFICATIONS
Output Voltage (VOUT1)
Output Voltage Initial Accuracy
IOUT = 10mA, TA = -40°C to 85°C
-2.0
-
2.0
%
Line Regulation
VIN = 3.0V to 3.6V, IOUT = 10mA
-0.15
0.0
0.15
%/V
Load Regulation
IOUT = 10mA to 330mA
-1.5
-
1.5
%
Maximum Output Current (IOUT1) (Note 7)
330
-
-
mA
Output Current Limit (Note 7)
500
600
1105
mA
-
115
-
VRMS
-
2.8
-
V
Output Voltage Noise (Note 7)
10Hz < f < 100kHz, COUT = 4.7F,
IOUT = 50mA
LDO2 SPECIFICATIONS
Output Voltage (VOUT2)
Output Voltage Accuracy
IOUT = 10mA, TA = -40°C to 85°C
-2.0
-
2.0
%
Maximum Output Current (IOUT2) (Note 7)
VIN = 3.6V
225
-
-
mA
330
-
900
mA
-
125
160
mV
-0.15
0.0
0.15
%/V
-
0.2
1.0
%
Output Current Limit (Note 7)
Dropout Voltage (Notes 5, 7)
IOUT = 225mA
Line Regulation
VIN = 3.0V to 3.6V, IOUT = 10mA
Load Regulation
IOUT = 10mA to 225mA
4
FN9067.1
March 20, 2007
ISL6412
Electrical Specifications
VIN = +3.3V, Compensation Capacitor = 33nF, TA = +25°C, unless otherwise noted. (Continued)
PARAMETER
TEST CONDITIONS
Output Voltage Noise (Note 7)
MIN
TYP
MAX
UNITS
COUT = 2.2F
-
65
-
VRMS
COUT = 10F
-
60
-
VRMS
-
2.8
-
V
10Hz < f < 100kHz, IOUT = 10mA
LDO3 SPECIFICATIONS
Output Voltage (VOUT3)
Output Voltage Accuracy
IOUT = 10mA, TA = -40°C to +85°C
-2.0
-
2.0
%
Maximum Output Current (IOUT3) (Note 7)
VIN = 3.6V
225
-
-
mA
300
450
840
mA
-
100
160
mV
-0.15
0.0
0.15
%/V
-
0.2
1.0
%
COUT = 2.2F
-
30
-
VRMS
COUT = 10F
-
20
-
VRMS
2.564
2.630
2.66
V
6.3
-
-
mV
-
20
-
s
50
-
-
ms
Output Current Limit (Note 7)
Dropout Voltage (Notes 5, 7)
IOUT = 125mA
Line Regulation
VIN = 3.0V to 3.6V, IOUT = 10mA
Load Regulation
IOUT = 10mA to 125mA
Output Voltage Noise (Note 7)
10Hz < f < 100kHz, IOUT = 10mA
RESET BLOCK SPECIFICATIONS
Reset Threshold
Reset Threshold Hysteresis (Note 7)
VIN to Reset Delay
VCC = VTH to VTH - 100mV
RESET Active Timeout Period (Notes 6, 7)
CT = 0.01µF
FAULT1
Rising Threshold
% of VOUT
+5.5
+8.0
+10.5
%
Falling Threshold
% of VOUT
-10.5
-8.0
-5.5
%
NOTES:
5. The dropout voltage is defined as VIN - VOUT, when VOUT is 50mV below the value of VOUT for VIN = VOUT + 0.5V.
6. The RESET time is linear with CT at a slope of ~5ms/nF. Thus, at 10nF (0.01F) the RESET time is 50ms.
7. Guaranteed by design, not production tested.
Typical Performance Curves
The test conditions for the Typical Operating Performance are: VIN = 3.3V, TA = +25°C,
Unless Otherwise Noted
SHDN
1V/DIV
SHDN
1V/DIV
VOUT3
1V/DIV
VOUT2
1V/DIV
VOUT2
1V/DIV
VOUT3
1V/DIV
VOUT1
1V/DIV
VOUT1
1V/DIV
100µs/DIV
FIGURE 1. START-UP SEQUENCE
5
100µs/DIV
FIGURE 2. SHUTDOWN SEQUENCE
FN9067.1
March 20, 2007
ISL6412
Typical Performance Curves
The test conditions for the Typical Operating Performance are: VIN = 3.3V, TA = +25°C,
Unless Otherwise Noted (Continued)
SHDN
2V/DIV
VOUT1
50mV/DIV
VOUT1
2V/DIV
RESET
2V/DIV
IOUT1
200mA/DIV
FAULT
2V/DIV
20ms/DIV
1ms/DIV
FIGURE 3. SHUTDOWN, FAULT, and RESET OPERATION
FIGURE 4. LDO1 TRANSIENT RESPONSE (10mA to 330mA)
VOUT2
100mV/DIV
VOUT3
100mV/DIV
IOUT2
100mA/DIV
IOUT3
50mA/DIV
1ms/DIV
1ms/DIV
FIGURE 5. LDO2 TRANSIENT RESPONSE (10mA to 200mA)
FIGURE 6. LDO3 TRANSIENT RESPONSE (10mA to 100mA)
VIN
0.5V/DIV
VIN
0.5V/DIV
RESET
0.5V/DIV
RESET
0.5V/DIV
CT
0.5V/DIV
CT
0.5V/DIV
20ms/DIV
FIGURE 7. RESET DELAY DURING START-UP (CT = 0.01µF)
6
100ms/DIV
FIGURE 8. RESET DELAY DURING START-UP (CT = 0.1µF)
FN9067.1
March 20, 2007
ISL6412
Typical Performance Curves
The test conditions for the Typical Operating Performance are: VIN = 3.3V, TA = +25°C,
Unless Otherwise Noted (Continued)
-10
PSRR (dB)
-20
FAULT
1V/DIV
-30
-40
-50
-60
VOUT1/2/3
1V/DIV
10
500ms/DIV
100
1k
10k
100k
1M
FREQUENCY (A)
FIGURE 9. THERMAL SHUTDOWN OPERATION
VIN
0.5V/DIV
FIGURE 10. LDO1 POWER SUPPLY REJECTION
(IOUT1 = 100mA, COUT = 10µF MLCC)
VIN = 2.7V
VOUT1
0.5V/DIV
FAULT
0.5V/DIV
FIGURE 11. VOUT1 REGULATION DOWN TO VIN = 2.7V; FAULT MONITORS VOUT1 ONLY
Pin Descriptions
OUT1 - This pin is the output for LDO1. Bypass with a
minimum of 2.2µF, low ESR capacitor to GND for stable
operation.
VIN - Supply input pins. Connect to input power source.
Bypass with a minimum 2.2F capacitor to GND. Both VIN
pins must be tied together on the PC board, close to the IC.
GND - Ground for LDO1 and LDO2.
CC1 - Compensation Capacitor for LDO1. Connect a
0.033µF capacitor from CC1 to GND.
SHDN - Shutdown input for all LDOs. Connect to VIN for
normal operation. Drive this pin LOW to turn off all LDOs.
7
OUT2 - This pin is the output for LDO2. Bypass with a
minimum of 2.2µF, low ESR capacitor to GND for stable
operation.
CT - Timing pin for the RESET circuit pulse width.
CC2 - Compensation capacitor for LDO2. Connect a
0.033µF capacitor from CC2 to GND.
OUT3 - This pin is output for LDO3. Bypass with a minimum
of 2.2µF, low ESR capacitor to GND3 for stable operation.
GND3 - Ground pin for LDO3.
CC3 - Compensation capacitor for LDO3. Connect a
0.033µF capacitor from CC3 to GND3.
FAULT1 - This is the power good indicator for LDO1. When
the 1.8V output is out of regulation this pin goes LOW. This
FN9067.1
March 20, 2007
ISL6412
pin also goes LOW during thermal shutdown or an
overcurrent event on LDO1. Connect this pin to GND, if
unused.
The voltage at the CT pin is compared to the 1.2V bandgap
voltage. The charging of the CT capacitor behaves like an
RC network and the RESET delay can be approximated by:
RESET - This pin is the active-LOW output of the push-pull
output stage of the integrated reset supervisory circuit. The
reset circuit monitors VIN and asserts a RESET output at this
pin, if VIN falls below the RESET threshold. The RESET
output remains LOW, while the VIN pin voltage is below the
reset threshold, and for at least 25ms, after VIN rises above
the RESET threshold.
Td = -R*C*ln(1-1.2V/VIN)
Where C is the capacitor at CT, and R is 11.1M for
VIN = 3.3V. With no capacitor on the CT pin the RESET
delay will be close to zero. Figure 12 shows the RESET
delay vs CT capacitance.
500
Functional Description
The 1.2V band gap reference is connected to the error
amplifier’s inverting input. The error amplifier compares this
reference to the selected feedback voltage and amplifies the
difference. The MOSFET driver reads the error signal and
applies the appropriate drive to the P-Channel pass transistor.
If the feedback voltage is lower then the reference voltage, the
pass transistor gate is pulled lower, allowing more current to
pass and increasing the output voltage. If the feedback
voltage is higher then the reference voltage, the pass
transistor gate is driven higher, allowing less current to pass to
the output. The output voltage is fed back through an internal
resistor divider connected to OUT1/OUT2/OUT3 pins.
Additional blocks include an output overcurrent protection,
thermal sensor, fault detector, RESET function and
shutdown logic.
Internal P-Channel Pass Transistors
The ISL6412 features a typical 0.5 rDS(ON) P-channel
MOSFET pass transistors. This provides several advantages
over similar designs using PNP bipolar pass transistors. The
P-Channel MOSFET requires no base drive, which reduces
quiescent current considerably. PNP based regulators waste
considerable current in dropout when the pass transistor
saturates. They also use high base drive currents under
large loads. The ISL6412 does not suffer from these
problems.
DELAY (ms)
The ISL6412 is a 3-in-1 multi-output, low dropout, regulator
designed for wireless chipset power applications. It supplies
three fixed output voltages 1.8V, 2.8V and 2.8V. Each LDO
consists of a 1.2V reference, error amplifier, MOSFET driver,
P-Channel pass transistor, dual-mode comparator and
internal feedback voltage divider.
400
300
200
100
0
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0
CT (µF)
FIGURE 12. RESET DELAY vs CT CAPACITANCE
Output Voltages
The ISL6412 provides fixed output voltages for use in
Wireless Chipset applications. Internal trimmed resistor
networks set the typical output voltages as shown here:
VOUT1 = 1.8V; VOUT2 = 2.8V; VOUT3 = 2.8V.
Shutdown
Pulling the SHDN pin LOW puts the complete chip into
shutdown mode, and supply current drops to 5A typical.
This input has an internal pull-up resistor, so that in normal
operation the outputs are always enabled; external pull-up
resistors are not required.
Current Limit
The ISL6412 monitors and controls the pass transistor’s
gate voltage to limit the output current. The current limit for
LDO1 is 500mA, LDO2 is 330mA and LDO3 is 300mA. The
output can be shorted to ground without damaging the part
due to the current limit and thermal protection features.
Integrated Reset for MAC/Baseband Processors
The ISL6412 includes a microprocessor supervisory block.
This block eliminates the extra reset IC and external
components needed in wireless chipset applications. This
block performs a single function; it asserts a RESET signal
whenever the VIN supply voltage decreases below a preset
threshold, keeping it asserted for a programmable time (set
by external capacitor CT) after the VIN pin voltage has risen
above the reset threshold. The reset threshold for the
ISL6412 is 2.63V typical.
8
FN9067.1
March 20, 2007
ISL6412
Thermal Overload Protection
Thermal overload protection limits total power dissipation in
the ISL6412. When the junction temperature (TJ) exceeds
+150°C, the thermal sensor sends a signal to the shutdown
logic, turning off the pass transistor and allowing the IC to
cool. The pass transistor turns on again after the IC’s
junction temperature typically cools by 20°C, resulting in a
pulsed output during continuous thermal overload
conditions. Thermal overload protection protects the
ISL6412 against fault conditions. For continuous operation,
do not exceed the absolute maximum junction temperature
rating of +150°C.
FAULT Functionality
TABLE 1.
EVENT
FAULT1
Below UVLO threshold
L
VOUT1 = 1.8V ±8% typ
VOUT2/VOUT3 not in regulation
H
VOUT1 not in regulation
VOUT2 and VOUT3 are in regulation
L
Thermal Shutdown
L
Normal Shutdown with SHDN pin
L
Operating Region and Power Dissipation
Overcurrent only on LDO1
L
The maximum power dissipation of ISL6412 depends on the
thermal resistance of the IC package and circuit board, the
temperature difference between the die junction and ambient
air, and the rate of air flow. The power dissipated in the
device is:
Overcurrent only on LDO2/LDO3
H
PT = P1 + P2 + P3, where
P1 = IOUT1 (VIN – VOUT1)
P2 = IOUT2 (VIN – VOUT2)
P3 = IOUT3 (VIN- VOUT3)
The maximum power dissipation is:
Pmax = (Tjmax – TA)/JA
Where Tjmax = +150°C, TA = ambient temperature, and JA
is the thermal resistance from the junction to the surrounding
environment.
The ISL6412 package features an exposed thermal pad on
its underside. This pad lowers the thermal resistance of the
package by providing a direct heat conduction path from the
die to the PC board. Additionally, the ISL6412’s ground
(GND/GND3) performs the dual function of providing an
electrical connection to system ground and channeling heat
away. Connect the exposed backside pad and GND to the
system ground using a large pad or ground plane, or through
multiple vias to the ground plane layer.
Integrator Circuitry
The ISL6412 uses an external 33nF compensation capacitor
for minimizing load and line regulation errors and for
lowering output noise. When the output voltage shifts due to
varying load current or input voltage, the integrator capacitor
voltage is raised or lowered to compensate for the
systematic offset at the error amplifier. Compensation is
limited to ±5% to minimize transient overshoot when the
device goes out of dropout, current limit, or thermal
shutdown.
9
Applications Information
Capacitor Selection and Regulator Stability
Capacitors are required at the ISL6412’s input and output for
stable operation over the entire load range and the full
temperature range. Use >1µF capacitor at the input of
ISL6412. The input capacitor lowers the source impedance
of the input supply. Larger capacitor values and lower ESR
provides better PSRR and line transient response. The input
capacitor must be located at a distance of not more then 0.5
inches from the VIN pins of the IC and returned to a clean
analog ground. Any good quality ceramic or tantalum can be
used as an input capacitor.
The output capacitor must meet the requirements of
minimum amount of capacitance and ESR for all three
LDO’s. The ISL6412 is specifically designed to work with
small ceramic output capacitors. The output capacitor’s ESR
affects stability and output noise. Use an output capacitor
with an ESR of 50m or less to insure stability and optimum
transient response. For stable operation, a ceramic
capacitor, with a minimum value of 3.3F, is recommended
for VOUT1 for 300mA output current, and 2.2F is
recommended for VOUT2 and VOUT3 each at 200mA load
current. There is no upper limit to the output capacitor value.
Larger capacitor can reduce noise and improve load
transient response, stability and PSRR. Higher value of
output capacitor (10µF) is recommended for LDO3 when
used to power VCO circuitry in wireless chipsets. The output
capacitor should be located very close to VOUT pins to
minimize impact of PC board inductances and the other end
of the capacitor should be returned to a clean analog
ground.
Input-Output (Dropout) Voltage
A regulator’s minimum input-output voltage differential (or
dropout voltage) determines the lowest usable supply
voltage. Because the ISL6412 uses a P-channel MOSFET
pass transistor, its dropout voltage is a function of rDS(ON)
(typically 0.5) multiplied by the load current.
FN9067.1
March 20, 2007
ISL6412
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L16.4x4
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220-VGGC ISSUE C)
MILLIMETERS
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
0.80
0.90
1.00
-
A1
-
-
0.05
-
A2
-
-
1.00
9
0.35
5, 8
A3
b
0.20 REF
0.23
0.28
9
D
4.00 BSC
-
D1
3.75 BSC
9
D2
1.95
E
E1
E2
2.10
2.25
7, 8
4.00 BSC
-
3.75 BSC
1.95
e
2.10
9
2.25
7, 8
-
0.65 BSC
-
k
0.25
-
-
L
0.50
0.60
0.75
8
L1
-
-
0.15
10
N
16
2
Nd
4
3
Ne
4
3
P
-
-
0.60

-
-
12
9
9
Rev. 5 5/04
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P &  are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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10
FN9067.1
March 20, 2007
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