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Sheet
November 3, 2004
TERSIL
1-888-IN
Triple Output, Low-Noise LDO Regulator
with Integrated Reset Circuit
The ISL6416 is an ultra low noise triple output LDO regulator
with microprocessor reset circuit and is optimized for
powering wireless chip sets. The IC accepts an input voltage
range of 3.0V to 3.6V and provides three regulated output
voltages: 1.8V (LDO1), 2.8V (LDO2), and another ultra-clean
2.8V (LDO3). On chip logic provides sequencing between
LDO1 and LDO2 for the BBP/MAC and the I/O supply
voltage outputs. LDO3 features ultra low noise that does not
exceed 30µVRMS (typical) to aid VCO stability. High
integration makes the ISL6416 an ideal choice to power
many of today’s small form factor industry standard wireless
cards such as PCMCIA, mini-PCI and Cardbus-32.
The ISL6416 uses an internal PMOS transistor as the pass
device. The ISL6416 also integrates a reset function, which
eliminates the need for the additional reset IC required in
WLAN applications. The IC asserts a RESET signal
whenever the VIN supply voltage drops below a preset
threshold, keeping it asserted for at least 25ms after Vin has
risen above the reset threshold. FAULT indicates the loss of
regulation on LDO1.
TEMP.
RANGE (°C)
FN9193.0
Features
• Three LDOs and a RESET circuit
• High Output Current
- LDO1, 1.8V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330mA
- LDO2, 2.8V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225mA
- LDO3, 2.8V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125mA
• Low Output Voltage Noise
- <30µVRMS (typical) for LDO3 (VCO Supply)
• Stable with Small Ceramic Output Capacitors
• Extensive Protection and Monitoring Features
- Overcurrent protection
- Short circuit protection
- Thermal shutdown
- FAULT indicator
• Logic-Controlled Shutdown Pin
• Integrated Microprocessor Reset Circuit
- Programmable Reset Delay
• Proven Reference Design for a Total WLAN System
Solution
• Pb-Free Available (RoHS Compliant)
Ordering Information
PART NUMBER
ISL6416
PACKAGE
PKG.
DWG. #
ISL6416IA
-40 to +85
16 Ld QSOP
M16.15A
ISL6416IAZ (Note 1)
-40 to +85
16 Ld QSOP
(Pb-free)
M16.15A
Applications
• WLAN Cards
- PCMCIA, Cardbus32, MiniPCI Cards
- Compact Flash Cards
• Hand-Held Instruments
NOTES:
1. Tape and Reel available. Add “-T” suffix for Tape and Reel
Packing Option.
2. Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020C.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004. All Rights Reserved. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL6416
Pinout and Typical Application Schematic
ISL6416 (QSOP)
TOP VIEW
FAULT
VIN 16
1 FAULT
VIN 15
2 NC
RESET
3 RESET
VOUT1 14
5 SHDN
VOUT3
+2.8V
C4
10µF
C8
0.01µF
C2
10µF
CC1 13
4 CT
SHDN
C1
10µF
VOUT2 12
6 NC
CC2 11
7 VOUT3
GND 10
8 CC3
GND 9
C5
0.033µF
C3
10µF
VIN
+3.3V
VOUT1
+1.8V
VOUT2
+2.8V
C6
0.033µF
C7
0.033µF
Typical Bill Of Materials
REFERENCE
DESIGNATOR
VALUE
PACKAGE
MANUFACTURER
MANUFACTURER’S
PART NUMBER
C1, C2, C3, C4
10µF, X7R
1206
TDK
C3216X7R1A106M
C5, C6, C7
0.033µF, X7R
0603
TDK/ANY
C1608X7R1A333K
C8
0.01µF, X7R
0603
TDK/ANY
C1608X7R1A103K
U1
ISL6416IA
QSOP16
Intersil
ISL6416IA
2
FN9193.0
November 3, 2004
ISL6416
Functional Block Diagram
BAND GAP REF.
1.2V
9
GND
10
GND
1
FAULT
VIN
16
VIN
15
VOUT1
14
CC1
13
LDO1
VREF
+
WINDOW
COMP
EN
EN
THERMAL SHUTDOWN
150°C
LDO2
VIN
CONTROL
LOGIC
EN
EN
5
OUT2
VREF
EN
VOUT2
12
CC2
11
CC2
SHDN
LDO3
4
VIN
CT
RESET
EN
3
RESET
3
OUT3
VREF
EN
VOUT3
7
CC3
8
CC3
FN9193.0
November 3, 2004
ISL6416
Absolute Maximum Ratings
Thermal Information
VIN, SHDN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V
RESET, CC, FAULT to GND . . . . . . . . . . . . . . . . . . . . -0.3V to 7.0V
Output Current (Continuous)
LDO1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330mA
LDO2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225mA
LDO3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125mA
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance (Typical)
JA (°C/W)
QSOP Package (Note 3) . . . . . . . . . . . . . . . . . . .
105
Maximum Junction Temperature (Plastic Package) . -55°C to 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
Operating Temperature Range . . . . . . . . . . . . . . . . . . -40°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
Electrical Specifications
VIN = +3.3V, Compensation Capacitor = 33nF, TA = 25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
3.0
3.3
3.6
V
GENERAL SPECIFICATIONS
VIN Voltage Range
Operating Supply Current
IOUT = 0mA
-
830
-
A
Shutdown Supply Current
SHDN = GND
-
5
10
A
SHDN Input Threshold
VIH, VIN = 3V to 3.6V
2.0
-
-
V
VIL, VIN = 3V to 3.6V
-
-
0.4
V
145
150
160
°C
-
20
-
°C
-
120
-
s
2.4
2.45
2.6
V
-
1.8
-
V
Thermal Shutdown Temperature (Note 6)
Thermal Shutdown Hysteresis (Note 6)
Start-up Time (Note 6)
COUT = 10F, VOUT = 90% of final
value
Input Undervoltage Lockout (Note 6)
Rising 75mV Hysteresis
LDO1 SPECIFICATIONS
Output Voltage (VOUT1)
Output Voltage Initial Accuracy
IOUT = 10mA, TA = -40°C to 85°C
-2.0
-
2.0
%
Line Regulation
VIN = 3.0V to 3.6V, IOUT = 10mA
-0.15
0.0
0.15
%/V
Load Regulation
IOUT = 10mA to 330mA
-1.5
-
1.5
%
Maximum Output Current (IOUT1)
VIN = 3.3V
330
-
-
mA
500
-
-
mA
-
115
-
VRMS
-
2.8
-
V
Output Current Limit
Output Voltage Noise (Note 6)
10Hz < f < 100kHz, COUT = 4.7F,
IOUT = 50mA
LDO2 SPECIFICATIONS
Output Voltage (VOUT2)
Output Voltage Accuracy
IOUT = 10mA, TA = -40°C to 85°C
-2.0
-
2.0
%
Maximum Output Current (IOUT2)
VIN = 3.3V
225
-
-
mA
330
-
-
mA
-
75
200
mV
Output Current Limit
Dropout Voltage (Note 4)
IOUT = 225mA
Line Regulation
VIN = 3.0V to 3.6V, IOUT = 10mA
-0.15
0.0
0.15
%/V
Load Regulation
IOUT = 10mA to 225mA
-1.0
0.2
1.0
%
4
FN9193.0
November 3, 2004
ISL6416
Electrical Specifications
VIN = +3.3V, Compensation Capacitor = 33nF, TA = 25°C, unless otherwise noted. (Continued)
PARAMETER
TEST CONDITIONS
Output Voltage Noise (Note 6)
MIN
TYP
MAX
UNITS
COUT = 2.2F
-
65
-
VRMS
COUT = 10F
-
60
-
VRMS
-
2.8
-
V
10Hz < f < 100kHz, IOUT = 10mA
LDO3 SPECIFICATIONS
Output Voltage (VOUT3)
Output Voltage Accuracy
IOUT = 10mA, TA = -40°C to 85°C
-2.0
-
2.0
%
Maximum Output Current (IOUT3)
VIN = 3.3V
125
-
-
mA
300
-
-
mA
-
65
200
mV
Output Current Limit
Dropout Voltage (Note 4)
IOUT = 125mA
Line Regulation
VIN = 3.0V to 3.6V, IOUT = 10mA
-0.15
0.0
0.15
%/V
Load Regulation
IOUT = 10mA to 125mA
-1.0
0.2
1.0
%
Output Voltage Noise (Note 6)
10Hz < f < 100kHz, IOUT = 10mA
COUT = 2.2F
-
30
-
VRMS
COUT = 10F
-
20
-
VRMS
2.564
2.630
2.66
V
6.3
-
-
mV
-
20
-
s
50
-
-
ms
RESET BLOCK SPECIFICATIONS
Reset Threshold
Reset Threshold Hysteresis (Note 5)
VIN to Reset Delay (Note 5)
VCC = VTH to VTH - 100mV
RESET Active Timeout Period (Note 5)
CT = 0.01µF
FAULT
Rising Threshold
% of VOUT
+5.5
+8.0
+10.5
%
Falling Threshold
% of VOUT
-10.5
-8.0
-5.5
%
4. The dropout voltage is defined as VIN - VOUT, when VOUT is 50mV below the value of VOUT for VIN = VOUT + 0.5V.
5. The RESET time is linear with CT at a slope of ~5ms/nF. Thus, at 10nF (0.01F) the RESET time is 50ms.
6. Guaranteed by design, not production tested.
Typical Performance Curves
The test conditions for the Typical Operating Performance are: VIN = 3.3V, TA = 25°C,
Unless Otherwise Noted
SHDN
1V/DIV
SHDN
1V/DIV
VOUT3
1V/DIV
VOUT2
1V/DIV
VOUT2
1V/DIV
VOUT3
1V/DIV
VOUT1
1V/DIV
VOUT1
1V/DIV
100µs/DIV
FIGURE 1. START-UP SEQUENCE
5
100µs/DIV
FIGURE 2. SHUTDOWN SEQUENCE
FN9193.0
November 3, 2004
ISL6416
Typical Performance Curves
The test conditions for the Typical Operating Performance are: VIN = 3.3V, TA = 25°C,
Unless Otherwise Noted (Continued)
VOUT2
100mV/DIV
VOUT1
50mV/DIV
IOUT2
100mA/DIV
IOUT1
200mA/DIV
1ms/DIV
1ms/DIV
FIGURE 3. LDO1 LOAD TRANSIENT RESPONSE (10mA to
380mA)
FIGURE 4. LDO2 LOAD TRANSIENT RESPONSE (10mA to
200mA)
SHDN
2V/DIV
VOUT3
100mV/DIV
VOUT1
2V/DIV
RESET
2V/DIV
IOUT3
50mA/DIV
FAULT
2V/DIV
1ms/DIV
FIGURE 5. LDO3 LOAD TRANSIENT RESPONSE (10mA to
100mA)
20ms/DIV
FIGURE 6. SHUTDOWN FAULT AND RESET OPERATION
VIN
0.5V/DIV
VIN
0.5V/DIV
RESET
0.5V/DIV
RESET
0.5V/DIV
CT
0.5V/DIV
CT
0.5V/DIV
20ms/DIV
FIGURE 7. RESET DELAY DURING START-UP (CT = 0.01µF)
6
100ms/DIV
FIGURE 8. RESET DELAY DURING START-UP (CT = 0.1µF)
FN9193.0
November 3, 2004
ISL6416
Typical Performance Curves
The test conditions for the Typical Operating Performance are: VIN = 3.3V, TA = 25°C,
Unless Otherwise Noted (Continued)
-10
PSRR (dB)
-20
FAULT
1V/DIV
-30
-40
-50
-60
VOUT1/2/3
1V/DIV
10
500ms/DIV
100
1K
10K
100K
1M
FREQUENCY (A)
FIGURE 9. THERMAL SHUTDOWN OPERATION
VIN
0.5V/DIV
FIGURE 10. LDO1 POWER SUPPLY REJECTION
(IOUT1 = 100mA, COUT = 10µF CERAMIC)
VIN = 2.7V
VOUT1
0.5V/DIV
FAULT
0.5V/DIV
FIGURE 11. VOUT1 REGULATION DOWN TO VIN = 2.7V. FAULT MONITORS VOUT1 ONLY
Pin Descriptions
VOUT1 - This pin is the output for LDO1. Bypass with a
minimum of 2.2µF, low ESR ceramic capacitor to GND for
stable operation.
VIN - Supply input pins. Connect to input power source.
Bypass with a minimum 2.2µF capacitor to GND. Both VIN
pins must be tied together on the PC board, close to the IC.
GND - Ground for LDO1, LDO2, and LDO3.
CC1 - Compensation Capacitor for LDO1. Connect a
0.033µF capacitor from CC1 to GND.
SHDN - Shutdown input for all LDOs. This pin is pulled up
internally. Drive this pin LOW to turn off all LDOs.
7
VOUT2 - This pin is the output for LDO2. Bypass with a
minimum of 2.2µF, low ESR capacitor to GND for stable
operation.
CT - Timing pin for the RESET circuit pulse width. A
capacitor connected from this pin to GND will set a delay the
RESET delay. Leaving this pin open will make the RESET
delay approximately zero.
CC2 - Compensation capacitor for LDO2. Connect a
0.033µF capacitor from CC2 to GND.
VOUT3 - This pin is output for LDO3. Bypass with a
minimum of 2.2µF, low ESR capacitor to GND3 for stable
operation.
FN9193.0
November 3, 2004
ISL6416
CC3 - Compensation capacitor for LDO3. Connect a
0.033µF capacitor from CC3 to GND3.
FAULT - This is the power good indicator for LDO1. When
the 1.8V output is out of regulation this pin goes LOW. This
pin also goes LOW during thermal shutdown or an
overcurrent event on LDO1. Leave floating if not used.
RESET - This pin is the active-LOW output of the push-pull
output stage of the integrated reset supervisory circuit. The
reset circuit monitors VIN and asserts a RESET output at this
pin, if VIN falls below the reset threshold. The RESET output
remains LOW, while the VIN pin voltage is below the reset
threshold, and for a time set by the CT capacitor, after VIN
rises above the reset threshold.
threshold, keeping it asserted for a programmable time (set
by external capacitor CT) after the VIN pin voltage has risen
above the reset threshold. The reset threshold for the
ISL6416 is 2.63V typical.
The voltage at the CT pin is compared to the 1.2V bandgap
voltage. The charging of the CT capacitor behaves like an
RC network and the RESET delay can be approximated by:
Td = -R*C*ln(1-1.2V/VIN)
Where C is the capacitor at CT, and R is 11.1M for
VIN = 3.3V. With no capacitor on the CT pin the RESET
delay will be close to zero. Figure 12 shows the RESET
delay vs CT capacitance.
500
Functional Description
The 1.2V band gap reference is connected to the error
amplifier’s non-inverting input. The error amplifier compares
this reference to the selected feedback voltage and amplifies
the difference. The MOSFET driver reads the error signal
and applies the appropriate drive to the P-Channel pass
transistor. If the feedback voltage is lower then the reference
voltage, the pass transistor gate is pulled lower, allowing
more current to pass and increasing the output voltage. If the
feedback voltage is higher than the reference voltage, the
pass transistor gate is driven higher, allowing less current to
pass to the output. The output voltage is fed back through an
internal resistor divider connected to OUT1/2/3 pins.
Additional blocks include an output overcurrent protection,
thermal sensor, fault detector, RESET function and
shutdown logic.
Internal P-Channel Pass Transistors
The ISL6416 features a typical 0.5 rDS(ON) P-channel
MOSFET pass transistor. This provides several advantages
over similar designs using PNP bipolar pass transistors. The
P-Channel MOSFET requires no base drive, which reduces
quiescent current considerably. PNP based regulators waste
considerable current in dropout when the pass transistor
saturates. They also use high base drive currents under
large loads. The ISL6416 does not suffer from these
problems.
Integrated Reset for MAC/ Baseband Processors
The ISL6416 includes a microprocessor supervisory block.
This block eliminates the extra reset IC and external
components needed in wireless chipset applications. This
block performs a single function; it asserts a RESET signal
whenever the VIN supply voltage decreases below a preset
8
400
DELAY (ms)
The ISL6416 is a 3-in-1 multi-output, low dropout, regulator
designed for wireless chipset power applications. It supplies
three fixed output voltages 1.8V, 2.8V and 2.8V. Each LDO
consists of a 1.2V reference, error amplifier, MOSFET driver,
P-Channel pass transistor, dual-mode comparator and
internal feedback voltage divider.
300
200
100
0
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0
CT (µF)
FIGURE 12. RESET DELAY vs CT CAPACITANCE
Output Voltages
The ISL6416 provides fixed output voltages for use in
Wireless Chipset applications. Internal trimmed resistor
networks set the typical output voltages as shown here:
VOUT1 = 1.8V; VOUT2 = 2.8V; VOUT3 = 2.8V.
Shutdown
Pulling the SHDN pin LOW puts the complete chip into
shutdown mode, and supply current drops to 5A typical.
This input has an internal pull-up resistor, so that in normal
operation the outputs are always enabled; external pull-up
resistors are not required.
Current Limit
The ISL6416 monitors and controls the pass transistor’s
gate voltage to limit the output current. The current limit for
LDO1 is 500mA, LDO2 is 330mA and LDO3 is 300mA. The
output can be shorted to ground without damaging the part
due to the current limit and thermal protection features.
Thermal Overload Protection
Thermal overload protection limits total power dissipation in
the ISL6416. When the junction temperature (TJ) exceeds
+150°C, the thermal sensor sends a signal to the shutdown
logic, turning off the pass transistor and allowing the IC to
cool. The pass transistor turns on again after the IC’s junction
temperature typically cools by 20°C, resulting in a pulsed
output during continuous thermal overload conditions.
Thermal overload protection protects the ISL6416 against
FN9193.0
November 3, 2004
ISL6416
fault conditions. For continuous operation, do not exceed the
absolute maximum junction temperature rating of +150°C.
of the IC and returned to a clean analog ground. Any good
quality ceramic or tantalum can be used as an input capacitor.
Operating Region and Power Dissipation
The output capacitor must meet the requirements of minimum
amount of capacitance and ESR for all three LDO’s. The
ISL6416 is specifically designed to work with small ceramic
output capacitors. The output capacitor’s ESR affects stability
and output noise. Use an output capacitor with an ESR of
50m or less to insure stability and optimum transient
response. For stable operation, a ceramic capacitor, with a
minimum value of 3.3F, is recommended for VOUT1 for
300mA output current, and 2.2F is recommended for VOUT2
and VOUT3 each at 200mA load current. There is no upper
limit to the output capacitor value. A larger capacitor can
reduce noise and improve load transient response, stability
and PSRR. Higher value of the output capacitor (10µF) is
recommended for LDO3 when used to power VCO circuitry in
wireless chipsets. The output capacitor should be located very
close to Vout pins to minimize impact of PC board
inductances and the other end of the capacitor should be
returned to a clean analog ground.
The maximum power dissipation of ISL6416 depends on the
thermal resistance of the IC package and circuit board, the temperature difference between the die junction and ambient air,
and the rate of air flow. The power dissipated in the device is:
PT = P1 + P2 + P3, where
P1 = Iout1 (Vin – Vout1)
P2 = Iout2 (Vin – Vout2)
P3 = Iout3 (Vin- Vout3)
The maximum power dissipation is:
Pmax = (Tjmax – TA)/JA
Where Tjmax = 150°C, TA = ambient temperature, and JA
is the thermal resistance from the junction to the surrounding
environment.
Integrator Circuitry
The ISL6416 uses an external 33nF compensation capacitor
for minimizing load and line regulation errors and for lowering
output noise. When the output voltage shifts due to varying
load current or input voltage, the integrator capacitor voltage
is raised or lowered to compensate for the systematic offset at
the error amplifier. Compensation is limited to ±5% to
minimize transient overshoot when the device goes out of
dropout, current limit, or thermal shutdown.
Input-Output (Dropout) Voltage
A regulator’s minimum input-output voltage differential (or
dropout voltage) determines the lowest usable supply
voltage. Because the ISL6416 uses a P-channel MOSFET
pass transistor, its dropout voltage is a function of rDS(ON)
(typically 0.5) multiplied by the load current.
FAULT Functionality
TABLE 1.
EVENT
FAULT
Below UVLO threshold
L
VOUT1 = 1.8V ±8% typ
VOUT2/3 not in regulation
H
VOUT1 not in regulation
VOUT2 and VOUT3 are in regulation
L
Thermal Shutdown
L
Normal Shutdown with SHDN pin
L
Overcurrent only on LDO1
L
Overcurrent only on LDO2/LDO3
H
Applications Information
Capacitor Selection and Regulator Stability
Capacitors are required at the ISL6416’s input and output for
stable operation over the entire load range and the full
temperature range. Use > 2.2µF capacitor at the input of
ISL6416. The input capacitor lowers the source impedance of
the input supply. Larger capacitor values and lower ESR
provides better PSRR and line transient response. The input
capacitor must be located as close as possible to the VIN pins
9
FN9193.0
November 3, 2004
ISL6416
Shrink Small Outline Plastic Packages (SSOP)
Quarter Size Outline Plastic Packages (QSOP)
M16.15A
N
INDEX
AREA
H
0.25(0.010) M
E
2
INCHES
GAUGE
PLANE
-B1
16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
(0.150” WIDE BODY)
B M
3
0.25
0.010
SEATING PLANE
-A-
A
D
h x 45°
-C-
e

A1
B
0.17(0.007) M
L
A2
C
0.10(0.004)
C A M
B S
NOTES:
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.061
0.068
1.55
1.73
-
A1
0.004
0.0098
0.102
0.249
-
A2
0.055
0.061
1.40
1.55
-
B
0.008
0.012
0.20
0.31
9
C
0.0075
0.0098
0.191
0.249
-
D
0.189
0.196
4.80
4.98
3
E
0.150
0.157
3.81
3.99
4
e
0.025 BSC
0.635 BSC
-
H
0.230
0.244
5.84
6.20
-
h
0.010
0.016
0.25
0.41
5
L
0.016
0.035
0.41
0.89
6
8°
0°
N
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
MILLIMETERS

16
0°
16
7
8°
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
Rev. 2 6/04
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.10mm (0.004 inch) total in excess
of “B” dimension at maximum material condition.
10. Controlling dimension: INCHES. Converted millimeter dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
10
FN9193.0
November 3, 2004
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