ISL9000AM ESIGNS R NEW D NT O F D E D N EME COMME REPL AC D t E NO T RE D N MMESheet upport Center a November 11, 2011 Data O S c l NO REC s a /t ic m n o h tersil.c our Tec contact ERSIL or www.in T 1-888-IN Dual LDO with Low Noise, Very High PSRR and Low IQ FN6620.1 Features • Integrates Two 100mA High Performance LDO’s ISL9000AMRNCP is a high performance dual LDO capable of sourcing 100mA current from each output. It has a low standby current and very high PSRR and is stable with output capacitance of 1µF to 10µF with ESR of up to 200m. • IOUT per Channel is 50mA at TJ = +150°C • Excellent Transient Response to Large Current Steps • ±1.8% Accuracy Over all Operating Conditions The device integrates an individual Power-On-Reset (POR) function for each output. The POR delay for VO2 can be externally programmed by connecting a timing capacitor to the CPOR pin. The POR delay for VO1 is internally fixed at approximately 2ms. A reference bypass pin is also provided for connecting a noise filtering capacitor for low noise and high-PSRR applications. • Excellent Load Regulation: < 0.1% Voltage Change Across Full Range of Load Current • Low Output Noise: Typically 30µVrms @ 100µA (1.5V) • Very High PSRR: 90dB @ 1kHz • Extremely Low Quiescent Current: 42µA (both LDOs active) The quiescent current is typically only 42µA with both LDO’s enabled and active. Separate enable pins control each individual LDO output. When both enable pins are low, the device is in shutdown, typically drawing less than 0.1µA. • Wide Input Voltage Capability: 2.3V to 5.5V • Low Dropout Voltage: Typically 200mV @ 100mA • Stable with 1µF to 10µF Ceramic Capacitors Output voltage for the LDO are VOUT1 = 3.3V and VOUT2 = 1.8V. • Separate Enable and POR Pins for Each LDO • Soft-Start and Staged Turn-On to Limit Input Current Surge During Enable Device Information The specifications for an Enhanced Product (EP) device are defined in a Vendor Item Drawing (VID), which is controlled by the Defense Logistics Agency (DLA). “Hot-links” to the applicable VID and other supporting application information are provided on our website. • Current Limit and Overheat Protection • Tiny 10 Ld 3x3mm DFN Package • -55°C to +125°C Operating Temperature Range Applications Pinout • PDAs, Cell Phones and Smart Phones ISL9000AMNCEP (10 LD 3X3 DFN) TOP VIEW • Portable Instruments, MP3 Players • Handheld Devices including Medical Handheld VIN 1 10 VO1 EN1 2 9 VO2 EN2 3 8 POR2 CBYP 4 7 POR1 CPOR 5 6 GND Ordering Information VENDOR PART NUMBER (Notes 1, 2) ISL9000AMRNCEP VENDOR ITEM DRAWING V62/08609-01XB PART MARKING DKTA VO2 VO1 VOLTAGE VOLTAGE TEMP RANGE (V) (°C) (V) 3.3 1.8 -55 to +125 PACKAGE 10 Ld 3x3 DFN PKG DWG. # L10.3x3C NOTES: 1. Add -T to part number for tape and reel. 2. Devices must be procured to the VENDOR PART NUMBER. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2007, 2011. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. ISL9000AM Dual Flat No-Lead Plastic Package (DFN) L10.3x3C 10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE 2X MILLIMETERS 0.10 C A A D 2X 0.10 C B SYMBOL MIN NOMINAL MAX NOTES A 0.85 0.90 0.95 - A1 - - 0.05 - b 6 INDEX AREA D2 B A C SEATING PLANE D2 7 0.08 C 8 2.38 2.43 7, 8 1.69 7, 8 3.00 BSC 1.59 1.64 - - 0.50 BSC k 0.20 - - - L 0.35 0.40 0.45 8 N 10 2 Nd 5 3 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2 2. N is the number of terminals. NX k AREA (DATUM A) 3. Nd refers to the number of terminals on D. 4. All dimensions are in millimeters. Angles are in degrees. E2 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. E2/2 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. NX L N-1 NX b e (Nd-1)Xe REF. BOTTOM VIEW 5 0.10 M C A B 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. COMPLIANT TO JEDEC MO-229-WEED-3 except for dimensions E2 & D2. CL NX (b) 5, 8 NOTES: INDEX N 0.30 Rev. 1 4/06 D2/2 1 2.33 e A3 SIDE VIEW (DATUM B) 0.10 C E2 0.25 - 3.00 BSC E // 8 0.20 D TOP VIEW 6 0.20 REF A3 E (A1) 9 L 5 e SECTION "C-C" C C TERMINAL TIP FOR ODD TERMINAL/SIDE All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 2 FN6620.1