HIP5010, HIP5011 IGNS W DES E N R O EMENT NDED F EPLAC nter at C OMME R E D R E T D O N Ce OMMEN pportSheet om/tsc NO REC Technical SuData tersil.c r n u .i o w t w c conta TERSIL or w 1-888-IN TM March 1996 FN4029.5 7V, 17A SynchroFET™ Complementary Drive Synchronous Half-Bridge Features Designed with the P6 and Pentium® in mind, the Intersil SynchroFET™ family provides a new approach for implementing a synchronous rectified buck switching regulator. The SynchroFET replaces two power DMOSs, a Schottky diode, two gate drivers and synchronous control circuitry. The complementary drive circuit turns the upper FET on and the lower FET off when the input from the PWM is high. When the input from the PWM goes low the upper FET turns off and the lower FET turns on. The HIP5011 has a PWM pin that inverts the relationship from the input to PHASE. This architecture allows the designer to utilize a low cost single-ended PWM controller in either a current or voltage mode configuration. The SynchroFET operates in continuous conduction mode reducing EMI constraints and enabling high bandwidth operation. Several features ensure easy start-up. First, the supply currents stay below specification as the supply voltages ramp up; no unexpected surges occur that might perturb a soft-start or deplete a charge-pump. Second, any power-up sequence of the VCC , VIN , or PWM pins can be used without causing large currents. Third, the chip operates when VCC is greater than 2V so VCC can be created from a charge pump powered from VIN. • Use With Low-Cost Single-Output PWM Controllers • Complementary Drive, Half-Bridge Power NMOS • Improve Efficiency Over Conventional Buck Converter with Schottky Clamp • Minimum Deadtime Provided by Adaptive Shoot-Through Protection Eliminates External Schottky • Grounded Case for Low EMI and Simple Heatsinking • Low Operating Current • Frequency Exceeding 1MHz • Dual Polarity Input Options • All Pins Surge Protected Applications • 5V to ≤3.3V Synchronous Buck Converters • Pentium and P6 Power Supplies • PowerPC ™ Power Supplies • Bus Terminations (BTL and GTL) • Drive 5V Motors Directly from Microprocessor Pinouts Ordering Information HIP5010IS1, HIP5011IS1 (SIP - VERTICAL) TOP VIEW 7 6 5 4 3 2 1 GND (TAB) PHASE VIN PWM (HIP5010), PWM (HIP5011) VCC VIN PHASE FRONT ROWS = PINS 1, 3, 5, 7 BACK ROWS = PINS 2, 4, 6 PART NUMBER TEMP. RANGE (oC) PACKAGE PKG. NO. HIP5010IS -40 to 85 7 Ld Gullwing SIP Z7.05B HIP5010IS1 -40 to 85 7 Ld Staggered Vertical SIP Z7.05C HIP5011IS -40 to 85 7 Ld Gullwing SIP HIP5011IS1 -40 to 85 7 Ld Staggered Vertical SIP Z7.05C Z7.05B Typical Application Block Diagram HIP5010IS, HIP5011IS (SIP - GULLWING) TOP VIEW GND (TAB) 7 6 5 4 3 2 1 +12V +5V PHASE VIN PWM (HIP5010), PWM (HIP5011) VCC VIN PHASE VCC PWM CONTROLLER PWM VIN +3.3V CONTROL PHASE HIP5010 GND SYNCHRONOUS RECTIFIED BUCK CONVERTER Pentium® is a registered trademark of Intel Corporation. PowerPC™ is a trademark of International Business Machines. SynchroFET™ is a trademark of Intersil Corporation. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved HIP5010, HIP5011 Non-Inverting SynchroFET Block Diagram HIP5010 VCC VIN DRIVER ADAPTIVE SHOOT-THROUGH PROTECTION BUFFER PHASE PWM VCC DRIVER GND Inverting SynchroFET Block Diagram HIP5011 VCC VIN DRIVER ADAPTIVE SHOOT-THROUGH PROTECTION BUFFER PHASE PWM VCC DRIVER GND 2 HIP5010, HIP5011 Absolute Maximum Ratings Thermal Information (Typical) Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +16V Input Voltage VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7V IPHASE, IVIN, IGND (TJ = 25oC) . . . . . . . . . . . 17A (Repetitive Peak) IPHASE, IVIN, IGND (TJ = 150oC) . . . . . . . . . . 15A (Repetitive Peak) PWM Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -4V to +16V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3 (4kV) Lead Temperature (Soldering 10s) (Lead Tips Only) . . . . . . 300oC Storage Temperature Range . . . . . . . . . . . . . . . . . . -65oC to 150oC Junction Temperature Range . . . . . . . . . . . . . . . . . -40oC to 150oC Operating Conditions Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . +12V, ±20% Input Voltage VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 5.5V Supply Voltage, VCC, minimum for charge-pumped start-up . +4.0V θJA (oC/W)† 2 3 θJC †† (oC/W) 0 1 SOIC (IB) . . . 26 63 45 42 41 35 SIP (IS). . . . . 2 55 30 25 24 18 SIP (IS1). . . . 2 - - - - - Package 3††† Versus additional square inches of 1 ounce copper on the printed circuit board. †† θJC is measured to pin 12 for the SOIC. Printed circuit board had 1 square inch of copper. For SIP Packages value shown is typical with an infinite heat sink. ††† 200 linear feet per minute of air flow. † IPHASE .SIPs:11.5A(RMS), 11.2A(DC); SOIC:7.4A(RMS), 7.4A(DC) IVIN . . . SIPs:10.0A(RMS), 8.5A(DC); SOIC:6.4A(RMS), 6.4A(DC) IGND. . . . .SIPs:8.5A(RMS), 6.0A(DC); SOIC:5.4A(RMS), 5.4A(DC) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the recommended operating conditions of this specification is not implied. Electrical Specifications TJ = - 40oC TJ = 150oC TJ = 25oC PARAMETERS SYMBOL TEST CONDITIONS MIN TYP MAX MIN MAX UNITS rDS(ON) Upper MOSFET RDSU VCC = 12V, VIN = 5V - 34 39 - 65 mΩ rDS(ON) Lower MOSFET RDSL VCC = 12V, VIN = 5V - 36 42 - 68 mΩ VIN Operating Current IVINO VIN = 5V, No Load, 500kHz - 5 8 - 10 mA VIN Quiescent Current IVIN PWM or PWM = VCC or GND - 0.1 10 - 100 μA VCC Operating Current ICCO VCC = 12V, 500kHz - 8 12 - 15 mA VCC Quiescent Current (HIP5010) ICCIH PWM = VCC - 80 - - 400 μA VCC Quiescent Current (HIP5010) ICCIL PWM = GND - 0.1 10 - 100 μA VCC Quiescent Current (HIP5011) ICCNIH PWM = VCC - 0.1 10 - 100 μA VCC Quiescent Current (HIP5011) ICCNIL PWM = GND - 140 - - 400 μA Low Level PWM Input Voltage VIL - 1.8 - 1 - V High Level PWM Input Voltage VIH - 2.1 - - 3 V PWM Input Voltage Hysteresis VIHYS - 0.3 - - - V Input Pulldown Resistance (HIP5010) RPWM - 220 - 100 400 kΩ Input Pullup Resistance (HIP5011) RPWM - 220 - 100 400 kΩ Switching Specifications TJ = - 40oC TJ = 150oC TJ = 25oC PARAMETERS SYMBOL TEST CONDITIONS MIN TYP MAX MIN MAX UNITS Upper Device Turn-Off Delay tPHL VCC = 12V, IPHASE = -1A - 30 50 - 80 ns Lower Device Turn-Off Delay tPLH VCC = 12V, IPHASE = +1A - 30 50 - 80 ns Dead Time tDT VCC = +12V, IPHASE = -1A - 10 - - - ns Phase Rise-Time tr VCC = 12V, IPHASE = -1A - 20 - - - ns Phase Fall-Time tf VCC = 12V, IPHASE = +1A - 20 - - - ns 3 HIP5010, HIP5011 Pin Descriptions SYMBOL DESCRIPTION VCC Positive supply to control logic and gate drivers. De-couple this pin to GND. VIN FET Switch Input Voltage. De-couple this pin to GND. Tie all VIN terminals together. PHASE Output. Tie all phase terminals together. PWM (HIP5010) PWM (HIP5011) GND Single Ended Control Input. This input connects to the PWM controller output. System Ground. Timing Diagram 12V PWM (HIP5010) 2V 0V 12V PWM (HIP5011) 2V 0V tPHL tPLH 5V 4.5V PHASE 2.5V 0.5V 0V -0.5V tf NOTE: IPHASE = +1A for tPLH and tf , IPHASE = -1A for tPHL, tDT , and tr . FIGURE 1. 4 tDT tr HIP5010, HIP5011 20 6.0 18 5.5 16 5.0 14 4.5 12 3.5 IVINO (mA) ICCO (mA) Typical Performance Curves 10 8 3.0 2.5 6 2.0 4 1.5 2 1.0 0 0 100 200 300 400 500 600 700 800 900 0 1000 0 100 200 300 400 FREQUENCY (kHz) 110 110 100 100 90 90 80 80 rDSL (mΩ) 120 VIN = 5V VIN = 3.3V 60 50 40 30 30 5 6 7 8 9 10 11 900 1000 12 13 14 15 16 VIN = 5V AND 3.3V 20 4 5 6 7 8 VCC (V) 9 10 11 12 VCC (V) FIGURE 4. RDSU vs VCC FIGURE 5. RDSL vs VCC 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 -40 -20 0 20 40 60 80 TEMPERATURE (oC) 100 120 FIGURE 6. RDSU OR RDSL vs TEMPERATURE 5 800 60 40 4 700 70 50 20 600 FIGURE 3. IVINO vs FREQUENCY 120 RDSU OR RDSL (NORMALIZED) rDSU (mΩ) FIGURE 2. ICCO vs FREQUENCY 70 500 FREQUENCY (kHz) 140 13 14 15 16 HIP5010, HIP5011 Single-In-Line Plastic Packages (SIP) -A- A 0.006 -B- (0.15) E C2 Z7.05B 7 LEAD PLASTIC SINGLE-IN-LINE PACKAGE SURFACE MOUNT “GULLWING” LEAD FORM L2 INCHES HEATSLUG PLANE D L -C- 0.00 - 0.0098 (0.00 - 0.25) L1 PIN #1 c 0o- 8o e b 0.010 (0.25) M B A M C M 0.004 (0.10) L3 E1 0.350 (8.89) MIN D1 SYMBOL MIN MAX MIN MAX NOTES A 0.170 0.180 4.32 4.57 - C2 0.048 0.055 1.22 1.39 5 D 0.350 0.370 8.89 9.39 - 10.28 - E 0.395 0.405 10.04 D1 0.310 - 7.88 E1 0.310 - 7.88 L 0.549 0.569 13.95 14.45 - L1 0.068 0.088 1.72 2.24 - L2 0.045 0.055 1.15 1.40 - L3 0.450 (11.43) MIN 0.609 (15.46) MIN MILLIMETERS 0.030 BSC - - - - 0.76 BSC 4 b 0.028 0.034 0.71 0.86 5, 6, 7 c 0.018 0.024 0.46 0.60 5 e 0.050 BSC 1.27 BSC Rev. 2 12/95 NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-169AC, Issue A. 2. Controlling dimension: Inch. BACK VIEW 0.129 (3.27) TYP 0.030 (0.76) TYP 6 e LAND PATTERN 3. Dimensioning and tolerance per ANSI Y14.5M-1982. 4. Gauge plane L3 is parallel to heatslug plane. 5. Dimensions include lead finish. 6. Leads are not allowed above the datum -B- . 7. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum “b” by more than 0.003’’ (0.08mm). HIP5010, HIP5011 Single-In-Line Plastic Packages (SIP) Z7.05C 0.006 (0.15) 7 LEAD PLASTIC SINGLE-IN-LINE PACKAGE STAGGERED VERTICAL LEAD FORM A INCHES D -B- ØP D1 F E2 HEADER BOTTOM E L1 E1 L e H L -A- B e3 e1 e2 L L L H H 7 PLACES H H 0.010 (0.25) M A B M MIN MAX MIN MAX NOTES A 0.170 0.180 4.32 4.57 - B 0.028 0.034 0.71 0.86 3, 4 C 0.018 0.024 0.46 0.60 3 D 0.395 0.405 10.04 10.28 - D1 0.198 0.202 5.03 5.13 - E 0.595 0.605 15.11 15.37 - E1 0.350 0.370 8.89 9.39 - E2 0.110 BSC 2.79 BSC e 0.050 BSC 1.27 BSC - e1 0.200 BSC 5.08 BSC - e2 0.169 BSC 4.29 BSC - F ALL LEADS 0.024 (0.61) M SYMBOL e3 C A MILLIMETERS 0.300 BSC 0.048 0.055 7.62 BSC 1.22 - 1.39 3 L 0.150 0.176 3.81 4.47 - L1 0.600 0.620 15.24 15.74 - ØP 0.147 0.152 3.73 3.86 3 Rev. 1 4/98 NOTES: 1. Controlling dimension: INCH. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimensions include lead finish. 4. Dimension “B” does not include dambar protrusion. Allowable dambar protrusion shall not cause lead width to exceed maximum “B” by more than 0.003 inches (0.08mm). All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 7