DATASHEET

ISL2100A, ISL2101A
Data Sheet
December 8, 2015
100V, 2A Peak, High Frequency
Half-Bridge Drivers
Features
• Drives N-Channel MOSFET Half-Bridge
The ISL2100A, ISL2101A are 100V, high frequency,
half-bridge N-channel power MOSFET driver ICs. They are
based on the popular HIP2100, HIP2101 half-bridge drivers,
but offer several performance improvements. The ISL2100A
has additional input hysteresis for superior operation in noisy
environments and the inputs of the ISL2101A, like those of
the ISL2100A, can now safely swing to the VDD supply rail.
Finally, both parts are available in a very compact 9 Ld DFN
package to minimize the required PCB footprint
Ordering Information
• Space-Saving DFN Package
• DFN Package Compliant with 100V Conductor Spacing
Guidelines per IPC-2221
• Pb-Free (RoHS compliant)
• Bootstrap Supply Max Voltage to 114VDC
• On-Chip 1 Bootstrap Diode
• Fast Propagation Times for Multi-MHz Circuits
• Drives 1nF Load with Typical Rise/Fall Times of 10ns
PART NUMBER
PART
TEMP.
(Note)
MARKING RANGE (°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
• CMOS Compatible Input Thresholds (ISL2100A)
• 3.3V/TTL Compatible Input Thresholds (ISL2101A)
ISL2100AAR3Z* 00AZ
-40 to +125 9 Ld 3x3 DFN L9.3x3
ISL2101AAR3Z* 01AZ
-40 to +125 9 Ld 3x3 DFN L9.3x3
• Independent Inputs Provide Flexibility
-40 to +125 8 Ld SOIC
• No Start-Up Problems
ISL2100AABZ
(No longer
available,
recommended
replacement:
HIP2100IBZ)*
001ABZ
ISL2101AABZ*
01ABZ
FN6294.4
M18.15
• Outputs Unaffected by Supply Glitches, HS Ringing Below
Ground or HS Slewing at High dv/dt
• Low Power Consumption
-40 to +125 8 Ld SOIC
M18.15
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on
reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
• Wide Supply Voltage Range (9V to 14V)
• Supply Undervoltage Protection
• 2.5 Typical Output Pull-Up/Pull-Down Resistance
Applications
• Telecom Half-Bridge Converters
• Telecom Full-Bridge Converters
• Two-Switch Forward Converters
• Active-Clamp Forward Converters
Pinouts
ISL2100A, ISL2101A
(9 LD DFN)
TOP VIEW
9 LO
8 VSS
VDD 1
HB 2
• Class-D Audio Amplifiers
EPAD
7 LI
HO 3
6 HI
HS 4
5 NC
ISL2100A, ISL2101A
(8 LD SOIC)
TOP VIEW
VDD
1
8
LO
HB
2
7
VSS
HO
3
6
LI
HS
4
5
HI
NOTE: EPAD = Exposed PAD.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark of Intersil Americas LLC
Copyright Intersil Americas LLC 2008, 2009, 2010, 2015. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL2100A, ISL2101A
Application Block Diagram
+12V
+100V
SECONDARY
CIRCUIT
VDD
HB
DRIVE
HI
CONTROL
HI
PWM
CONTROLLER
LI
HO
HS
LO
DRIVE
LO
ISL2100A
ISL2101A
VSS
REFERENCE
AND
ISOLATION
Functional Block Diagram
HB
VDD
UNDER
VOLTAGE
HO
LEVEL SHIFT
DRIVER
HS
HI
ISL2101A
ISL2101A
UNDER
VOLTAGE
LO
DRIVER
LI
VSS
EPAD (DFN PACKAGE ONLY)
*EPAD = EXPOSED PAD. THE EPAD IS ELECTRICALLY ISOLATED FROM ALL OTHER
PINS. FOR BEST THERMAL PERFORMANCE CONNECT THE EPAD TO THE PCB
POWER GROUND PLANE.
2
FN6294.4
December 8, 2015
ISL2100A, ISL2101A
+48V
+12V
PWM
ISL2100A
ISL2101A
SECONDARY
CIRCUIT
ISOLATION
FIGURE 1. TWO-SWITCH FORWARD CONVERTER
+48V
SECONDARY
CIRCUIT
+12V
PWM
ISL2100A
ISL2101A
ISOLATION
FIGURE 2. FORWARD CONVERTER WITH AN ACTIVE-CLAMP
3
FN6294.4
December 8, 2015
ISL2100A, ISL2101A
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VDD, VHB - VHS (Notes 1, 2) . . . . . . . -0.3V to 18V
LI and HI Voltages (Note 2) . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V
Voltage on LO (Note 2) . . . . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V
Voltage on HO (Note 2) . . . . . . . . . . . . . . VHS - 0.3V to VHB + 0.3V
Voltage on HS (Continuous) (Note 2) . . . . . . . . . . . . . . -1V to 110V
Voltage on HB (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118V
Average Current in VDD to HB Diode . . . . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
Maximum Recommended Operating Conditions
JA (°C/W)
JC (°C/W)
DFN (Notes 3, 4) . . . . . . . . . . . . . . . . .
47
3.5
SOIC (Note 3) . . . . . . . . . . . . . . . . . . .
120
N/A
Max Power Dissipation at +25°C in Free Air (DFN, Note 3) . . . 2.27W
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
For Recommended soldering conditions see Tech Brief TB389.
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9V to 14V
Voltage on HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to 100V
Voltage on HS . . . . . . . . . . . . . . .(Repetitive Transient) -5V to 105V
Voltage on HB . . VHS + 8V to VHS + 14V and VDD - 1V to VDD + 100V
HS Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <50V/ns
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. The ISL2100A-ISL2101A are capable of derated operation at supply voltages exceeding 14V. Figure 22 shows the high-side voltage derating
curve for this mode of operation.
2. All voltages referenced to VSS unless otherwise specified.
3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features.
4. For JC, the “case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379 for details.
Electrical Specifications
VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified. Parameters with MIN
and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
TJ = -40°C to
+125°C
TJ = +25°C
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNITS
0.1
0.25
-
0.3
mA
SUPPLY CURRENTS
VDD Quiescent Current
IDD
ISL2100A; LI = HI = 0V
-
VDD Quiescent Current
IDD
ISL2101A; LI = HI = 0V
-
0.3
0.45
-
0.55
mA
VDD Operating Current
IDDO
ISL2100A; f = 500kHz
-
1.6
2.2
-
2.7
mA
VDD Operating Current
IDDO
ISL2101A; f = 500kHz
-
1.9
2.5
-
3
mA
Total HB Quiescent Current
IHB
LI = HI = 0V
-
0.1
0.15
-
0.2
mA
Total HB Operating Current
IHBO
f = 500kHz
-
2.0
2.5
-
3
mA
HB to VSS Current, Quiescent
IHBS
LI = HI = 0V; VHB = VHS = 114V
-
0.05
1
-
10
µA
HB to VSS Current, Operating
IHBSO
f = 500kHz; VHB = VHS = 114V
-
0.9
-
-
-
mA
INPUT PINS
Low Level Input Voltage Threshold
VIL
ISL2100A
3.7
4.4
-
2.7
-
V
Low Level Input Voltage Threshold
VIL
ISL2101A
1.4
1.8
-
1.2
-
V
High Level Input Voltage Threshold
VIH
ISL2100A
-
6.6
7.4
-
8.4
V
High Level Input Voltage Threshold
VIH
ISL2101A
-
1.8
2.2
-
2.4
V
VIHYS
ISL2100A
-
2.2
-
-
-
V
RI
-
210
-
100
500
k
VDD Rising Threshold
VDDR
6.8
7.3
7.8
6.5
8.1
V
VDD Threshold Hysteresis
VDDH
-
0.6
-
-
-
V
HB Rising Threshold
VHBR
6.2
6.9
7.5
5.9
7.8
V
Input Voltage Hysteresis
Input Pull-down Resistance
UNDERVOLTAGE PROTECTION
4
FN6294.4
December 8, 2015
ISL2100A, ISL2101A
Electrical Specifications
VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified. Parameters with MIN
and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested. (Continued)
TJ = -40°C to
+125°C
TJ = +25°C
PARAMETERS
SYMBOL
HB Threshold Hysteresis
TEST CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNITS
-
0.6
-
-
-
V
VHBH
BOOTSTRAP DIODE
Low Current Forward Voltage
VDL
IVDD-HB = 100µA
-
0.5
0.6
-
0.7
V
High Current Forward Voltage
VDH
IVDD-HB = 100mA
-
0.7
0.9
-
1
V
RD
IVDD-HB = 100mA
-
0.8
1
-
1.5

Dynamic Resistance
LO GATE DRIVER
Low Level Output Voltage
VOLL
ILO = 100mA
-
0.25
0.3
-
0.4
V
High Level Output Voltage
VOHL
ILO = -100mA,
VOHL = VDD - VLO
-
0.25
0.3
-
0.4
V
Peak Pull-Up Current
IOHL
VLO = 0V
-
2
-
-
-
A
Peak Pull-Down Current
IOLL
VLO = 12V
-
2
-
-
-
A
Low Level Output Voltage
VOLH
IHO = 100mA
-
0.25
0.3
-
0.4
V
High Level Output Voltage
VOHH
IHO = -100mA,
VOHH = VHB - VHO
-
0.25
0.3
-
0.4
V
Peak Pull-Up Current
IOHH
VHO = 0V
-
2
-
-
-
A
Peak Pull-Down Current
IOLH
VHO = 12V
-
2
-
-
-
A
HO GATE DRIVER
Electrical Specifications
Switching Specifications VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise
Specified. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified.
Temperature limits established by characterization and are not production tested.
PARAMETERS
SYMBOL
TEST
CONDITIONS
TJ = -40°C
to +125°C
TJ = +25°C
MIN
TYP
MAX
MIN
MAX
UNITS
Lower Turn-Off Propagation Delay (LI Falling to LO Falling)
tLPHL
-
34
50
-
60
ns
Upper Turn-Off Propagation Delay (HI Falling to HO Falling)
tHPHL
-
31
50
-
60
ns
Lower Turn-On Propagation Delay (LI Rising to LO Rising)
tLPLH
-
39
50
-
60
ns
Upper Turn-On Propagation Delay (HI Rising to HO Rising)
tHPLH
-
39
50
-
60
ns
Delay Matching: Upper Turn-Off to Lower Turn-On
tMON
1
8
-
-
16
ns
Delay Matching: Lower Turn-Off to Upper Turn-On
tMOFF
1
6
-
-
16
ns
Either Output Rise/Fall Time (10% to 90%/90% to 10%)
tRC,tFC
CL = 1nF
-
10
-
-
-
ns
CL = 0.1µF
-
0.5
0.6
-
0.8
us
Either Output Rise/Fall Time (3V to 9V/9V to 3V)
tR,tF
Minimum Input Pulse Width that Changes the Output
tPW
-
-
-
-
50
ns
Bootstrap Diode Turn-On or Turn-Off Time
tBS
-
10
-
-
-
ns
5
FN6294.4
December 8, 2015
ISL2100A, ISL2101A
Pin Descriptions
SYMBOL
DESCRIPTION
VDD
Positive supply to lower gate driver. Bypass this pin to VSS.
HB
High-side bootstrap supply. External bootstrap capacitor is required. Connect positive side of bootstrap capacitor to this pin.
Bootstrap diode is on-chip.
HO
High-side output. Connect to gate of high-side power MOSFET.
HS
High-side source connection. Connect to source of high-side power MOSFET. Connect negative side of bootstrap capacitor to this
pin.
HI
High-side input.
LI
Low-side input.
VSS
Chip negative supply, which will generally be ground.
LO
Low-side output. Connect to gate of low-side power MOSFET.
EPAD
Exposed pad. Connect to ground or float. The EPAD is electrically isolated from all other pins.
Timing Diagrams
LI
HI
HI,
LI
tHPLH ,
tLPLH
tHPHL,
tLPHL
LO
tMOFF
tMON
HO,
LO
HO
FIGURE 3. PROPAGATION DELAYS
FIGURE 4. DELAY MATCHING
Typical Performance Curves
10
10
IDDO (mA)
IDDO (mA)
T = +150°C
T = +150°C
1
T = -40°C
T = +125°C
T = +25°C
0.1
10
100
FREQUENCY (kHz)
FIGURE 5. ISL2100A IDD OPERATING CURRENT vs
FREQUENCY
6
3
1 .10
T = -40°C
0.1
T = +125°C
T = +25°C
1
10
3
1 .10
100
FREQUENCY (kHz)
FIGURE 6. ISL2101A IDD OPERATING CURRENT vs
FREQUENCY
FN6294.4
December 8, 2015
ISL2100A, ISL2101A
Typical Performance Curves
(Continued)
10
10
T = +150°C
IHBSO (mA)
IHBO (mA)
T = +25°C
T = -40°C
1
0.1
T = +25°C
1
T = +150°C
0.1
T = -40°C
T = +125°C
T = +125°C
0.01
10
3
1 .10
100
0.01
10
FREQUENCY (kHz)
FREQUENCY (kHz)
FIGURE 7. IHB OPERATING CURRENT vs FREQUENCY
FIGURE 8. IHBS OPERATING CURRENT vs FREQUENCY
450
450
VDD = VHB = 9V
400
VOLL, VOLH (mV)
VOHL, VOHH (mV)
500
350
300
250
VDD = VHB = 12V
200
150
-50
0
50
TEMPERATURE (°C)
100
VDD = VHB = 9V
350
300
250
150
150
VDD = VHB = 12V
VDD = VHB = 14V
-50
0
50
TEMPERATURE (°C)
100
150
FIGURE 10. LOW LEVEL OUTPUT VOLTAGE vs
TEMPERATURE
0.60
VDDH, VHBH (V)
7.6
7.4
VDDR
7.2
VHBR
7.0
6.8
400
200
VDD = VHB = 14V
FIGURE 9. HIGH LEVEL OUTPUT VOLTAGE vs TEMPERATURE
VDDR, VHBR (V)
3
1 .10
100
0.50
0
50
TEMPERATURE (°C)
100
150
FIGURE 11. UNDERVOLTAGE LOCKOUT THRESHOLD vs
TEMPERATURE
7
VDDH
0.45
0.40
50
VHBH
0.55
-50
0
50
TEMPERATURE (°C)
100
150
FIGURE 12. UNDERVOLTAGE LOCKOUT HYSTERESIS vs
TEMPERATURE
FN6294.4
December 8, 2015
ISL2100A, ISL2101A
(Continued)
55
tLPLH, tLPHL, tHPLH, tHPHL (ns)
tLPLH, tLPHL, tHPLH, tHPHL (ns)
Typical Performance Curves
tLPLH
50
tHPLH
45
40
tLPHL
35
30
tHPHL
25
20
-50
0
50
100
150
55
tLPLH
50
tHPLH
45
40
35
30
25
20
-50
0
TEMPERATURE (°C)
9
9
tMON, tMOFF (ns)
tMON, tMOFF (ns)
10
8
tMOFF
6
5
3
tMON
-50
0
50
8
7
6
5
tMOFF
4
3
100
2
-50
150
FIGURE 15. ISL2100A DELAY MATCHING vs TEMPERATURE
0
2.5
2.5
2.0
2.0
1.5
1.0
50
TEMPERATURE (°C)
100
150
FIGURE 16. ISL2101A DELAY MATCHING vs TEMPERATURE
IOLL, IOLH (A)
IOHL, IOHH (A)
150
tMON
TEMPERATURE (°C)
1.5
1.0
0.5
0.5
0
100
FIGURE 14. ISL2101A PROPAGATION DELAYS vs
TEMPERATURE
10
4
50
TEMPERATURE (°C)
FIGURE 13. ISL2100A PROPAGATION DELAYS vs
TEMPERATURE
7
tHPHL
tLPHL
0
2
4
6
8
10
12
VLO, VHO (V)
FIGURE 17. PEAK PULL-UP CURRENT vs OUTPUT VOLTAGE
8
0
0
2
4
6
8
10
12
VLO, VHO (V)
FIGURE 18. PEAK PULL-DOWN CURRENT vs OUTPUT
VOLTAGE
FN6294.4
December 8, 2015
ISL2100A, ISL2101A
260
240
220
200
180
160
140
120
100
80
60
40
20
0
(Continued)
IDD
IHB
0
5
10
340
320
300
280
260
240
220
200
180
160
140
120
100
80
60
40
20
0
IDD, IHB (µA)
IDD, IHB (µA)
Typical Performance Curves
15
20
IDD
IHB
0
5
VHS to VSS VOLTAGE (V)
FORWARD CURRENT (A)
0.1
0.01
1 .10
-4
1 .10
-5
1 .10
-6
0.3
20
120
1
1 .10
15
FIGURE 20. ISL2101A QUIESCENT CURRENT vs VOLTAGE
FIGURE 19. ISL2100A QUIESCENT CURRENT vs VOLTAGE
-3
10
VDD, VHB (V)
VDD, VHB (V)
0.4
0.5
0.6
0.7
FORWARD VOLTAGE (V)
FIGURE 21. BOOTSTRAP DIODE I-V CHARACTERISTICS
9
0.
100
80
60
40
20
0
12
13
14
15
VDD to VSS VOLTAGE (V)
16
FIGURE 22. VHS VOLTAGE vs VDD VOLTAGE
FN6294.4
December 8, 2015
ISL2100A, ISL2101A
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE
REVISION
CHANGE
December 8, 2015
FN6294.4
- Updated Ordering Information Table on page 1.
- Added Revision History.
- Added About Intersil Verbiage.
- Updated POD L9.3X3 to latest revision changes are as follow:
Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends)..
- Updated POD M8.15 to latest revision changes are as follow:
Changed Note 1 "1982" to "1994"
Changed in Typical Recommended Land Pattern the following:
2.41(0.095) to 2.20(0.087)
0.76 (0.030) to 0.60(0.023)
0.200 to 5.20(0.205)
Updated to new POD format by removing table and moving dimensions onto
drawing and adding land pattern.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
10
FN6294.4
December 8, 2015
ISL2100A, ISL2101A
Dual Flat No-Lead Plastic Package (DFN)
L9.3x3
2X
9 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
0.15 C A
A
D
MILLIMETERS
2X
0.15 C B
E
SYMBOL
MIN
0.80
0.90
1.00
-
-
-
0.05
-
0.20 REF
0.20
D
D2
B
A
C
SEATING
PLANE
0.08 C
A3
SIDE VIEW
D2
1
6
2.10
6, 7
-
3.00 BSC
0.80
e
0.95
1.05
6, 7
0.50 BSC
-
k
0.60
-
-
-
L
0.25
0.35
0.45
7
9
2
D2/2
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2
2. N is the number of terminals.
E2/2
3. All dimensions are in millimeters. Angles are in degrees.
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
E2
5. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
NX L
N-1
6. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
NX b
e
(Nd-1)Xe
REF.
BOTTOM VIEW
4
0.10 M C A B
7. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
8. Compliant to JEDEC MO-229-WEED-3 except for dimensions E2
& D2.
9. Tiebar shown (if present) is a non-functional feature and may be
located on any of the 4 sides (or ends).
CL
NX (b)
4, 7
NOTES:
NX k
N
0.30
Rev. 1 3/15
7
(DATUM A)
7
E2
2.00
N
(DATUM B)
5
INDEX
AREA
0.10 C
0.25
-
3.00 BSC
1.85
E
//
NOTES
A
b
TOP VIEW
MAX
A1
A3
5
INDEX
AREA
NOMINAL
(A1)
8 L
4
e
SECTION "C-C"
C C
TERMINAL TIP
FOR ODD TERMINAL/SIDE
11
FN6294.4
December 8, 2015
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