DATASHEET

ISL6700
®
Data Sheet
December 29, 2004
80V/1.25A Peak, Medium Frequency, Low
Cost, Half-Bridge Driver
The ISL6700 is an 80V/1.25A peak, medium frequency, low
cost, half-bridge driver IC available in 8-lead SOIC and
12-lead QFN plastic packages. The low-side and high-side
gate drivers are independently controlled and matched to
25ns. This gives the user maximum flexibility in dead-time
selection and driver protocol. Undervoltage protection on
both the low-side and high-side supplies force the outputs
low. Non-latching, level-shift translation is used to control the
upper drive circuit. Unlike some competitors, the high-side
output returns to its correct state after a momentary
undervoltage of the high-side supply.
Features
• Drives 2 N-Channel MOSFETs in Half-Bridge
Configuration
• Space Saving SO8 and Low RC-S QFN Packages
• Phase Supply Max Voltage to 80VDC
• Bootstrap Supply Max Voltage to 96VDC
• Drives 1000pF Load with Rise and Fall Times Typ. 15ns
• TTL/CMOS Compatible Input Thresholds
• Independent Inputs for Non-Half-Bridge Topologies
• No Start-Up Problems
• Low Power Consumption
Ordering Information
PART
NUMBER
FN9077.6
• Wide Supply Range
TEMP. RANGE
(°C)
PACKAGE
PKG. DWG. #
• Supply Undervoltage Protection
ISL6700IB
-40 to 125
8 Ld SOIC
M8.15
ISL6700IBZ
(See Note)
-40 to 125
8 Ld SOIC
(Pb-free)
M8.15
• QFN Package
- Compliant to JEDEC PUB95 MO-220 QFN
- Quad Flat No Leads - Package Outline
ISL6700IR
-40 to 125
12 Ld 4x4 QFN
L12.4x4
• Pb-Free Available (RoHS Compliant)
ISL6700IRZ
(See Note)
-40 to 125
12 Ld 4x4 QFN
(Pb-free)
L12.4x4
Applications
Add “-T” suffix to part number for tape and reel packaging.
• Telecom/Datacom Power Supplies
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
• Half-Bridge Converters
• Two-Switch Forward Converters
• Active Clamp Forward Converters
Pinouts
VDD
1
8
HB
NC
HB
ISL6700IR (QFN)
TOP VIEW
VDD
ISL6700IB (SOIC)
TOP VIEW
HI
2
7
HO
12
11
10
LI
3
6
HS
VSS
4
5
LO
2
LI
3
EPAD
8 NC
7 HS
4
5
6
LO
NC
9 HO
NC
1
VSS
HI
NOTE: EPAD = Exposed PAD.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002-2004. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL6700
Application Block Diagram
+12V
+48V
VDD
DRIVE
HI
PWM
CONTROLLER
LI
CONTROL
HI
SECONDARY
CIRCUIT
HB
HO
HS
DRIVE
LO
LO
REFERENCE
AND
ISOLATION
ISL6700
VSS
Functional Block Diagram
HB
U/V
LEVEL
SHIFT
HO
HS
HI
TURN-ON
DELAY
LI
LO
DETECTOR
UNDERVOLTAGE
VDD
VSS
EPAD (QFN PACKAGE ONLY)
2
FN9077.6
December 29, 2004
ISL6700
+48V
+12V
PWM
SECONDARY
CIRCUIT
ISL6700
ISOLATION
FIGURE 1. TWO-SWITCH FORWARD CONVERTER
+48V
SECONDARY
CIRCUIT
+12V
PWM
ISL6700
ISOLATION
FIGURE 2. FORWARD CONVERTER WITH AN ACTIVE CLAMP
3
FN9077.6
December 29, 2004
ISL6700
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VDD (Note 1) . . . . . . . . . . . . . . . . . . . -0.3V to 16V
LI and HI Voltages (Note 1) . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V
Voltage on HS (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 80V
Voltage on HB (Note 1) . . . . . . . . . . . . . . . . VHS-0.3V to VHS+VDD
Voltage on LO (Note 1) . . . . . . . . . . . . . . . . . VSS-0.3 to VDD+0.3V
Voltage on HO (Note 1) . . . . . . . . . . . . . . . . VHS-0.3V to VHB+0.3V
Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns
Thermal Resistance (Typical)
Maximum Recommended Operating Conditions
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9V to 15V
Voltage on HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 75V
Voltage on HS (Note 2) . . . . . . . . . .(Repetitive Transient) -1V to 80V
Voltage on HB . . . . . . . . . . . . . . . . . . . . . . . . . . VHS +7.5V to VHS +VDD
θJA (°C/W)
θJC (°C/W)
SOIC (Note 3) . . . . . . . . . . . . . . . . . . .
95
N/A
QFN (Note 4) . . . . . . . . . . . . . . . . . . . .
49
7
Max Power Dissipation at 25°C in Free Air (SOIC, Note 3). 1.316W
Max Power Dissipation at 25°C in Free Air (QFN, Note 4) . .2.976W
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Maximum Junction Temperature Range . . . . . . . . .-40°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300°C
(SOIC - Lead Tips Only)
For Recommended soldering conditions see Tech Brief TB389.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the recommended operating conditions of this specification is not implied.
NOTES:
1. All voltages referenced to VSS unless otherwise specified.
2. Based on VDD=15V. The magnitude of the allowable negative transient on the HS pin is a function of the VDD supply voltage. VHS<15.6VVDD+VF, where VHS is the magnitude of the allowable negative transient and VF is the forward voltage drop of the bootstrap diode.
3. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. θJC, the
“case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Electrical Specifications
VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified
TJ = -40°C TO
125°C
TJ = 25°C
PARAMETERS
MIN
TYP
MAX
MIN
MAX
UNITS
LI = 0 or VDD
-
1.9
2.2
-
2.4
mA
SYMBOL
TEST CONDITIONS
SUPPLY CURRENTS & UNDERVOLTAGE PROTECTION
VDD Quiescent Current
IDD
VDD Operating Current
IDDO
f = 50kHz
-
2.0
2.2
-
2.5
mA
VDD Operating Current
IDDO
f = 500kHz
-
2.5
3.0
-
4.0
mA
HB Off Quiescent Current
IHBL
HI = 0
-
1.25
1.5
-
1.8
mA
HB On Quiescent Current
IHBH
HI = VDD
-
170
240
-
250
µA
HB Operating Current
IHBO
f = 50kHz, CL = 1000pF
-
1.45
1.8
-
2.0
mA
HB Operating Current
IHBO
f = 500kHz, CL = 1000pF
-
2.4
2.8
-
3.0
mA
HS Leakage Current
IHLK
VHS = 80V
VHB = 96V
-
-
1
-
1
µA
VDD Rising Undervoltage Threshold
VDDUV+
6.8
7.6
8.25
6.5
8.5
V
VDD Falling Undervoltage Threshold
VDDUV-
6.5
7.1
7.8
6.25
8.1
V
Undervoltage Hysteresis
UVHYS
0.17
0.45
0.75
0.15
0.90
V
HB Undervoltage Threshold
VHBUV
Referenced to HS
4.8
5.3
6.5
4.0
7.5
V
INPUT PINS: LI and HI
Low Level Input Voltage
VIL
Full Operating Conditions
0.8
1.6
-
0.8
-
V
High Level Input Voltage
VIH
Full Operating Conditions
-
1.7
2.2
-
2.2
V
-
100
-
-
-
mV
Input Voltage Hysteresis
Low Level Input Current
IIL
VIN = 0V, Full Operating Conditions
-70
-60
-30
-80
-30
µA
High Level Input Current
IIH
VIN = 5V, Full Operating Conditions
30
115
130
30
145
µA
4
FN9077.6
December 29, 2004
ISL6700
Electrical Specifications
VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified (Continued)
TJ = -40°C TO
125°C
TJ = 25°C
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNITS
GATE DRIVER OUTPUT PINS: LO & HO
Low Level Output Voltage
VOL
IOUT = 0A
-
-
0.1
-
0.1
V
High Level Output Voltage
VDD-VOH
IOUT = 0A
-
-
0.1
-
0.1
V
Peak Pullup Current
IO+
VOUT = 0V
-
1.4
-
-
-
A
Peak Pulldown Current
IO -
VOUT = 12V
-
1.3
-
-
-
A
Switching Specifications
VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified
PARAMETERS
SYMBOL
TEST
CONDITIONS
TJ = -40°C
TO 125°C
TJ = 25°C
MIN
TYP
MAX
MIN
MAX
UNITS
Lower Turn-off Propagation Delay
(LI Falling to LO Falling)
tLPHL
-
45
50
-
65
ns
Upper Turn-off Propagation Delay
(HI Falling to HO Falling)
tHPHL
-
60
75
-
90
ns
Lower Turn-on Propagation Delay
(LI Rising to LO Rising)
tLPLH
-
75
82
-
95
ns
Upper Turn-on Propagation Delay
(HI Rising to HO Rising)
tHPLH
-
70
75
-
95
ns
Deadtime, (tHPLH - tLPHL)
DHtON
0
24
-
0
-
ns
Deadtime, (tLPLH - tHPHL)
DLtON
0
17
-
0
-
ns
Rise Time
tR
-
5
20
-
25
ns
Fall Time
tF
-
5
20
-
25
ns
Delay Matching: Lower Turn-On and Upper Turn-Off
tMON
-
8
20
-
25
ns
Delay Matching: Lower Turn-Off and Upper Turn-On
tMOFF
-
-15
25
-
30
ns
LI, HI switched simultaneously
Pin Descriptions
SYMBOL
VDD
DESCRIPTION
Positive supply to control logic and lower gate drivers. De-couple this pin to VSS. Connect anode of bootstrap diode to this pin.
HI
Logic level input that controls the HO output.
LI
Logic level input that controls the LO output.
VSS
Chip negative supply, generally will be ground.
LO
Low-side output. Connect to gate of low-side power MOSFET.
HS
High-side source connection. Connect to source of high-side power MOSFET. Connect negative side of bootstrap capacitor to this
pin.
HO
High-side output. Connect to gate of high-side power MOSFET.
HB
High-side bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive
side of bootstrap capacitor to this pin.
EPAD
Exposed pad. Connect to ground or float. The EPAD is electrically isolated from all other pins.
5
FN9077.6
December 29, 2004
ISL6700
Timing Diagrams
LI
HI
HI,
LI
tHPLH ,
tLPLH
tHPHL,
tLPHL
LO
tMOFF
tMON
HO,
LO
HO
FIGURE 3.
6
FIGURE 4.
FN9077.6
December 29, 2004
ISL6700
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L12.4x4
12 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220-VGGC ISSUE C)
MILLIMETERS
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
0.80
0.90
1.00
-
A1
-
-
0.05
-
A2
-
-
1.00
A3
b
0.23
D
0.28
9
0.38
5, 8
4.00 BSC
D1
D2
9
0.20 REF
-
3.75 BSC
1.95
2.10
9
2.25
7, 8
E
4.00 BSC
-
E1
3.75 BSC
9
E2
1.95
e
2.10
2.25
7, 8
0.80 BSC
-
k
0.25
-
-
-
L
0.35
0.60
0.75
8
L1
-
-
0.15
10
N
12
2
Nd
3
3
Ne
3
3
P
-
-
0.60
9
θ
-
-
12
9
Rev. 1 5/03
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
7
FN9077.6
December 29, 2004
ISL6700
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
N
INDEX
AREA
0.25(0.010) M
H
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
B M
E
INCHES
-B-
1
2
SYMBOL
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
α
e
A1
B
0.25(0.010) M
C
C A M
B S
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
MILLIMETERS
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.1890
0.1968
4.80
5.00
3
E
0.1497
0.1574
3.80
4.00
4
0.050 BSC
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
8o
0o
N
NOTES:
MAX
A1
e
0.10(0.004)
MIN
α
8
0o
8
7
8o
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
8
FN9077.6
December 29, 2004
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