DATASHEET

DATASHEET
100V, 1.25A Peak, High Frequency Half-Bridge Drivers
ISL89400, ISL89401
Features
The ISL89400, ISL89401 are 100V, high frequency, half-bridge
N-Channel power MOSFET driver ICs. They are based on the
popular HIP2100, HIP2101 half-bridge drivers, but offer
several performance improvements. The ISL89400 has
additional input hysteresis for superior operation in noisy
environments and the inputs of the ISL89401 (like those of the
ISL89400) can now safely swing to the VDD supply rail. Finally,
both parts are available in a very compact 9 Ld DFN package
and an 8 Ld SOIC to minimize the required PCB footprint.
• Drives N-channel MOSFET half-bridge
Applications
• Fast propagation times for multi-MHz circuits
• Space saving DFN package
• DFN package compliant with 100V conductor spacing
guidelines per IPC-2221
• Pb-free (RoHS compliant)
• Bootstrap supply maximum voltage to 114VDC
• On-chip 1Ω bootstrap diode
• Drives 1nF load with typical rise/fall times of 16ns
• Telecom half-bridge converters
• CMOS compatible input thresholds (ISL89400)
• Telecom full-bridge converters
• 3.3V/TTL compatible input thresholds (ISL89401)
• Two-switch forward converters
• Independent inputs provide flexibility
• Active-clamp forward converters
• No start-up problems
• Class-D audio amplifiers
• Outputs unaffected by supply glitches, HS ringing below
ground or HS slewing at high dV/dt
TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
PART NUMBER
INPUT THRESHOLDS
ISL89400
CMOS Compatible
ISL89401
3.3V/TTL Compatible
• Low power consumption
• Wide supply voltage range (9V to 14V)
• Supply undervoltage protection
• 4.0Ω typical output pull-up/pull-down resistance
Application Block Diagram
+12V
+100V
SECONDARY
CIRCUIT
VDD
HB
DRIVE
HI
PWM
CONTROLLER
LI
CONTROL
HI
HO
HS
DRIVE
LO
ISL89400
ISL89401
VSS
LO
REFERENCE
AND
ISOLATION
FIGURE 1. APPLICATION BLOCK DIAGRAM
December 4, 2015
FN6614.3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2007-2009, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL89400, ISL89401
Ordering Information
PART NUMBER
(Notes 3, 4)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
ISL89400AR3Z (Note 1)
9400
-40 to +125
9 Ld 3x3 DFN
L9.3x3
ISL89401AR3Z (Note 1)
9401
-40 to +125
9 Ld 3x3 DFN
L9.3x3
ISL89400ABZ (Note 2)
89400 ABZ
-40 to +125
8 Ld SOIC
M8.15
ISL89401ABZ (Note 2)
89401 ABZ
-40 to +125
8 Ld SOIC
M8.15
NOTES:
1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. Add “-T” suffix for 2.5k unit or add “-TK” suffix for 1k unit tape and reel. Please refer to TB347 for details on reel specifications.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), please see product information page for ISL89400, ISL89401. For more information on MSL, please see tech
brief TB363.
Pin Configurations
ISL89400, ISL89401
(9 LD DFN)
TOP VIEW
ISL89400, ISL89401
(8 LD SOIC)
TOP VIEW
VDD
1
8
LO
HB
2
7
VSS
HO
3
6
LI
HS
4
5
HI
VDD
9 LO
1
8 VSS
HB
2
HO
3
6 HI
HS
4
5 NC
EPAD
7 LI
NOTE: EPAD = Exposed PAD.
Pin Descriptions
SYMBOL
DESCRIPTION
VDD
Positive supply to lower gate driver. Bypass this pin to VSS.
HB
High-side bootstrap supply. External bootstrap capacitor is required. Connect positive side of bootstrap capacitor to this pin. Bootstrap
diode is on-chip.
HO
High-side output. Connect to gate of high-side power MOSFET.
HS
High-side source connection. Connect to source of high-side power MOSFET. Connect negative side of bootstrap capacitor to this pin.
HI
High-side input.
LI
Low-side input.
VSS
Chip negative supply, which will generally be ground.
LO
Low-side output. Connect to gate of low-side power MOSFET.
NC
No connect.
EPAD
Exposed pad. Connect to ground or float. The EPAD is electrically isolated from all other pins.
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ISL89400, ISL89401
Functional Block Diagram
HB
VDD
UNDERVOLTAGE
HO
LEVEL SHIFT
DRIVER
HS
HI
ISL89401
UNDERVOLTAGE
LO
ISL89401
DRIVER
LI
VSS
EPAD (DFN PACKAGE ONLY)
*EPAD = EXPOSED PAD. THE EPAD IS ELECTRICALLY ISOLATED FROM ALL OTHER
PINS. FOR BEST THERMAL PERFORMANCE, CONNECT THE EPAD TO THE PCB
POWER GROUND PLANE.
FIGURE 2. FUNCTIONAL BLOCK DIAGRAM
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ISL89400, ISL89401
+48V
+12V
SECONDARY
CIRCUIT
ISL89400
ISL89401
PWM
ISOLATION
FIGURE 3. TWO-SWITCH FORWARD CONVERTER
+48V
SECONDARY
CIRCUIT
+12V
PWM
ISL89400
ISL89401
ISOLATION
FIGURE 4. FORWARD CONVERTER WITH AN ACTIVE-CLAMP
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ISL89400, ISL89401
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VDD, VHB - VHS (Note 6). . . . . . . . . . . . . . . . . . -0.3V to 18V
LI and HI Voltages (Note 6) . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V
Voltage on LO (Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V
Voltage on HO (Note 6) . . . . . . . . . . . . . . . . . . . . . VHS - 0.3V to VHB + 0.3V
Voltage on HS (Continuous) (Note 6) . . . . . . . . . . . . . . . . . . . . . -1V to 110V
Voltage on HB (Note 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118V
Average Current in VDD to HB Diode . . . . . . . . . . . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
9 Ld DFN (Notes 7, 9). . . . . . . . . . . . . . . . . .
55
3.5
8 Ld SOIC (Note 8, 10) . . . . . . . . . . . . . . . . .
107
50
Max Power Dissipation at +25°C in Free Air (Note 7). . . . . . . . . . . . . . 2.27W
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .see link TB493
Maximum Recommended Operating
Conditions
Supply Voltage, VDD (Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9V to 14V
Voltage on HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to 100V
Voltage on HS . . . . . . . . . . . . . . . . . . . . . .(Repetitive Transient) -5V to 105V
Voltage on HB . . . . . . . . . VHS + 8V to VHS + 14V and VDD - 1V to VDD + 100V
HS Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <50V/ns
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. The ISL89400 and ISL89401 are capable of derated operation at supply voltages exceeding 14V. Figure 24 shows the high-side voltage derating curve
for this mode of operation.
6. All voltages referenced to VSS, unless otherwise specified.
7. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features.See Tech
Brief TB379.
8. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
9. For JC, the “case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379 for details.
10. For JC, the “case temp” location is taken at the package top center.
Electrical Specifications VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, unless otherwise specified. Parameters with MIN
and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits at –40°C and +125°C are established by characterization
and are not production tested.
TJ = +25°C
PARAMETERS
SYMBOL
TEST CONDITIONS
TJ = -40°C to +125°C
MIN
TYP
MAX
MIN
MAX
UNIT
SUPPLY CURRENTS
VDD Quiescent Current
IDD
ISL89400; LI = HI = 0V
-
0.1
0.25
-
0.3
mA
VDD Quiescent Current
IDD
ISL89401; LI = HI = 0V
-
0.3
0.45
-
0.55
mA
VDD Operating Current
IDDO
ISL89400; f = 500kHz
-
1.6
2.2
-
2.7
mA
VDD Operating Current
IDDO
ISL89401; f = 500kHz
-
1.9
2.5
-
3
mA
Total HB Quiescent Current
IHB
LI = HI = 0V
-
0.1
0.15
-
0.2
mA
Total HB Operating Current
IHBO
f = 500kHz
-
2.0
2.5
-
3
mA
HB to VSS Current, Quiescent
IHBS
LI = HI = 0V; VHB = VHS = 114V
-
0.05
1
-
10
µA
HB to VSS Current, Operating
IHBSO
f = 500kHz; VHB = VHS = 114V
-
0.9
-
-
-
mA
INPUT PINS
Low Level Input Voltage Threshold
VIL
ISL89400
3.7
4.4
-
2.7
-
V
Low Level Input Voltage Threshold
VIL
ISL89401
1.4
1.8
-
1.2
-
V
High Level Input Voltage Threshold
VIH
ISL89400
-
6.6
7.4
-
8.4
V
High Level Input Voltage Threshold
VIH
ISL89401
-
1.8
2.2
-
2.4
V
VIHYS
ISL89400
-
2.2
-
-
-
V
-
210
-
100
500
kΩ
Input Voltage Hysteresis
Input Pull-Down Resistance
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FN6614.3
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ISL89400, ISL89401
Electrical Specifications VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, unless otherwise specified. Parameters with MIN
and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits at –40°C and +125°C are established by characterization
and are not production tested. (Continued)
TJ = +25°C
PARAMETERS
SYMBOL
TEST CONDITIONS
TJ = -40°C to +125°C
MIN
TYP
MAX
MIN
MAX
UNIT
6.8
7.3
7.8
6.5
8.1
V
UNDERVOLTAGE PROTECTION
VDD Rising Threshold
VDDR
VDD Threshold Hysteresis
VDDH
-
0.6
-
-
-
V
HB Rising Threshold
VHBR
6.2
6.9
7.5
5.9
7.8
V
HB Threshold Hysteresis
VHBH
-
0.6
-
-
-
V
BOOTSTRAP DIODE
Low Current Forward Voltage
VDL
IVDD-HB = 100µA
-
0.5
0.6
-
0.7
V
High Current Forward Voltage
VDH
IVDD-HB = 100mA
-
0.7
0.9
-
1
V
Dynamic Resistance
RD
IVDD-HB = 100mA
-
0.8
1
-
1.5
Ω
LO GATE DRIVER
Low Level Output Voltage
VOLL
ILO = 100mA
-
0.4
0.5
-
0.7
V
High Level Output Voltage
VOHL
ILO = -100mA, VOHL = VDD - VLO
-
0.4
0.5
-
0.7
V
Peak Pull-Up Current
IOHL
VLO = 0V
-
1.25
-
-
-
A
Peak Pull-Down Current
IOLL
VLO = 12V
-
1.25
-
-
-
A
Low Level Output Voltage
VOLH
IHO = 100mA
-
0.4
0.5
-
0.7
V
High Level Output Voltage
VOHH
IHO = -100mA, VOHH = VHB - VHO
-
0.4
0.5
-
0.7
V
Peak Pull-Up Current
IOHH
VHO = 0V
-
1.25
-
-
-
A
Peak Pull-Down Current
IOLH
VHO = 12V
-
1.25
-
-
-
A
HO GATE DRIVER
Switching Specifications
VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, unless otherwise specified. Parameters with MIN
and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits at –40°C and +125°C are established by characterization
and are not production tested.
PARAMETERS
SYMBOL
TEST
CONDITIONS
TJ = +25°C
TJ = -40°C to +125°C
MIN
TYP
MAX
MIN
MAX
UNIT
Lower Turn-Off Propagation Delay (LI Falling to LO Falling)
tLPHL
-
34
50
-
60
ns
Upper Turn-Off Propagation Delay (HI Falling to HO Falling)
tHPHL
-
31
50
-
60
ns
Lower Turn-On Propagation Delay (LI Rising to LO Rising)
tLPLH
-
39
50
-
60
ns
Upper Turn-On Propagation Delay (HI Rising to HO Rising)
tHPLH
-
39
50
-
60
ns
Delay Matching: Upper Turn-Off to Lower Turn-On
tMON
1
8
-
-
16
ns
Delay Matching: Lower Turn-Off to Upper Turn-On
tMOFF
1
6
-
-
16
ns
Either Output Rise/Fall Time (10% to 90%/90% to 10%)
tRC,tFC
CL = 1nF
-
16
-
-
-
ns
CL = 0.1µF
-
0.8
1.0
-
1.2
µs
Either Output Rise/Fall Time (3V to 9V/9V to 3V)
tR,tF
Minimum Input Pulse Width that Changes the Output
tPW
-
-
-
-
50
ns
Bootstrap Diode Turn-On or Turn-Off Time
tBS
-
10
-
-
-
ns
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ISL89400, ISL89401
Timing Diagrams
LI
HI,
LI
HI
tHPLH ,
tLPLH
tHPHL,
tLPHL
LO
tMOFF
tMON
HO,
LO
HO
FIGURE 5. PROPAGATION DELAYS
FIGURE 6. DELAY MATCHING
Typical Performance Curves
10.0
10.0
T = -40°C
T = +25°C
1.0
IDDO (mA)
IDDO (mA)
T = -40°C
T = +125°C
T = +25°C
T = +125°C
1.0
T = +150°C
T = +150°C
0.1
10k
100k
0.1
1M
10k
100k
FREQUENCY (Hz)
1M
FREQUENCY (Hz)
FIGURE 7. ISL89400 IDD OPERATING CURRENT vs FREQUENCY
FIGURE 8. ISL89401 IDD OPERATING CURRENT vs FREQUENCY
10.00
10.00
T = +125°C
T = -40°C
1.00
T = +25°C
IHBO (mA)
IHBO (mA)
1.00
0.10
T = +125°C
T = +150°C
0.10
T = -40°C
T = +150°C
T = +25°C
0.01
10k
100k
FREQUENCY (Hz)
FIGURE 9. IHB OPERATING CURRENT vs FREQUENCY
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1M
0.01
10k
100k
1M
FREQUENCY (Hz)
FIGURE 10. IHBS OPERATING CURRENT vs FREQUENCY
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ISL89400, ISL89401
Typical Performance Curves
500
(Continued)
450
VDD = VHB = 9V
400
VDD = VHB = 12V
350
300
250
350
-50
0
50
VDD = VHB = 12V
300
250
200
VDD = VHB = 14V
200
150
VDD = VHB = 9V
400
VOLL, VOLH (mV)
VOLL, VOLH (mV)
450
100
150
150
VDD = VHB = 14V
-50
0
TEMPERATURE (°C)
FIGURE 11. HIGH LEVEL OUTPUT VOLTAGE vs TEMPERATURE
VHBH
0.55
7.2
VHBR
7.0
0.50
0.45
VDDH
0.40
-50
0
50
100
150
-50
0
FIGURE 13. UNDERVOLTAGE LOCKOUT THRESHOLD vs
TEMPERATURE
55
tLPLH, tLPHL, tHPLH, tHPHL (ns)
45
40
tHPLH
35
30
tLPHL
25
20
tHPHL
-50
0
50
100
150
TEMPERATURE (°C)
FIGURE 15. ISL89400 PROPAGATION DELAYS vs TEMPERATURE
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100
150
FIGURE 14. UNDERVOLTAGE LOCKOUT HYSTERESIS vs
TEMPERATURE
tLPLH
50
50
TEMPERATURE (°C)
TEMPERATURE (°C)
tLPLH, tLPHL, tHPLH, tHPHL (ns)
150
0.60
VDDR
7.4
6.8
100
FIGURE 12. LOW LEVEL OUTPUT VOLTAGE vs TEMPERATURE
VDDH, VHBH (V)
VDDR, VHBR (V)
7.6
50
TEMPERATURE (°C)
55
tLPLH
50
45
tHPLH
40
35
30
tHPHL
25
20
-50
0
tLPHL
50
100
150
TEMPERATURE (°C)
FIGURE 16. ISL89401 PROPAGATION DELAYS vs TEMPERATURE
FN6614.3
December 4, 2015
ISL89400, ISL89401
Typical Performance Curves
(Continued)
10
10
9
tMOFF
tMON, tMOFF (ns)
tMON, tMOFF (ns)
9
8
7
6
5
4
3
0
50
tMON
7
6
5
4
3
tMON
-50
8
100
2
150
tMOFF
-50
0
1.25
1.25
1.00
1.00
0.75
0.50
0.25
0.50
0.25
0
2
4
6
8
10
0
12
0
2
4
IDD, IHB (µA)
IHB
5
10
15
VDD, VHB (V)
FIGURE 21. ISL89400 QUIESCENT CURRENT vs VOLTAGE
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8
10
12
FIGURE 20. PEAK PULL-DOWN CURRENT vs OUTPUT VOLTAGE
IDD
0
6
VLO, VHO (V)
FIGURE 19. PEAK PULL-UP CURRENT vs OUTPUT VOLTAGE
IDD, IHB (µA)
150
0.75
VLO, VHO (V)
260
240
220
200
180
160
140
120
100
80
60
40
20
0
100
FIGURE 18. ISL89401 DELAY MATCHING vs TEMPERATURE
IOLL, IOLH (A)
IOHL, IOHH (A)
FIGURE 17. ISL89400 DELAY MATCHING vs TEMPERATURE
0
50
TEMPERATURE (°C)
TEMPERATURE (°C)
20
340
320
300
280
260
240
220
200
180
160
140
120
100
80
60
40
20
0
IDD
IHB
0
5
10
15
20
VDD, VHB (V)
FIGURE 22. ISL89401 QUIESCENT CURRENT vs VOLTAGE
FN6614.3
December 4, 2015
ISL89400, ISL89401
Typical Performance Curves
(Continued)
120
VHS TO VSS VOLTAGE (V)
FORWARD CURRENT (A)
1.00
0.10
0.01
1.10-3
1.10-4
1.10-5
1.10-6
0.3
0.4
0.5
0.6
0.7
0.8
100
80
60
40
20
0
12
13
14
15
16
VDD to VSS VOLTAGE (V)
FORWARD VOLTAGE (V)
FIGURE 23. BOOTSTRAP DIODE I-V CHARACTERISTICS
FIGURE 24. VHS VOLTAGE vs VDD VOLTAGE
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
CHANGE
December 4, 2015
FN6614.3
Updated datasheet to the latest Intersil standards.
Moved Note 5 from “Absolute Maximum Ratings” section to “Maximum Recommended Operating
Conditions”section.
Updated Theta JC on page 5 for DFN from “7.5” to “3.5”.
Added Theta JC on page 5 for SOIC.
Updated Theta JA on page 5 for SOIC from “115” to “107”.
Added Note 10 on page 5.
Updated last sentence in the “Electrical Specifications” table title area.
Added more verbiage to “Switching Specifications” table title area.
Added Revision History and About Intersil sections
Updated package outline drawings to the latest revisions. Changes are as follows:
M8.15
-Updated to new POD format by removing table and moving dimensions onto drawing and adding land
pattern
-Changed in Typical Recommended Land Pattern the following:
2.41(0.095) to 2.20(0.087)
0.76 (0.030) to 0.60(0.023)
0.200 to 5.20(0.205)
-Changed Note 1 “1982” to “1994”
L9.3x3
-Tiebar Note 9 added: Tiebar shown (if present) is a non-functional feature and may be located on any of the
4 sides (or ends).
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
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FN6614.3
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ISL89400, ISL89401
Package Outline Drawing
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 1/12
DETAIL "A"
1.27 (0.050)
0.40 (0.016)
INDEX
6.20 (0.244)
5.80 (0.228)
AREA
0.50 (0.20)
x 45°
0.25 (0.01)
4.00 (0.157)
3.80 (0.150)
1
2
8°
0°
3
0.25 (0.010)
0.19 (0.008)
SIDE VIEW “B”
TOP VIEW
2.20 (0.087)
SEATING PLANE
5.00 (0.197)
4.80 (0.189)
1.75 (0.069)
1.35 (0.053)
1
8
2
7
0.60 (0.023)
1.27 (0.050)
3
6
4
5
-C-
1.27 (0.050)
0.51(0.020)
0.33(0.013)
SIDE VIEW “A
0.25(0.010)
0.10(0.004)
5.20(0.205)
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1994.
2. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
3. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.
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11
FN6614.3
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ISL89400, ISL89401
Dual Flat No-Lead Plastic Package (DFN)
L9.3x3
2X
9 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
0.15 C A
A
D
MILLIMETERS
2X
0.15 C B
E
SYMBOL
MIN
0.80
0.90
1.00
-
-
-
0.05
-
0.20 REF
0.20
D
D2
B
A
C
SEATING
PLANE
0.08 C
A3
SIDE VIEW
D2
1
6
2.10
6, 7
-
3.00 BSC
0.80
e
0.95
1.05
6, 7
0.50 BSC
-
k
0.60
-
-
-
L
0.25
0.35
0.45
7
9
2
D2/2
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2
2. N is the number of terminals.
E2/2
3. All dimensions are in millimeters. Angles are in degrees.
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
E2
5. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
NX L
N-1
6. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
NX b
e
(Nd-1)Xe
REF.
BOTTOM VIEW
4
0.10 M C A B
7. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
8. Compliant to JEDEC MO-229-WEED-3 except for dimensions E2
& D2.
9. Tiebar shown (if present) is a non-functional feature and may be
located on any of the 4 sides (or ends).
CL
NX (b)
4, 7
NOTES:
NX k
N
0.30
Rev. 1 3/15
7
(DATUM A)
7
E2
2.00
N
(DATUM B)
5
INDEX
AREA
0.10 C
0.25
-
3.00 BSC
1.85
E
//
NOTES
A
b
TOP VIEW
MAX
A1
A3
5
INDEX
AREA
NOMINAL
(A1)
8 L
4
e
SECTION "C-C"
C C
TERMINAL TIP
FOR ODD TERMINAL/SIDE
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in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
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12
FN6614.3
December 4, 2015
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