DATASHEET

CA3282
TM
Octal Low Side Power Driver
with Serial Bus Control
June 1998
Features
Description
• Output Current Drive Capability
The CA3282 is a logic controlled, eight channel octal power
driven. The serial peripheral interface (SPI) utilized by the
CA3282 is a serial synchronous bus compatible with Intersil
CDP68HC05, or equivalent, microcomputers. As shown in
the Block Diagram for the CA3282 each of the open drain
NDMOS output drivers has individual protection for overvoltage and over-current. Each output channel has separate
output latch control with fault unlatch and diagnostic feedback. Under normal ON conditions, each output driver is in a
low, saturation state. Comparators in the diagnostic circuitry
monitor the output drivers to determine if an out of saturation
condition exists. If a comparator senses a fault, the respective output driver is unlatched. In addition, over current protection is provided with current limiting in each output,
independent of the diagnostic feedback loop.
- All Outputs ON, Equal . . . . . . . . . . . . . . 0.625A Each
- Per Output Individually . . . . . . . . . . . . . . . . . 1A Each
- Maximum Total of Outputs ON . . . . . . . . . . . . . . . . 5A
• High Voltage Power BiMOS Outputs
- 8 Open Drain NDMOS Drivers
- Individual Output Latch
- Over-Current Limit Protection . . . . . . . . . . . . . 1.05A
- Over-Voltage Clamp Protection . . . . . . . . . . . . . . 30V
• High Speed CMOS Logic Control
- Low Quiescent IDD Current . . . . . . . . . . . . . . . . . 5mA
- SPI Bus Controlled Interface
The CA3282 is fabricated in a Power BiMOS IC process, and is
intended for use in automotive and other applications having a
wide range of temperature and electrical stress conditions. It is
particularly suited for driving lamps, relays, and solenoids in
applications where low operating power, high breakdown voltage, and high output current at high temperatures is required.
- Individual Fault Unlatch and Feedback
- Common Reset Line
• Operating Temperature Range . . . . . . . -40oC to 125oC
Applications
The CA3282 is supplied in 15 lead plastic SIP package with
lead forms for either vertical or surface mount.
• Automotive and Industrial Systems
• Solenoids, Relays and Lamp Drivers
Ordering Information
• Logic and µP Controlled Drivers
PART
NUMBER
• Robotic Controls
Pinout
TEMP.
RANGE(oC)
PACKAGE AND
LEAD FORM
CA3282AS1
-40 to 125
15 Ld Plastic SIP
Staggered Vertical
Z15.05A
CA3282AS2
-40 to 125
15 Ld Plastic SIP
Surface Mount
Z15.05B
Block Diagram
CA3282 (SIP)
TOP VIEW
OUTPUT #0
(1 OF 8)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
OUTPUT 4
OUTPUT 5
OUTPUT 6
OUTPUT 7
RESET
VDD
MOSI
SCK
MISO
VSS
MOSI
SCK
CE
MISO
CE
OUTPUT 0
OUTPUT 1
OUTPUT 2
OUTPUT 3
RESET
SPI INTERFACE CIRCUIT
NOTE:
HEAT SINK TAB
INTERNALLY
CONNECTED TO
GROUND (VSS)
PKG
NO.
SHIFT
REGISTER
OUTPUT
LATCH
CURRENT
LIMIT
CONTROL
LOGIC
DIAGNOSTIC
CIRCUITRY
TO DRIVERS
1 THRU 7
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1
File Number
2767.6
CA3282
Absolute Maximum Ratings
Thermal Information
Output Voltage, VO (Note 1) . . . . . . . . . . . . . . . . . . . . . VOC (Clamp)
Output Load Current, ILOAD (Per Output, Individual) . . . . . . . . . 1A
Output Load Current, ILOAD (All 8 Outputs ON, Equal IOUT) . . . . .
0.625A
Output Load Current, ILOAD (Max. Total of Outputs ON) . . . . 5.0A
DC Logic Supply, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.7 to +7V
Thermal Resistance (Typical, Note 2)
Plastic SIP
No Heat Sink . . . . . . . . . . . . . . . . . . .
Infinite Heat Sink . . . . . . . . . . . . . . . . .
Power Dissipation
θJA(oC/W)
θJC(oC/W)
45
N/A
N/A
3
Up to 125oC w/o Heat Sink . . . . . . . . . . . . . . . . . . . . . . . . 0.56W
Above 125oC w/o Heat Sink . . . . . . .Derate Linearly at 22mW/oC
Up to 125oC w/Infinite Heat Sink. . . . . . . . . . . . . . . . . . . . 8.33W
Above 125oC w/Infinite Heat Sink . . . Derate Linearly at 333mW/oC
Maximum Storage Temperature Range . . . . . . . . . -55oC to 150oC
Maximum Lead Temperature (Soldering, 10s). . . . . . . . . . . . . . . 265oC
Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . -40oC to 125oC
Junction Temperature Range . . . . . . . . . . . . . . . . . -40oC to 150oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. The MOSFET Output Drain is internally clamped with a Drain-to-Gate zener diode that turns-on the MOSFET; holding the Drain at the
Output Clamp Voltage, VOC.
2. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
VDD = 5V, TA = -40oC to 125oC, Unless Otherwise Specified
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Quiescent Supply Current, ON
IDD
All Outputs ON, 0.5A Load Per Output
-
5
10
mA
Quiescent Supply Current, OFF
IDD
All Outputs OFF
-
0.2
-
mA
Output Clamping Voltage
VOC
ILOAD = 0.5A, Output Programmed OFF
27
32
40
V
Output Clamping Energy
EOC
ILOAD = 0.5A, Output ON
20
-
-
mJ
VO = 24V
-
150
1000
µA
VO = 14V
-
150
500
µA
Output Leakage Current
IO LEAK
Output Programmed OFF
VO = 5V
-
150
200
µA
Output ON Resistance
rDS(ON)
ILOAD = 0.5A (Note 3)
-
-
1
Ω
Output Current Limit
IO LIMIT
Output Programmed ON, VOUT > 3V
1.05
1.5
-
A
-
1
10
µs
Turn-On Delay
Turn-Off Delay
Fault Reference Voltage
Fault Reset Delay (After CE Low
to High Transition)
Output OFF Voltage
LOGIC INPUTS
tPHL
IO = 500mA, No Reactive Load
tPLH
IO = 500mA, No Reactive Load
VOREF
tUD
VOFF
-
2
10
µs
Output Programmed ON, Fault Detected
If VO > VOREF
1.6
1.8
2.0
V
See Figure 1
50
80
250
µs
-
0
1
V
Output Programmed OFF, Output Pin
Floating
(MOSI, CE, SCK and RESET)
Threshold Voltage at Falling
Edge
VT-
VDD = 5V ± 10%
0.2VDD
0.3VDD
-
V
Threshold Voltage at Rising
Edge
VT+
VDD = 5V ± 10%
-
0.6VDD
0.7VDD
V
Hysteresis Voltage
VH
VT+ - VT-
0.85
1.4
2.25
V
-10
-
+10
µA
Input Current
II
VDD = 5.5V, 0 < VI < VDD
Input Capacitance
CI
0 < VI < VDD
-
-
20
pF
Output LOW Voltage
VOL
IOL = 1.6mA
-
0.2
0.4
V
Output HIGH Voltage
VOH
IOL = 0.8mA
VDD
- 1.3V
VDD
- 0.2V
-
V
LOGIC OUTPUT
(MISO)
2
CA3282
Electrical Specifications
PARAMETER
VDD = 5V, TA = -40oC to 125oC, Unless Otherwise Specified (Continued)
SYMBOL
Output Three State Leakage
Current
Output Capacitance
TEST CONDITIONS
IOL
MIN
TYP
MAX
UNITS
-10
-
+10
µA
-
-
20
pF
VDD = 5.25V, 0 < VO < VDD ,
CE Pin Held High
COUT
Serial Peripheral Interface Timing
PARAMETER
0 < VO < VDD, CE Pin Held High
(See Figure 1B)
SYMBOL
Operating Frequency
TEST CONDITIONS
fOPER
MIN
TYP
MAX
UNITS
D.C.
Note 4
3.0
MHz
Enable Lead Time
(2)
tLEAD
-
<100
200
ns
Enable Lag Time
(3)
tLAG
-
<100
200
ns
Clock HIGH Time
(4)
twSCK
-
50
100
ns
-
50
100
ns
H
Clock LOW Time
(5)
twSCK
L
Data Setup Time
(6)
tSU
-
20
50
ns
Data Hold Time
(7)
tH
-
20
50
ns
Enable Time
(8)
tEN
-
50
100
ns
Disable Time
(9)
tDIS
-
150
300
ns
Data Valid Time
(10)
tV
-
75
150
ns
Output Data Hold Time
(11)
tHO
0
50
-
ns
Rise Time (MISO Output)
(12)
trSO
VDD = 20% to 70%, CL = 200pF
-
35
100
ns
Rise Time SPI Inputs (SCK, MOSI, CE)
(12)
trSI
VDD = 20% to 70%, CL = 200pF
-
-
50
ns
Fall Time (MISO Output)
(13)
tfSO
VDD = 70% to 20%, CL = 200pF
-
45
100
ns
Fall Time SPI Inputs (SCK, MOSI, CE)
(13)
tfSI
VDD = 70% to 20%, CL = 200pF
-
-
50
ns
NOTES:
3. Refer to Figure 4A for IOUT current vs VSAT voltage. Typical rDS(ON) values are given for -40oC, 25oC, 105oC and 125oC temperatures.
4. The Maximum Operating Frequency is typically greater than 10MHz but it is application limited primarily by external SPI input rise/fall
times and MISO output loading.
Timing Diagrams
CE
SCK
(CPOL = 0, CPHA = 1)
MSB
6
5
4
3
2
1
INTERNAL STROBE FOR DATA CAPTURE
FIGURE 1A. DATA AND CLOCK TIMING DIAGRAM
3
LSB
CA3282
Timing Diagrams
(Continued)
CE
(INPUT)
(2)
(4)
(1)
(13)
(3)
(12)
SCK
(INPUT)
MISO
(OUTPUT)
LAST BIT
TRANSMITTED
HIGH
Z
(5)
D70
D60
(10)
(8)
MOSI
(INPUT)
D71
(6)
DRIVER
OUTPUT
D10
(11)
D61
(9)
D11
FAULT-INDUCED
TURN-OFF
(7)
OLD
NEW
tPHL
tPLH
FIGURE 1B.
tUD
SPI TIMING DIAGRAM
RESET
CE
SCK
MOSI
7
6
5
4
3
2
1
0
MISO
7
6
5
4
3
2
1
0
OUTPUTS
OLD
NEW
RESET
FAULTS
FIGURE 2. BYTE TIMING DIAGRAM WITH ASYNCHRONOUS RESET
Signal Descriptions
all output drivers. A power on clear function may be implemented by connecting this pin to VDD with an external resistor, and to VSS with an external capacitor. In any case, this
pin must not be left floating.
Power Output Drivers, Output 0 - Output 7 - The input and
output bits corresponding to Output 0 thru Output 7 are
transmitted and received most significant bit (MSB) first via
the SPI bus. The outputs are provided with current limiting
and voltage sense functions for fault indication and protection. The nominal load current for these outputs is 500mA,
with current limiting set to a minimum of 1.05A. An on-chip
clamp circuit capable of handling 500mA is provided at each
output for clamping inductive loads.
CE - Active low chip enable. Data is transferred from the shift
register to the outputs on the rising edge of this signal. The
falling edge of CE loads the shift register with the output voltage sense bits coming from the output stages. The output
driver for the MISO pin is enabled when this pin is low. CE
must be a logic low prior to the first serial clock (SCK) and
must remain low until after the last (eighth) serial clock cycle.
A low level on CE also activates an internal disable circuit
used for unlatching output states that are in a fault mode as
RESET - Active low reset input. When this input line is low,
the shift register and output latches are configured to turn off
4
CA3282
Serial Peripheral Interface (SPI) protocol. Each channel is
independently controlled by an output latch and a common
RESET line that disables all eight outputs. Byte timing with
asynchronous reset is shown in Figure 4. The circuit
receives 8-bit serial data by means of the serial input
(MOSI), and stores this data in an internal register to control
the output drivers. The serial output (MISO) provides 8-bit
diagnostic data representing the voltage level at the driver
output. This allows the microcomputer to diagnose the condition at the output drivers. The device is selected when the
chip enable (CE) line is low. When (CE) is high, the device is
deselected and the serial output (MISO) is placed in a threestate mode. The device shifts serial data on the rising edge
of the serial clock (SCK), and latches data on the falling
edge. On the rising edge of chip enable (CE), new input data
from the shift register is latched in the output drivers. The
falling edge of chip enable (CE) transfers the output drivers
fault information back to the shift register. The output drivers
have low ON voltage at rated current, and are monitored by
a comparator for an out of saturation condition, in which
case the output driver with the fault becomes unlatched and
diagnostic data is sent to the microcomputer via the MISO
line. A typical microcomputer interface circuit is shown in
Figure 2. Also, the CA3282 may be cascaded with another
CA3282 octal driver.
sensed by an out of saturation condition. A high on CE
forces MISO to a high impedance state. Also, when CE is
high, the octal driver ignores the SCK and MOSI signals.
SCK, MISO, MOSI - See Serial Peripheral Interface (SPI)
section in this data sheet.
VDD and VSS (GND) - Positive and negative power supply
lines.
Serial Peripheral Interface (SPI)
The Serial Peripheral Interface (SPI) utilized by the CA3282
is a serial synchronous bus for control and data transfers.
The Clock (SCK), which is generated by the microcomputer,
is active only during data transfers. In systems using
CDP68HC05 family microcomputers, the inactive clock
polarity is determined by the CPOL bit in the microcomputer’s control register. The CPOL bit is used in conjunction
with the clock phase bit, CPHA to produce the desired clock
data relationship between the microcomputer and octal
driver. The CPHA bit in general selects the clock edge which
captures data and allows it to change states. For the
CA3282, the CPOL bit must be set to a logic zero and the
CPHA bit to a logic one. Configured in this manner, MISO
(output) data will appear with every rising edge SCK, and
MOSI (input) data will be latched into the shift register with
every falling edge of SCK. Also, the steady state value of the
inactive serial clock, SCK, will be at a low level. Timing diagrams for the serial peripheral interface are shown in Figure 1.
Shift Register
The shift register has both serial and parallel inputs and outputs. Serial output and input data are simultaneously transferred to and from the SPI bus. The parallel outputs are
latched into the output latch in the CA3282 at the end of a
data transfer. The parallel inputs jam diagnostic data into the
shift register at the beginning of a data transfer cycle.
SPI Signal Descriptions
MOSI (Master Out/Slave In) - Serial data input. Data bytes
are shifted in at this pin, most significant bit (MSB) first. The
data is passed directly to the shift register which in turn controls the latches and output drivers. A logic “0” on this pin will
program the corresponding output to be ON, and a logic “1”
will turn it OFF.
CDP68HC05C4
MICROCOMPUTER
MISO (Master In/Slave Out) - Serial data output. Data bytes
are shifted out at this pin, most significant bit (MSB) first.
This pin is the serial output from the shift register and is
three stated when CE is high. A high for a data bit on this pin
indicates that the corresponding output is high. A low on this
pin for a data bit indicates that the output is low. Comparing
the serial output bits with the previous input bits, the microcomputer implements the diagnostic data supplied by the
CA3282.
PORT
CE
MOSI
MOSI
MISO
MISO
SCK
SCK
RESET
SCK - Serial clock input. This signal clocks the shift register
SCK and new MOSI (input) data will be latched into the shift
register on every falling edge of SCK. The SCK phase bit,
CPHA, and polarity bit, CPOL, must be set to 1 and 0,
respectively in the microcomputer’s control register.
CA3282
RESET
FIGURE 3. TYPICAL MICROCOMPUTER INTERFACE WITH
THE CA3282
Output Latch
The output latch holds input data from the shift register
which is used to activate the outputs. The latch circuit may
be cleared by a fault condition (to protect the overloaded outputs), or by the RESET signal.
Functional Descriptions
The CA3282 is a low operating power, high voltage, high
current, octal power driver featuring eight channels of open
drain NDMOS output drivers. The drivers have low saturation voltage and output short circuit protection, suited for
driving resistive or inductive loads such as lamps, relays and
solenoids. Data is transmitted to the device serially using the
5
CA3282
Output Drivers
shows a zero, then the probable cause is an open circuit
resulting in a floating output.
The output drivers provide and active low output of 500mA
nominal with current limiting set to 1.05A to allow for high
inrush currents. In addition, each output is provided with a
voltage clamp circuit to limit inductive transients. Each output driver is also monitored by a comparator for an out of
saturation condition. If the output voltage of an ON output
pin exceeds the saturation voltage limit, a fault condition is
assumed and the latch driving this output is reset, turning
the output off. The output comparators, which also provide
diagnostic feedback data to the shift register, contain an
internal pull-down current which will cause the cell to indicate a low output voltage if the output is programmed OFF
and the output pin is open circuited.
1.5
-40×oC
CURRENT IN AMPERES (IOUT)
rDS(ON) = 0.48Ω
25o×C
rDS(ON) = 0.54Ω
rDS(ON) = 0.67Ω
1.0
105×oC
rDS(ON) = 0.78Ω
125×oC
0.5
CE High to Low Transition
When CE is low the three state MISO pin is enabled. On
the falling edge of CE, diagnostic data from the output voltage comparators will be latched into the shift register. If an
output is high, a logic one will be loaded into that bit in the
shift register. If the output is low, a logic zero will be loaded.
During the time that CE is low, data bytes controlling the
output drivers are shifted in at the MOSI pin most significant bit (MSB) first. A logic zero on this pin will program the
corresponding output to be ON, and a logic one will turn it
OFF.
0
0.2
0.4
0.6
0.8
SATURATION VOLTAGE (VSAT)
FIGURE 3A. CA3282 TYPICAL OUTPUT DRIVER rDS(ON)
CHARACTERISTICS OF CURRENT OUT vs
SATURATION VOLTAGE, VSAT FOR A -40oC TO
125oC JUNCTION TEMPERATURE
TYP CURRENT LIMITING
CE Low to High Transition
1.5
CURRENT IN AMPERES (IOUT)
When the last data bit has been shifted into the CA3282,
the CE pin should be pulled high. At the rising edge of CE,
shift register data is latched into the output latch and the
outputs are activated with the new data. An internal 150µs
delay timer will start at this rising edge to compensate for
high inrush currents in lamps and inductive loads. During
this period, the outputs will be protected only by the analog
current limiting circuits since resetting of the output latches
by fault conditions will be inhibited during this time. This
allows the device to handle inrush currents immediately
after turn on. When the 150µs delay has elapsed, the output voltages are sensed by the comparators and any out of
saturation outputs are latched off. The serial clock input pin
(SCK) should be low during CE transitions to avoid false
clocking of the shift register. The SCK input is gated by CE
so that the SCK input is ignored when CE is high.
-40oC
1.0
25oC
105oC
0.5
125oC
0
0
0.5
1.0
1.5
SATURATION VOLTAGE (VSAT)
FIGURE 3B. CA3282 TYPICAL OUTPUT DRIVER rDS(ON)
CHARACTERISTICS OF CURRENT OUT vs
SATURATION VOLTAGE, VSAT FOR A -40oC TO
125oC JUNCTION TEMPERATURE
Detecting Fault Conditions
Fault conditions may be checked as follows. Clock in a new
control byte and wait approximately 150µs to allow the outputs to settle. Clock in the same control byte and note the
diagnostic data output at the MISO pin. The diagnostic bits
should be identical to the data clocked in. Any differences
will indicate a fault in the corresponding outputs. For example, if an output was programmed ON by clocking in a zero,
and the corresponding diagnostic bit for that output is a
one, indicating the driver output is still high, then a short circuit or overload condition may have caused the output to
unlatch. Alternatively, if the output was programmed OFF
by clocking in one, and the diagnostic bit for that output
Dissipation In Multiple Outputs
The CA3282 Octal Power Driver has multiple MOS Output
Drivers and requires special consideration with regard to
maximum current and dissipation ratings. While each output
has a maximum current specification consistent with the
device structure, all such devices on the chip can not be
simultaneously rated to the same high level of peak current.
The total combined current and the dissipation on the chip
must be adjusted for maximum allowable ratings, given
simultaneous multiple output conditions.
6
CA3282
Equation 3 and Equation 3A may be expressed as:
For the CA3282, the maximum positive output current rating
is 1A when one output is ON. When ALL outputs are ON, the
rating is reduced to 0.625A because the total maximum current is limited to 5A. For any given application, all output
drivers on a chip may or may not have a different level of
loading. The discussion here is intended to provide relatively
simple methods to determine the maximum dissipation and
current ratings as a general solution and, as a special solution, when all switched ON outputs have the same current
loading.
T
T
A
= T –P ×θ
J
D
JA
(EQ. 5A)
Calculation Example 1
For the CA3282, θJC = 3oC/W and the worst case junction
temperature, as an application design solution, should not
exceed 150oC. For any given application, Equation 1 determines the dissipation, PD .
Assume the package is mounted to a heat sink having a
thermal resistance of 6oC/W and, for a given application, the
dissipation, PD = 3W. Assume the operating ambient temperature, TA = 100oC. The calculated Junction-to-Ambient
thermal resistance is:
n
Pk
(EQ. 5)
Not all Integrated Circuit packages have a directly definable
case temperature because the heat is spread thru the lead
frame to a PC Board which is the effective heat sink.
A general equation for dissipation should specify that the
total power dissipation in a package is the sum of all significant elements of dissipation on the chip. However, in Power
BiMOS Circuits very little dissipation is needed to control the
logic and predriver circuits on the chip. The over-all chip dissipation is primarily the sum of the I2R dissipation losses in
each channel where the current, I is the output current and
the resistance, R is the NMOS channel resistance, rDS(ON)
of each output driver. As such, the total dissipation, PD for n
output drivers is:
∑
= T +P ×θ
A
D
JA
or
General Solution
PD =
J
(EQ. 1)
θJA = θJC + θCA = 9oC/W
k=1
This expression sums the dissipation, PK of each output
driver without regard to uniformity of dissipation in each
MOS channel. The dissipation loss in an NMOS channel is:
The solution for junction temperature by Equation 5 is :
2
P k = I × r DS ON
(
)
Calculation Example 2
TJ = 100oC + 3W x 9oC/W = 127oC
(EQ. 2)
Using the CA3282 maximum Junction-to-Ambient Thermal
Resistance, θJA value of 45oC/W (no external heat sink) and
the worst case Junction Temperature, TC of 150oC we have
an application design solution for the maximum ambient
temperature or dissipation. For example; Using Equation 1
and assuming a device dissipation, PD of 1W, the maximum
allowable Ambient Temperature, TA from Equation 5A is
calculated as follows:
where the current, I is determined by the output load when
the channel is turned ON. The channel resistance, rDS(ON)
is a function of the circuit design, level of gate voltage and
the chip temperature. Refer to the Electrical Specifications
values for worse case channel resistance.
The temperature rise in the package due to the dissipation is
the product of the on-chip dissipation, PD and the package
Junction-to-Case thermal resistance, θJC. To determine the
junction temperature, TJ, given the case (heat sink tab)
temperature, TC, the linear heat flow solution is:
T J = T C + P D × θ JC
TA = 150oC - 1.0W x 45oC/W = 105oC
Equal Current Loading Solution
Where a given application has equal current loading in the
output drivers, equal rDS(ON) and temperature conditions
may be assumed. As such, a convenient method to show
rating boundaries is to substitute the dissipation Equation 2
into the junction temperature Equation 3. For m outputs that
are ON with equal currents, where I = I1 = I2..... = Im , we
have the following solution for dissipation:
(EQ. 3)
or
T C = T J – P D × θ JC
(EQ. 3A)
Since this solution relates only to the package, further
consideration must be given to a practical heat sink. The
equation of linear heat flow assumes that the Junction-toAmbient thermal resistance, θJA , is the sum of the thermal
resistance from Junction-to-Case and the thermal resistance
from Case (heat sink)-to-Ambient, θCA . The Junction-toAmbient thermal resistance, θJA is the sum of all thermal
paths from the chip junction to the ambient temperature (TA)
environment and can be expressed as:
θ J A = θ JC + θ CA
2
P D = m × Pk = m × I × r DS ( ON )
I =
(EQ. 4)
7
TJ – TC
----------------------------------------------------m × θ JC × r DS ON
(
)
(EQ. 6)
(EQ. 7)
CA3282
The number of output drivers ON and conducting (m) may
be from 1 to n. (i.e., For all 8 output drivers conducting, m =
n = 8.) Maximum temperature, dissipation and current ratings must be observed. The drain current vs case temperature may be plotted for any value of m from 1 to 8, provided
drain currents remain equal.
The curve of Figure 5 illustrates the boundary limits for temperature and dissipation. Figure 6 shows the maximum current for all 8 outputs ON with equal current plotted versus
Case Temperature, TC. Boundary conditions relate to the
Absolute Maximum Ratings as defined in the data sheet.
12
CA3282 WITH EXT.
6oC/W HEAT SINK
(θJA = 9oC/W)
DISSIPATION WATTS (W)
10
CA3282 WITH INFINITE
HEAT SINK
(θJC = 3oC/W)
8
6
CA3282 WITH NO HEAT SINK
(θJA = 45oC/W)
4
2
0
-40
-25
0
25
50
75
100
125
150
AMBIENT TEMPERATURE (oC)
MAX. DRIVE CURRENT, ALL OUTPUTS ON
(WITH EQUAL CURRENT) (A)
FIGURE 5. DISSIPATION DERATING CURVE
1.0
MAX. ALL ON CURRENT LIMITED
(0.625A EA. X 8 = 5A TOTAL CURRENT)
0.5
IMAX ALL ON DISSIPATION LIMITED
I MAX =
rDS(ON) = 1Ω
THERMAL RESISTANCE, θJC = 3oC/W
150 – T C
----------------------------------------------------8 × θ JC × ( r DS ( ON ) )
0.0
50
75
100
125
150
CASE TEMPERATURE (oC)
FIGURE 6. CURRENT vs CASE (TAB) TEMPERATURE, ALL OUTPUTS ON WITH EQUAL CURRENT
8
CA3282
Single-In-Line Plastic Packages (SIP)
D
-X-
Z15.05A (JEDEC MO-048 AB ISSUE A)
A
SEE TAB
DETAIL
15 LEAD PLASTIC SINGLE-IN-LINE PACKAGE STAGGERED
VERTICAL LEAD FORM
F
INCHES
E
E1
L1
-Y-
TERMINAL
N
3
R1
TERMINAL
#1
L
H
e
e3
e1
e2
B
0.024(0.61) M
C
L L L L L L L
H H H H H H H H
0.010(0.25) M
L
-Z-
Z
X M
Z
TYP ALL LEADS
Y M
SYMBOL
MIN
MAX
MIN
MAX
A
0.172
0.182
4.37
4.62
B
0.024
0.031
0.61
0.79
C
0.014
0.024
0.36
0.61
D
0.778
0.798
19.76
20.27
E
0.684
0.694
17.37
17.63
E1
0.416
0.426
10.57
10.82
E2
0.110 BSC
2.79 BSC
e
0.050 BSC
1.27 BSC
e1
0.200 BSC
5.08 BSC
e2
0.169 BSC
4.29 BSC
e3
0.700 BSC
17.78 BSC
F
0.057
0.063
1.45
1.60
L
0.150
0.176
3.81
4.47
L1
0.690
0.710
17.53
N
ØP
Ø 0.015(0.38) M
Z
X S
MILLIMETERS
15
18.03
15
ØP
0.148
0.152
3.76
3.86
R1
0.065
0.080
1.65
2.03
Rev. 1 4/98
E2
TAB DETAIL
NOTES:
1. Refer to series symbol list, JEDEC Publication No. 95.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1982.
3. N is the number of terminals.
4. Controlling dimension: INCH.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
9
CA3282
Single-In-Line Plastic Packages (SIP)
Z15.05B
-ZD
15 LEAD PLASTIC SINGLE-IN-LINE PACKAGE SURFACE
MOUNT “GULLWING” LEAD FORM
A
-X-
F
ØP
INCHES
E2
E
E1
R1
-Y-
SYMBOL
MIN
MAX
A
0.172
0.182
4.37
4.62
15 C
SURFACES
B TYP
0.010 M
Z X S
Y M
0.004
15 LEAD TIPS
0.008 Z
e3
(NOTE 3)
HEADER
BOTTOM
L
L1
MAX
B
0.024
0.031
0.61
0.79
0.018
0.024
0.46
0.61
D
0.778
0.798
19.76
20.27
E
0.684
0.694
17.37
17.63
E1
0.416
0.426
10.57
0.110 BSC
10.82
2.79 BSC
e
0.050 BSC
1.27 BSC
e3
0.700 BSC
17.78 BSC
F
0.057
0.063
L
0.065
0.080
1.66
L1
0.098
0.108
2.49
N
0 o- 8 o
MIN
C
E2
e
MILLIMETERS
1.45
15
1.60
2.03
2.74
15
ØP
0.148
0.152
3.76
3.86
R1
0.065
0.080
1.65
2.03
Rev. 1 11/97
NOTES:
1. Dimensioning and Tolerancing per ANSI Y14.5M - 1982.
2. N is the number of terminals.
3. All lead surfaces are within 0.004 inch of each other. No lead can
be more than 0.004 inch above or below the header plane,
( -Z- Datum).
BOTTOM VIEW
4. Controlling dimension: INCH.
LAND PATTERN
0.814
0.407
CL OF 0.150
0.130
0.700
0.662
0.774
0.030 TYP
0.050 TYP
0.350
0.700
10
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