DATASHEET

EL7182
ESIGNS
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FN7281.1
2-Phase, High Speed CCD Driver
Features
The EL7182 is extremely well suited for driving CCD's,
especially where high contrast imaging is desirable. The 16V
supply rating is attractive for higher voltage CCD
applications, as in color fax machines. The input is TTL and
3V compatible. The low quiescent current requirement is
advantageous in portable/battery powered systems. The
EL7182 is available in 8 Ld PDIP and 8 Ld SOIC packages.
• 3V and 5V Input compatible
• Clocking speeds up to 10MHz
• Reduced clock skew
• 20ns Switching/delay time
• 2A Peak drive
• Low quiescent current
Pinout
• Wide operating voltage: 4.5V–16V
EL7182
(8 LD PDIP, SOIC)
TOP VIEW
• Pb-free plus anneal available (RoHS compliant)
Applications
• CCD Drivers requiring high-contrast imaging
• Differential line drivers
• Push-pull circuits
Manufactured under U.S. Patent Nos. 5,334,883, #5,341,047
Ordering Information
PART
TEMP.
PART NUMBER MARKING RANGE (°C) PACKAGE
PKG.
DWG. #
EL7182CN
EL7182CN
-40 to +85 8 Ld PDIP
MDP0031
EL7182CS
7182CS
-40 to +85 8 Ld SOIC
MDP0027
EL7182CSZ
(Note)
7182CSZ
-40 to +85 8 Ld SOIC
(Pb-free)
MDP0027
EL7182CSZ-T7 7182CSZ
(Note)
8 Ld SOIC (7” Tape and Reel)
(Pb-free)
EL7182CSZ-T13 7182CSZ
(Note)
8 Ld SOIC (7” Tape and Reel)
(Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003, 2006. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
EL7182
Absolute Maximum Ratings (TA = 25°C)
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 125°C
Power Dissipation
SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .570mW
PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1050mW
Supply (V+ to Gnd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5V
Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V above V+
Combined Peak Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . .4A
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
TA = 25°C, V = 15V unless otherwise specified
DESCRIPTION
TEST CONDITIONS
MIN
TYP
MAX
UNITS
INPUT
VIH
Logic “1” Input Voltage
IIH
Logic “1” Input Current
VIL
Logic “0” Input Voltage
IIL
Logic “0” Input Current
VHVS
Input Hysteresis
2.4
@V+
V
0.1
@0V
0.1
10
µA
0.8
V
10
µA
0.3
V
OUTPUT
ROH
Pull-Up Resistance
IOUT = -100mA
3
6

ROL
Pull-Down Resistance
IOUT = +100mA
4
6

IPK
Peak Output Current
Source
2
A
Sink
2
A
IDC
Continuous Output Current
Source/Sink
IS
Power Supply Current
Input High
VS
Operating Voltage
100
mA
POWER SUPPLY
4.5
5
mA
16
V
TA = 25°C, V = 15V unless otherwise specified
AC Electrical Specifications
PARAMETER
2.5
DESCRIPTION
TEST CONDITIONS
MIN
TYP
MAX
UNITS
SWITCHING CHARACTERISTICS
tR
tF
Rise Time
Fall Time
CL = 500pF
7.5
ns
CL = 1000pF
10
CL = 500pF
10
CL = 1000pF
13
20
ns
20
ns
ns
tD-ON
Turn-On Delay Time
18
25
ns
tD-OFF
Turn-Off Delay Time
20
25
ns
2
FN7281.1
June 15, 2006
EL7182
Timing Table
Standard Test Configuration
Simplified Schematic
3
FN7281.1
June 15, 2006
EL7182
Typical Performance Curves
Switch Threshold vs
Supply Voltage
Max Power/Derating Curves
Input Current vs Voltage
Peak Drive vs Supply Voltage
Quiescent Supply Current
“ON” Resistance vs Supply Voltage
CASE:
Average Supply Current vs
Voltage and Frequency
4
Input Level
Curve
GND
B
V+
D
Average Supply Current
vs Capacitive Load
FN7281.1
June 15, 2006
EL7182
Typical Performance Curves
(Continued)
Rise/Fall Time vs Load
Rise/Fall Time vs Supply Voltage
Rise/Fall Time vs Temperature
Propagation Delay vs Supply Voltage
Delay Time vs Temperature
5
FN7281.1
June 15, 2006
EL7182
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M C A B
e
H
C
A2
GAUGE
PLANE
SEATING
PLANE
A1
0.004 C
0.010 M C A B
L
b
0.010
4° ±4°
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
SYMBOL
SO-8
SO-14
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
TOLERANCE
NOTES
A
0.068
0.068
0.068
0.104
0.104
0.104
0.104
MAX
-
A1
0.006
0.006
0.006
0.007
0.007
0.007
0.007
0.003
-
A2
0.057
0.057
0.057
0.092
0.092
0.092
0.092
0.002
-
b
0.017
0.017
0.017
0.017
0.017
0.017
0.017
0.003
-
c
0.009
0.009
0.009
0.011
0.011
0.011
0.011
0.001
-
D
0.193
0.341
0.390
0.406
0.504
0.606
0.704
0.004
1, 3
E
0.236
0.236
0.236
0.406
0.406
0.406
0.406
0.008
-
E1
0.154
0.154
0.154
0.295
0.295
0.295
0.295
0.004
2, 3
e
0.050
0.050
0.050
0.050
0.050
0.050
0.050
Basic
-
L
0.025
0.025
0.025
0.030
0.030
0.030
0.030
0.009
-
L1
0.041
0.041
0.041
0.056
0.056
0.056
0.056
Basic
-
h
0.013
0.013
0.013
0.020
0.020
0.020
0.020
Reference
-
16
20
24
28
Reference
N
8
14
16
Rev. L 2/01
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
6
FN7281.1
June 15, 2006
EL7182
Plastic Dual-In-Line Packages (PDIP)
E
D
A2
SEATING
PLANE
L
N
A
PIN #1
INDEX
E1
c
e
b
A1
NOTE 5
1
eA
eB
2
N/2
b2
MDP0031
PLASTIC DUAL-IN-LINE PACKAGE
SYMBOL
PDIP8
PDIP14
PDIP16
PDIP18
PDIP20
TOLERANCE
A
0.210
0.210
0.210
0.210
0.210
MAX
A1
0.015
0.015
0.015
0.015
0.015
MIN
A2
0.130
0.130
0.130
0.130
0.130
±0.005
b
0.018
0.018
0.018
0.018
0.018
±0.002
b2
0.060
0.060
0.060
0.060
0.060
+0.010/-0.015
c
0.010
0.010
0.010
0.010
0.010
+0.004/-0.002
D
0.375
0.750
0.750
0.890
1.020
±0.010
E
0.310
0.310
0.310
0.310
0.310
+0.015/-0.010
E1
0.250
0.250
0.250
0.250
0.250
±0.005
e
0.100
0.100
0.100
0.100
0.100
Basic
eA
0.300
0.300
0.300
0.300
0.300
Basic
eB
0.345
0.345
0.345
0.345
0.345
±0.025
L
0.125
0.125
0.125
0.125
0.125
±0.010
N
8
14
16
18
20
Reference
NOTES
1
2
Rev. B 2/99
NOTES:
1. Plastic or metal protrusions of 0.010” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.
4. Dimension eB is measured with the lead tips unconstrained.
5. 8 and 16 lead packages have half end-leads as shown.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
7
FN7281.1
June 15, 2006
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