DATASHEET

HIP0051
TM
0.25A/50V Octal Low Side Power Driver
with Serial Bus Control
June 1996
Features
Description
• Eight Open Drain - NDMOS Low Side Drivers Each
Capable of 250mA
The HIP0051 is a logic controlled, eight channel Octal Low
Side Power Driver. As shown in the Block Diagram, the
outputs are controlled via the serial data interface which
allows the data to be shifted out, allowing control of other
cascaded serial devices.
• High Voltage Power BiMOS with Low Idle and Standby
Current
• Over-Voltage Clamp Protection
- Each Output . . . . . . . . . . . . . . . . . . . . . . . 50V Typical
The HIP0051 is fabricated in a Power BiMOS IC process,
and is intended for use in automotive and other applications
having a wide range of temperature and electrical stress
conditions. It is particularly suited for driving lamps, displays,
relays, and solenoids in applications where low operating
power, high breakdown voltage, and high output current at
high temperature is required.
• Serial Data Input, Parallel Output Power Drive
• Common Enable for Output Drivers and Data Storage
Register
• -40oC to 85oC Operating Range
Ordering Information
Applications
PART
NUMBER
• Automotive and Industrial Systems
• Solenoids, Relays and Lamp Drivers
HIP0051IB
TEMP.
RANGE (oC)
-40 to 85
PACKAGE
20 Ld SOIC
PKG.
NO.
M20.3
• Logic and µP Controlled Drivers
• Robotic Controls
Pinout
Block Diagram
HIP0051
(SOIC)
TOP VIEW
EN
GND
1
20 GND
VCC
2
19 LGND
SI
3
18 SO
DR0
4
17 DR7
DR1
5
16 DR6
DR2
6
15 DR5
DR3
7
14 DR4
NC
8
13 SCK
EN
9
12 STR
GND 10
11 GND
STR
OUTPUT DRIVER
(CHANNEL 1 OF 8)
(ENABLE)
DR#0
(STROBE)
Q0
SI
SCK
SO
8-BIT
SERIAL
(SPI)
INPUT
REGISTER
(DATA IS
PARALLEL
OUTPUT
LATCHED
WHEN
STROBED)
Q1
OUTPUT
LATCH
Q2
Q3
Q4
Q5
Q6
Q7
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1
FN4155
Specifications HIP0051
Absolute Maximum Ratings
Thermal Information
Output Voltage, VOUT (Note 1). . . . . . . . . . . . . . . . . . . -0.3V to 40V
Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V
Logic Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
Output Clamp Energy, 25oC (5ms Pulse). . . . . . . . . . . . . . . . . 75mJ
Continuous Output Load Current, ILOAD (Each Output) . . . . . 0.25A
Continuous Output Current, ILOAD (All Outputs ON, Note 2). . 1.69A
Peak Output Current
Each Output, Other Outputs OFF . . . . . . . . . . . . . . . . . . . . . ±2A
Peak Avalanche Current (3ms duration) . . . . . . . . . . . . . . . . . . 1A
Thermal Resistance (Typical, Note 3)
θJA (oC/W)
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range, TSTG . . . . -55oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC Lead Tips Only)
Operating Conditions
Operating Ambient Temperature Range, TA. . . . . . . -40oC to 85oC
Operating Logic Supply Voltage Range, VCC . . . . . +4.5V to +5.5V
Power Output Driver Voltage Range . . . . . . . . . . . . . . . . . 0 to VOC
Max. Supply Current, with 100mA each Output . . . . . . . . . . . 100µA
Max. Supply Current, with No Load, Outputs OFF . . . . . . . . . 100µA
Logic Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . .0.7xVCC
Logic Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.2xVCC
Typical Output RDSON Channel Resistance . . . . . . . . . . . . . . . . 2Ω
Typical Output Rise Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4µs
Typical Output Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10µs
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. The MOSFET Output Drain is internally clamped with a Drain-to-Gate zener diode that turns-on the MOSFET; holding the Drain at the
Output Clamp voltage VOC.
2. The maximum continuous current with all outputs on is limited by package dissipation. At 25oC ambient temperature, the maximum equal
current with all outputs ON is 211mA in each output for a total of 1.69A. At a maximum ambient temperature of TA = 85oC and
rDSON(Max) = 3.5Ω, each output is limited to 152mA and the total current for all 8 outputs ON is 8 x 152mA = 1.22A.
3. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
VCC = 4.5V to 5.5V, VBATT = 8V to 16V, TA = -40oC to 85oC, Unless Otherwise Specified.
PARAMETER
SYMBOL
TEST CONDITIONS
rDS(ON)
Output Current = 200mA, TA = 85oC
MIN
TYP
MAX
UNITS
2
3.5
Ω
58
V
OUTPUTS DRIVERS (DR0 TO DR7)
Output Channel Resistance
Output Clamping Voltage
Output Clamping Energy
VOC
Outputs OFF
42
50
EOC
5ms Pulse, TA = 25oC
75
190
mJ
Peak Output Load Currents,
Short Duration
IPEAK
100µs Duration, Each Output, all
Outputs ON, Duty Cycle ≤ 2%
0.85
-
-
A
Cold Start-up Lamp Currents
ILAMP
5ms Duration, Each Output, all
Outputs ON, Duty Cycle ≤ 17%
0.3
-
-
A
Output OFF Leakage Current
IOFF
Output Voltage = 40V, TA = 85oC
-
-0.2
10
µA
Output Rise Time
trise
0.5
4
30
µs
Output Fall Time
tfall
Load = 75Ω, 0.01µF (RC in Parallel),
VBATT = 18V
0.5
10
30
µs
Output Delay from Strobe, High to
Low Output Transition
tDHL
1
4
10
µs
Output Delay from Strobe, Low to
High Output Transition
tDLH
0.2
2.6
10
µs
LOGIC SUPPLY
Logic Supply Current, Loaded
ICC
All Outputs ON, 200mA Load at each
Output
-
-
100
µA
Logic Supply Current, No Load
ICC
All Outputs OFF
-
-
100
µA
2
Specifications HIP0051
Electrical Specifications
VCC = 4.5V to 5.5V, VBATT = 8V to 16V, TA = -40oC to 85oC, Unless Otherwise Specified. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
LOGIC INPUTS (EN, SI, SCK, STR)
Threshold Voltage at Falling Edge
VT-
VCC = 5V ± 10%
0.2VCC
0.3VCC
-
V
Threshold Voltage at Rising Edge
VT+
VCC = 5V ± 10%
-
0.6VCC
0.7VCC
V
Hysteresis Voltage
VH
VT+ - V T-
0.85
1.4
2.25
V
Leakage Current
I LIN
VCC = 5V
-10
-0.2
10
µA
Leakage Current
I LIN
VCC = 0V
-10
-0.1
10
µA
fSCK
-
-
1.6
MHz
Pulse Width High
tW(CKH)
175
27
-
ns
Pulse Width Low
tW(CKL)
175
27
-
ns
Input Setup Time
tSUI
-
1.1
75
ns
Input Hold Time
THI
-
1.5
75
ns
Strobe Pulse Width
tW(S)
150
12
-
ns
Min. Clock to Strobe Delay
tD(CS)
75
5
-
ns
-
0.2
0.4
V
3.7
4.4
-
V
75
260
-
ns
SERIAL DATA CLOCK (SCK)
Frequency
SERIAL DATA IN (SI)
STROBE (STR)
SERIAL DATA OUT (SO)
Low Level Output Voltage
VOL
Sink Current = 1.6mA
High Level Output Voltage
VOH
Source Current = -1.6mA
Propagation Delay
tP(CD)
tW(SCK)
tW(SCK)
SCK (CLOCK)
tSUI
tHI
SI (SERIAL DATA IN)
tW(S)
tD(CS)
STR (STROBE)
tDHL
tDLH
90%
10%
DRx
(POWER OUTPUT DRIVER)
tP(CD)
SO (SERIAL DATA OUT)
FIGURE 1. LOGIC TIMING CONTROL SPECIFICATIONS
3
tfall, trise
HIP0051
Pin Descriptions
VCC - Logic Power Supply
SO - Serial Data Out
The VCC pin is the positive 5V logic voltage supply input for
the IC. The normal operating voltage range is 4.5 to 5.5V.
When switched on, the POR forces all outputs off.
The Serial Data Out allows other ICs to be serially cascaded.
For example, a 10-bit LED driver may be located behind the
HIP0051. A controlling microprocessor may then clock out
18 bits of information and simultaneously strobe both parts.
The cascaded ICs may be the same or different from the
HIP0051.
SCK - Serial Clock
SCK is the clock input for the SPI interface. Output ON/OFF
control data is clocked into an eight stage shift register on
the rising edge of an external clock. This input has a Schmitt
trigger.
DR0 to DR7 - Outputs 0 Thru 7
The Drain Output pins of the DMOS Power Drivers are
capable of sinking 250mA.
SI - Serial Data In
EN - Enable
SI is the Serial Data Input pin for the SPI interface. The eight
Power Outputs are controlled by the serial data via the
Output Data Buffer. This input has a Schmitt trigger.
The Enable pin is an active low enable function for all eight
output drivers. When EN is high, drive from the Output Data
Buffer is held low and all output drivers are disabled. When
EN is low, the output drivers are enabled and data in the
8-bit shift register is transparent to the Output Data Buffer.
This input has a Schmitt trigger.
STR - Strobe for the SPI Interface
When the STR pin is high, data from the 8-bit shift register is
passed into the Output Data Buffers where it controls the
ON-OFF state of each output driver. The data is latched in
the Output Data Buffers on the trailing edge of the STR
pulse. This input has a Schmitt trigger.
LGND and GND - Ground
LGND is the logic input power supply ground pin. The GND
pins are common grounds for the Power Output Drivers. The
power supplies for the logic and power circuits require a
common ground. To minimize ground bounce at the logic
input, the external ground return path for the GND pin should
be separate from the LGND pin. LGND and GND have common substrate ground connections on the chip.
OUTPUT CONTROL TABLE
STROBE
8-BIT SERIAL DATA (LATCHED)
OUTPUT

D1
D2
D3
D4
D5
D6
D7
D8
DR1
DR2
DR3
DR4
DR5
DR6
DR7
DR8

0
0
0
0
0
0
0
0
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF

1
0
0
0
0
0
0
0
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF

1
1
0
0
0
0
0
0
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF

1
1
1
0
0
0
0
0
ON
ON
ON
OFF
OFF
OFF
OFF
OFF

1
1
1
1
0
0
0
0
ON
ON
ON
ON
OFF
OFF
OFF
OFF

0
0
0
0
1
1
1
1
OFF
OFF
OFF
OFF
ON
ON
ON
ON

1
1
1
1
1
1
1
1
ON
ON
ON
ON
ON
ON
ON
ON
4
HIP0051
Small Outline Plastic Packages (SOIC)
M20.3 (JEDEC MS-013-AC ISSUE C)
N
20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010) M
H
B M
INCHES
MILLIMETERS
E
SYMBOL
-B1
2
3
L
SEATING PLANE
-A-
h x 45 o
A
D
µα
A1
B
C
0.10(0.004)
0.25(0.010) M C A M
B S
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
0.0040
0.0118
0.10
0.30
-
B
0.013
0.0200
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.4961
0.5118
12.60
13.00
3
E
0.2914
0.2992
7.40
7.60
4
0.050 BSC
1.27 BSC
-
H
0.394
0.419
10.00
10.65
-
h
0.010
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
8o
0o
N
α
NOTES:
MAX
A1
e
-C-
e
MIN
20
0o
20
7
8o
Rev. 0 12/93
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
7585 Irvine Center Drive
Suite 100
Irvine, CA 92618
TEL: (949) 341-7000
FAX: (949) 341-7123
Intersil Corporation
2401 Palm Bay Rd.
Palm Bay, FL 32905
TEL: (321) 724-7000
FAX: (321) 724-7946
EUROPE
Intersil Europe Sarl
Ave. William Graisse, 3
1006 Lausanne
Switzerland
TEL: +41 21 6140560
FAX: +41 21 6140579
5
ASIA
Intersil Corporation
Unit 1804 18/F Guangdong Water Building
83 Austin Road
TST, Kowloon Hong Kong
TEL: +852 2723 6339
FAX: +852 2730 1433
Similar pages