DATASHEET

HIP0060
TM
1.5A, 50V Quad Low Side Power Driver
with Serial Bus Control and Fault Protection
July 1997
Features
Description
• Quad NDMOS Output Drivers in a High Voltage Power
BiMOS Process
The HIP0060 is a 5V logic controlled Quad Low Side Power
Driver. The outputs are individually protected for over-current
(OC), over-temperature (OT) and over-voltage (OV). If an OC
short circuit in the output load is sensed (IS) in one output
power driver, that output current will be independently limited
while the other outputs remain in operation. Over-current is
limited by direct gate feedback. Over-voltage protection is provided by a drain-to-gate zener diode that clamps inductive
switching pulses.
• Over-Stress Protection - Each Output
- Over-Current Limiting . . . . . . . . . . . . . . . . . . 1.5A Min
- Internal Zener Drain-to-Gate Over-Voltage Clamp
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50V Typ
- Thermal Shutdown Protection
- Open-Load Detection
The output drivers are individually controlled through a Gate
Control Latch. Temperature is sensed at each output. If a
thermal fault exists, a status flag is set and the output is
latched off. Open-load (OL) and over-temperature (OT) faults
sets a status flag bit as diagnostic output to the SPI bus. For
all fault bits (8), an ORed one-shot interrupt signal is output to
the INT pin. An RST reset clears the fault flags and disables
all outputs while active. The Serial Peripheral Interface (SPI)
bus pins are the Serial Input (SI), Serial Output (SO), Serial
Data Clock (SCK) and the Chip Select (CS).
• Low Quiescent Current . . . . . . . . . . . . . . . . 10mA Max
• Serial Diagnostic Link with SPI Bus
• Diagnostic Interrupt Fault Flag
• 5V CMOS Logic Input Control
• Common Reset for Fault Bits and Output Drivers
• Ambient Operating
Temperature Range . . . . . . . . . . . . . . . -40oC to 125oC
The HIP0060 is fabricated in a Power BiMOS IC process, and
is intended for use in automotive and other applications having
a wide range of temperature and electrical stress conditions. It
is particularly suited for driving lamps, relays, and solenoids in
applications where low operating power, high breakdown voltage, and higher output current at high temperatures is required.
Applications
• Automotive and Industrial Systems
• Fuel Injection Drivers
• Solenoids, Relays and Lamp Drivers
Ordering Information
• Logic and µP Controlled Drivers
• Robotic Controls
PART NUMBER
TEMP.
RANGE ( oC)
-40 to 125
HIP0060AB
Pinout
CHANNEL A
(1 OF 4)
VDD
GND
1
24 VDD
INT
2
23 RST
INA
3
22 IND
5
20 GND
GND
6
19 GND
GND
7
18 GND
GND
8
17 GND
9
16 OUTC
INB 10
SI 11
CS 12
M24.3
15 INC
14 SO
OVER TEMP.
DETECTOR
OPEN LOAD
DETECTOR
+5V
GATE
CONTROL
LATCH
INA
21 OUTD
GND
OUTB
24 Ld SOIC
PKG.
NO.
Block Diagram
HIP0060 (SOIC)
TOP VIEW
OUTA 4
PACKAGE
+
O.T.
BIT
O.L.
BIT
OVER
CURRENT
LIMIT
OUTA
IS
RST
SCK
SI
SO
CS
8-BIT SPI
(SERIAL
DIAG.
REG)
8 ORed O.T./O.L.
FAULT INPUTS,
ONE-SHOT
MULTI OUTPUT
2
2
2
2
2
INT
2
13 SCK
TO
B, C, D
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1
FROM B, C, D
FN
4045
HIP0060
Absolute Maximum Ratings
Thermal Information
Max Output Voltage, VOUT (Note 2). . . . . . . . . . . . . . . . . . . . . VOC
Max Output Load Current, ILOAD (Per Output, Note 3) . . . . . . . . ICL
Logic Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
Logic Supply Voltage, V DD. . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
Thermal Resistance (Typical, Notes 1, 4)
SOIC - PC Board Mount, Min. Copper . . . . . . . . . .
SOIC - PC Board Mount, 2 sq. in. Copper . . . . . . . .
Maximum Storage Temperature Range -55oC to 150oC
Operating Conditions
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
θJA (oC/W)
60
35
Ambient Temperature Range . . . . . . . . . . . . . . . . -40oC to 125oC
Junction Temperature Range . . . . . . . . . . . . . . . . -40oC to 150oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
2. The MOSFET Output Drain is internally clamped with a Drain-to-Gate zener diode that turns on the MOSFET; holding the Drain at the
Output Clamp voltage VOC.
3. The output drive is protected by an internal current limit. The ICL over-current limiting threshold parameter specification defines the maximum current. The maximum current with all outputs ON may be further limited by dissipation.
4. Device dissipation is based on thermal resistance capability of the package in a normal operating environment. The junction to ambient
thermal resistance of 60oC/W is defined here as a PC Board mounted device with minimal copper. With approximately 2 square inches
of copper area as a heat sink, it is practical to achieve 35oC/W thermal resistance. Further reduction in the thermal resistance can be
achieved with additional PC Board Copper ground area or an external heat sink structure next to the ground leads at the center of the
package.
Electrical Specifications
PARAMETER
VDD = 4.5V to 5.5V, VSS = 0V, TA = -40oC to 125oC; Unless Otherwise Specified
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
-
-
0.8
Ω
1.5
-
3.5
A
40
50
60
V
-
85
-
mJ
VOUT = 14.5V
-
-
180
µA
ROLD
VOUT = 14.5V, Output Off
4
-
200
kΩ
Output Rise Time
tR
RL = 30Ω, VOUT = 14.5V
1
-
12
µs
Output Fall Time
tF
RL = 30Ω, VOUT = 14.5V
1
-
12
µs
Turn-On Delay
tON
RL = 30Ω, VOUT = 14.5V
-
-
12
µs
Turn-Off Delay
tOFF
RL = 30Ω, VOUT = 14.5V
-
-
12
µs
3.2
-
4.4
V
-
-
10
mA
OUTPUTS DRIVERS (DR0 TO DR7)
Output Channel Resistance
Over-Current Limiting Threshold
Output Clamping Voltage
Output Clamping Energy
rDSON
IOUT = 0.5A
ICL
VOC
EOC
1ms Single Pulse Width, TA = 25oC,
(Refer to Figure 3 for SOA Limits).
Output OFF Leakage Current
Open-Load Fault Threshold
ILK
POWER SUPPLY
Power On Reset Threshold
VDD(POR)
VDD Logic Supply Current
IDD
All Outputs ON or OFF
LOGIC INPUTS (INx, SI, SCK, RST, CS)
High Level Input Voltage
VIH
0.7xVDD
-
-
V
Low Level Input Voltage
VIL
-
-
0.2xV DD
V
V ILHYS
0.8
-
-
V
-
-
0.4
V
VDD -0.8
-
-
V
Input Hysteresis
High Output Voltage, SO, INT
V OL
Current Sink = 1.6mA
Low Output Voltage, SO
V OH
Current Source = -0.8mA
Input Pull-Down Current, INx
IINPD
75
-
250
µA
Reset Input Pull-Up Current, RST
IRPU
20
-
120
µA
2
HIP0060
Electrical Specifications
VDD = 4.5V to 5.5V, VSS = 0V, TA = -40oC to 125oC; Unless Otherwise Specified (Continued)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
t INT
3
-
25
µs
tFAULT
-
-
16
µs
160
-
-
oC
tCYC
500
-
-
ns
tWSCKH,
tWSCKL
200
-
-
ns
SCK Rise/Fall Time
trSCK ,
tfSCK
-
-
30
ns
Enable Lead/Lag Time
tLEAD,
tLAG
250
-
-
ns
Output Data Valid Time
tV
-
-
170
ns
Data Setup Time
tSU
-
-
30
ns
Disable Time
tDIS
-
-
250
ns
DIAGNOSTIC
Pulse Width, INT
Fault Response Time
OVER-TEMPERATURE PROTECTION
Over-Temperature Shutdown
TSD
SERIAL PERIPHERAL INTERFACE TIMING
SCK Period
SCK Clock High/Low Time
(Capacitance Each Pin, CL = 200pF)
Description of Diagnostics
OL (Open-Load) Fault Mode
An open-load fault mode sequence consists of setting a status flag (the OL Bit) when an output open load condition is
detected. If the output impedance is greater than a preset
threshold, as detected when the input is off; the status bit is
set. The OL Bit is reset on the next falling edge of the IN
input signal. The off-on detection sequence will repeat as
long as the output impedance is higher than the detection
threshold, as detected in the off state.
OC (Over-Current) Fault Mode
In a short circuit or over-current fault condition when an output is switched on, the output current is limited to the ICL
maximum as defined in the Electrical Specifications. An OC
fault condition does not shutdown the output. The current is
sensed and feedback is directed to the gate of the MOS Output Driver. The gate voltage is reduced to maintained the
specified level of current limiting. In this mode, the drain voltage will increase and cause increased dissipation.
Diagnostic action for an OL fault mode differs from the OT
fault mode by not forcing an output shutdown through the
Gate Controlled Latch. Also, because the OL fault is
detected in the off state, the status flag is reset on the falling
edge of the input instead of the rising edge. The OL output
information to the Serial Diagnostic Register and the INT pin
is the same as the OT fault mode action.
OT (Over-Temperature) Fault Mode
Under a high dissipation over-temperature fault condition,
the output temperature is detected and compared to a preset
threshold level. When the OT threshold is exceeded, thermal
shutdown for that output occurs. The Gate Control Latch
drive to the output is switched off and a status flag (the OT
Bit) for the fault is set. The output shutdown action is independent of the IN input state. However, the Gate Control
Latch and OL Bit will be reset on the next rising edge of the IN
input and, if the fault still exists, the shutdown action will repeat.
ORed Fault Bits
It is important to note that the trigger input to the one-shot is
locked-out for the t INT duration and any fault that may have
occurred in the t INT window will not be displayed at the INT
output. However, all 8 fault bits may still be read as data
from the SO output when clock by the SCK input. The INT
fault output is provided as an interrupt signal to flag the
immediate occurrence of a fault and take appropriate action
as defined by the microcontroller to the SPI bus and the
users programming. The INT fault output may be ORed with
other ICs to provide a system microcontroller interrupt to
indicate the presence of a fault.
Diagnostic action for an OT fault includes feedback of the
fault status to the Serial Diagnostic Register for a SPI bus
data output. Also, as shown in the Block Diagram, the OT
fault status bit information is ORed into a one-shot that
drives an open drain to provide an INT interrupt signal output. The INT output has a specified timing from the one-shot
multi and is defined in the Electrical Specifications as t INT.
3
HIP0060
HIP0060 devices may be linked in cascade for the purposes
of SPI control. Serial data is clocked in and out of each
HIP0060 and then back to the host microcontroller. All linked
devices have a common control sequence. When CS goes
low, fault data is shifted to the Serial Diagnostic Register.
SCK must be low when CS goes low. Also, when CS goes
low, SO changes from a three-state to a low state and
remains low until SCK goes high. Serial data is transferred
by SCK. After the serial data is transferred, SCK must
remain low as CS goes high. The serial data transfer must
be a continuous sequence while CS is low.
Serial Diagnostic Link
A serial diagnostic link via the SPI bus provides the means
to clock fault data in and out of the fault register to the microcontroller. When the microcontroller receives an INT interrupt signal, data is clocked from the Serial Diagnostic
Register to determine what fault bit has been set. Appropriate action for the fault may then be taken, as defined by the
programming of the microcontroller.
Serial Diagnostic Register
Fault bits consist of one OT bit and one OL bit for each
switching channel (A, B, C and D). Data is transferred out
of SO MSB first on the rising edge of SCK after CS goes
low. Data is shifted into the input shift register on the falling
edge of SCK. The defined order of the DO0 to DO7 fault
bits is as follows:
Serial Peripheral Interface
The Serial Peripheral Interface (SPI) bus is system controlled by a host micro. The SPI bus controls the Serial Diagnostic Link with the CS (Chip Select), SCK, SI, SO and RST
(Reset) lines. Figures 4 and 5 define the timing and protocol
for the bus.
BIT
NAME
CONDITION REQUIRED TO SET BIT
DO0
OTA
OT in Output Driver A, TJ ≥ TLIM
Reset Operation
DO1
OTB
OT in Output Driver B, TJ ≥ TLIM
DO2
OTC
OT in Output Driver C, TJ ≥ TLIM
DO3
OTD
OT in Output Driver D, TJ ≥ TLIM
DO4
OLA
OL in Output Driver A, OFF Load > ROLD
DO5
OLB
OL in Output Driver B, OFF Load > ROLD
The RST input is an active low reset input. When RST is low,
the internal diagnostic flags are cleared but not the shift register. When RST is low, all outputs and output switches are
disabled. To clear the shift register, CS is switched from high
to low during or after a reset while there are no active faults,
jamming data from the cleared fault flags into the shift registor. The RST input has an internal pull-up to sustain a logic
high when floating.
DO6
OLC
OL in Output Driver C, OFF Load > ROLD
DO7
OLD
OL in Output Driver D, OFF Load > ROLD
The VDD input is the power supply to the 5V logic and the
POR function. When the VDD is less than the VDD(POR)
threshold, the output drivers are shutoff. To insure that the
diagnostic link shift register is correct after VDD is less than
VDD(POR), a manual reset must be executed.
VDD
+5V
4.7kΩ
INT
SOLENOID
OUTA
RST
OUTB
RELAY
VBATT
INA
INB
HIP0060
OUTC
LAMP
INC
OUTD
M
VBATT
MOTOR
IND
FIGURE 1. TYPICAL HIP0060 APPLICATION AS A LOW SIDE SWITCH FOR INDUCTIVE LOADS, LAMPS AND SMALL LINEAR
MOTORS OR STEPPER MOTORS
4
HIP0060
+5V
VDD
4.7kΩ
RST
4.7kΩ
+14.5V
OUTA
30Ω
OUTB
30Ω
OUTC
30Ω
INA
INB
50Ω
5V, 100µs
2% DUTY CYCLE
HIP0060
(TIMING TEST
CIRCUIT)
INC
FUNCTION GEN.
IND
30Ω
OUTD
GND
INT
5V
VIN
3V
1V
0V
tOFF
tON
tf
tr
14.5V
90%
90%
VOUT
0V
10%
10%
FIGURE 2. INPUT TO OUTPUT SWITCHING TIME DIAGRAM FOR EACH SWITCHING CHANNEL. THE CONDITIONS SHOWN
REFER TO THE TIMING TEST CIRCUIT
ENERGY (mJ)
10000
1000
100
10
0.1
SAFE OPERATING AREA
BELOW LINE
1
10
100
TIME (ms)
FIGURE 3. MAXIMUM SINGLE PULSE ENERGY SAFE OPERATING AREA FOR EACH CLAMPED OUTPUT DRIVER, TA = 25oC
5
HIP0060
Timing Diagrams
CS
SCK
(CPOL = 0, CPHA = 1)
MSB
6
5
4
3
2
1
LSB
INTERNAL STROBE FOR DATA CAPTURE
FIGURE 4. DATA AND CLOCK TIMING DIAGRAM
CS
tLEAD
SCK
tCYC
tfSCK
trSCK
DI6
DI1
tLAG
tWSCKH
tWSCKL
tSU
DI7
SI
D10
tDIS
SO
(THREE-STATE)
DO7
DO6
DO1
DO0
tV
FIGURE 5. BYTE TIMING DIAGRAM WITH ASYNCHRONOUS RESET. REFER TO THE ELECTRICAL SPECIFICATION FOR THE
HIGH AND LOW INPUT AND OUTPUT THRESHOLD LEVELS SHOWN FOR TIMING REFERENCE
6
HIP0060
Small Outline Plastic Packages (SOIC)
M24.3 (JEDEC MS-013-AD ISSUE C)
N
INDEX
AREA
0.25(0.010) M
H
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
B M
INCHES
E
SYMBOL
-B1
2
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
e
A1
B
0.25(0.010) M C A M
C
0.10(0.004)
B S
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact
7
MIN
MAX
NOTES
0.0926
0.1043
2.35
2.65
-
0.0040
0.0118
0.10
0.30
-
B
0.013
0.020
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.5985
0.6141
15.20
15.60
3
E
0.2914
0.2992
7.40
7.60
4
0.05 BSC
1.27 BSC
-
H
0.394
0.419
10.00
10.65
-
h
0.010
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
8o
0o
N
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
MILLIMETERS
A
α
NOTES:
MAX
A1
e
µα
MIN
24
0o
24
7
8o
Rev. 0 12/93
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