DATASHEET

ISL6209
®
Data Sheet
High Voltage Synchronous Rectified Buck
MOSFET Driver
The ISL6209 is a high frequency, dual MOSFET driver,
optimized to drive two N-Channel power MOSFETs in a
synchronous-rectified buck converter topology in mobile
computing applications. This driver, combined with an Intersil
Multi-Phase Buck PWM controller, such as ISL6216, ISL6244,
and ISL6247, forms a complete single-stage core-voltage
regulator solution for advanced mobile microprocessors.
The ISL6209 features 4A typical sink current for the lower gate
driver. The 4A typical sink current is capable of holding the
lower MOSFET gate during the PHASE node rising edge to
prevent the shoot-through power loss caused by the high dv/dt
of the PHASE node. The operation voltage matches the 30V
breakdown voltage of the MOSFETs commonly used in mobile
computer power supplies.
The ISL6209 also features a three-state PWM input that,
working together with most of Intersil multiphase PWM
controllers, will prevent a negative transient on the output
voltage when the output is being shut down. This feature
eliminates the Schottky diode, that is usually seen in a
microprocessor power system for protecting the
microprocessor, from reversed-output-voltage damage.
The ISL6209 has the capacity to efficiently switch power
MOSFETs at frequencies up to 2MHz. Each driver is capable of
driving a 3000pF load with a 8ns propagation delay and less
than a 10ns transition time. This product implements
bootstrapping on the upper gate with an internal bootstrap
Schottky diode, reducing implementation cost, complexity, and
allowing the use of higher performance, cost effective
N-Channel MOSFETs. Programmable dead-time with gate
threshold monitoring is integrated to prevent both MOSFETs
from conducting simultaneously.
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Technical Brief TB389 “PCB Land Pattern Design and
Surface Mount Guidelines for QFN Packages”
• Technical Brief TB447 “Guidelines for Preventing Boot-toPhase Stress on Half-Bridge MOSFET Driver ICs”
1
March 23, 2007
FN9132.2
Features
• Drives Two N-Channel MOSFETs
• Shoot-Through Protection
- Active gate threshold monitoring
- Programmable dead-time
• 30V Operation Voltage
• 0.4Ω On-Resistance and 4A Sink Current Capability
• Supports High Switching Frequency
- Fast output rise time
- Propagation delay 8ns
• Three-State PWM Input for Power Stage Shutdown
• Internal Bootstrap Schottky Diode
• QFN Package:
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Core Voltage Supplies for Intel and AMD® Mobile
Microprocessors
• High Frequency Low Profile DC/DC Converters
• High Current Low Output Voltage DC/DC Converters
• High Input Voltage DC/DC Converter
Ordering Information
PART
NUMBER
PART
MARKING
ISL6209CB*
ISL6209CB
TEMP.
RANGE
(°C)
PACKAGE
PKG.
DWG. #
-10 to +100 8 Ld SOIC
M8.15
ISL6209CBZ* ISL6209CBZ -10 to +100 8 Ld SOIC
(Note)
(Pb-free)
M8.15
ISL6209CR*
L8.3x3
209C
-10 to +100 8 Ld 3x3 QFN
*Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004, 2005, 2007. All Rights Reserved. Intel® is a registered trademark of Intel Corporation.
AMD® is a registered trademark of Advanced Micro Devices, Inc. All other trademarks mentioned are the property of their respective owners.
ISL6209
Pinouts
ISL6209
(8 LD QFN)
TOP VIEW
UGATE
1
8
PHASE
UGATE
PHASE
ISL6209
(8 LD SOIC)
TOP VIEW
BOOT
2
7
DELAY
8
7
PWM
3
6
VCC
GND
4
5
LGATE
66 DELAY
BOOT 1
PWM 2
3
4
GND
LGATE
5 VCC
ISL6209 Block Diagram
VCC
BOOT
DELAY
UGATE
PHASE
SHOOTTHROUGH
PROTECTION
CONTROL
LOGIC
PWM
VCC
LGATE
10K
GND
THERMAL PAD (FOR QFN PACKAGE ONLY)
FIGURE 1. BLOCK DIAGRAM
Timing Diagram
2.5V
PWM
tPDHU
tPDLU
tRU
tTSSHD
tRU
tFU
tFU
tPTS
1V
UGATE
LGATE
tPTS
1V
tRL
tFL
tTSSHD
tPDHL
tPDLL
tFL
2
ISL6209
Typical Application - Two Phase Converter Using ISL6209 Gate Drivers
VBAT
+5V
+5V
VCC
+5V
+VCORE
BOOT
FB
COMP
UGATE
VCC
VSEN
PWM1
PWM2
PGOOD
PWM
DRIVE
ISL6209
PHASE
DELAY
LGATE
MAIN
CONTROL
ISEN1
VID
ISEN2
VCC
FS
VBAT
+5V
BOOT
DACOUT
GND
UGATE
PWM
DELAY
DRIVE
ISL6209
PHASE
LGATE
FIGURE 2. TYPICAL APPLICATION
3
ISL6209
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
Input Voltage (VDELAY, VPWM) . . . . . . . . . . . . -0.3V to VCC + 0.3V
BOOT Voltage (VBOOT-GND). . . . . . . . . . . . . . . . . . . . . -0.3V to 33V
BOOT To PHASE Voltage (VBOOT-PHASE) . . . . . . -0.3V to 7V (DC)
-0.3V to 9V (<10ns)
PHASE Voltage (Note 1) . . . . . . . . . . . . . . . . . . . GND - 0.3V to 30V
GND - 8V (<20ns Pulse Width, 10μJ)
UGATE Voltage . . . . . . . . . . . . . . . . VPHASE - 0.3V (DC) to VBOOT
VPHASE - 5V (<20ns Pulse Width, 10μJ) to VBOOT
LGATE Voltage . . . . . . . . . . . . . . . GND - 0.3V (DC) to VCC + 0.3V
GND - 2.5V (<20ns Pulse Width, 5μJ) to VCC + 0.3V
Ambient Temperature Range . . . . . . . . . . . . . . . . . .-40°C to +125°C
Thermal Resistance (Typical)
θJA (°C/W)
θJC (°C/W)
SOIC Package (Note 2) . . . . . . . . . . . .
110
N/A
QFN Package (Notes 3, 4). . . . . . . . . .
80
15
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C
(SOIC - Lead Tips Only)
Recommended Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . .-10°C to +100°C
Maximum Operating Junction Temperature. . . . . . . . . . . . . +125°C
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. The Phase Voltage is capable of withstanding -7V when the BOOT pin is at GND.
2. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
3. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
4. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
85
-
μA
POR Rising
-
3.4
4.2
V
POR Falling
2.2
2.9
-
V
-
500
-
mV
0.40
0.52
0.60
V
VPWM = 5V
-
250
-
μA
VPWM = 0V
-
-250
-
μA
PWM Three-State Rising Threshold
VVCC = 5V
-
-
1.8
V
PWM Three-State Falling Threshold
VVCC = 5V
3.1
-
-
V
Three-State Shutdown Hold-off Time
VVCC = 5V, temperature = +25°C
-
150
-
ns
VCC SUPPLY CURRENT
Bias Supply Current
IVCC
PWM pin floating, VVCC = 5V
Hysteresis
BOOTSTRAP DIODE
Forward Voltage
VF
VVCC = 5V, forward bias current = 2mA
PWM INPUT
Input Current
IPWM
SWITCHING TIME
UGATE Rise Time (Note 5)
tRUGATE
VVCC = 5V, 3nF Load
-
8
-
ns
LGATE Rise Time (Note 5)
tRLGATE
VVCC = 5V, 3nF Load
-
8
-
ns
UGATE Fall Time (Note 5)
tFUGATE
VVCC = 5V, 3nF Load
-
8
-
ns
LGATE Fall Time (Note 5)
tFLGATE
VVCC = 5V, 3nF Load
-
4
-
ns
UGATE Turn-Off Propagation Delay
tPDLUGATE
VVCC = 5V, No Output Load, DELAY = VCC
-
13
-
ns
LGATE Turn-Off Propagation Delay
tPDLLGATE
VVCC = 5V, No Output Load, DELAY = VCC
-
13
-
ns
UGATE Turn-On Propagation Delay
tPDHUGATE
VVCC = 5V, Outputs Unloaded,
DELAY = VCC
10
20
30
ns
4
ISL6209
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted. (Continued)
PARAMETER
SYMBOL
LGATE Turn-On Propagation Delay
tPDHLGATE
TEST CONDITIONS
VVCC = 5V, Outputs Unloaded,
DELAY = VCC
MIN
TYP
MAX
UNITS
10
20
30
ns
OUTPUT
Upper Drive Source Resistance
RUGATE
500mA Source Current
-
1.0
2.5
Ω
Upper Driver Source Current (Note 5)
IUGATE
VUGATE-PHASE = 2.5V
-
2.0
-
A
Upper Drive Sink Resistance
RUGATE
500mA Sink Current
-
1.0
2.5
Ω
Upper Driver Sink Current (Note 5)
IUGATE
VUGATE-PHASE = 2.5V
-
2.0
-
A
Lower Drive Source Resistance
RLGATE
500mA Source Current
-
1.0
2.5
Ω
Lower Driver Source Current (Note 5)
ILGATE
VLGATE = 2.5V
-
2.0
-
A
Lower Drive Sink Resistance
RLGATE
500mA Sink Current
-
0.4
1.0
Ω
Lower Driver Sink Current (Note 5)
ILGATE
VLGATE = 2.5V
-
4.0
-
A
NOTE:
5. Guaranteed by characterization, not 100% tested in production.
Functional Pin Description
UGATE (Pin 1 for SOIC-8, Pin 8 for QFN)
The UGATE pin is the upper gate drive output. Connect to
the gate of high-side power N-Channel MOSFET.
BOOT (Pin 2 for SOIC-8, Pin 1 for QFN)
DELAY (Pin 7 for SOIC-8, Pin 6 for QFN)
The DELAY pin sets the dead-time between gate switching
for the ISL6209. Connect a resistor to GND from this pin to
adjust the dead-time, refer to Figure 4. Tie this pin to VCC to
disable the delay circuitry. See Shoot-Through Protection
section for more detail.
BOOT is the floating bootstrap supply pin for the upper gate
drive. Connect the bootstrap capacitor between this pin and
the PHASE pin. The bootstrap capacitor provides the charge
to turn on the upper MOSFET. See the Bootstrap Diode and
Capacitor section under DESCRIPTION for guidance in
choosing the appropriate capacitor value.
PHASE (Pin 8 for SOIC-8, Pin 7 for QFN)
PWM (Pin 3 for SOIC-8, Pin 2 for QFN)
Operation
The PWM signal is the control input for the driver. The PWM
signal can enter three distinct states during operation, see the
three-state PWM Input section under DESCRIPTION for further
details. Connect this pin to the PWM output of the controller. In
addition, place a 500kΩ resistor to ground from this pin. This
allows for proper three-state operation under all start-up
conditions.
Designed for speed, the ISL6209 dual MOSFET driver controls
both high-side and low-side N-Channel FETs from one
externally provided PWM signal.
GND (Pin 4 for SOIC-8, Pin 3 for QFN)
GND is the ground pin. All signals are referenced to this
node.
LGATE (Pin 5 for SOIC-8, Pin 4 for QFN)
LGATE is the lower gate drive output. Connect to gate of the
low-side power N-Channel MOSFET.
VCC (Pin 6 for SOIC-8, Pin 5 for QFN)
Connect the VCC pin to a +5V bias supply. Place a high
quality bypass capacitor from this pin to GND.
5
Connect the PHASE pin to the source of the upper MOSFET
and the drain of the lower MOSFET. This pin provides a
return path for the upper gate driver.
Description
A rising edge on PWM initiates the turn-off of the lower
MOSFET (see Timing Diagram). After a short propagation
delay [tPDLLGATE], the lower gate begins to fall. Typical fall
times [tFLGATE] are provided in the Electrical Specifications
section. Adaptive shoot-through circuitry monitors the
LGATE voltage and determines the upper gate delay time
[tPDHUGATE], based on how quickly the LGATE voltage
drops below 1V. This prevents both the lower and upper
MOSFETs from conducting simultaneously, or shootthrough. Once this delay period is completed, the upper gate
drive begins to rise [tRUGATE], and the upper MOSFET
turns on.
A falling transition on PWM indicates the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
propagation delay [tPDLUGATE] is encountered before the
upper gate begins to fall [tFUGATE]. Again, the adaptive
ISL6209
shoot-through circuitry determines the lower gate delay time
tPDHLGATE. The upper MOSFET gate-to-source voltage is
monitored, and the lower gate is allowed to rise, after the
upper MOSFET gate-to-source voltage drops below 1V. The
lower gate then rises [tRLGATE], turning on the lower
MOSFET.
by the addition or removal of the additional dead-time. Refer
to Figure 3 and Figure 4 for more detail.
FCCM = VCC or GND
GATE B
GATE A
This driver is optimized for converters with large step down
ratio, such as those used in a mobile-computer core voltage
regulator. The lower MOSFET is usually sized much larger.
This driver is optimized for converters with large step down
compared to the upper MOSFET because the lower
MOSFET conducts for a much longer time in a switching
period. The lower gate driver is therefore sized much larger
to meet this application requirement. The 0.4Ω on-resistance
and 4A sink current capability enable the lower gate driver to
absorb the current injected to the lower gate through the
drain-to-gate capacitor of the lower MOSFET and prevent a
shoot through caused by the high dv/dt of the phase node.
Adaptive Shoot-Through Protection
1V
FCCM = RESISTOR to VCC or GND
GATE B
GATE A
Three-State PWM Input
A unique feature of the ISL6209 and other Intersil drivers is
the addition of a shutdown window to the PWM input. If the
PWM signal enters and remains within the shutdown window
for a set holdoff time, the output drivers are disabled and
both MOSFET gates are pulled and held low. The shutdown
state is removed when the PWM signal moves outside the
shutdown window. Otherwise, the PWM rising and falling
thresholds outlined in the ELECTRICAL SPECIFICATIONS
determine when the lower and upper gates are enabled.
During start-up, PWM should be in the three-state position
(1/2 VCC) until actively driven by the controller IC.
Adaptive Protection with Delay
tdelay = 5n - 50ns
1V
FIGURE 3. PROGRAMMABLE DEAD-TIME
4
Shoot-Through Protection
50
The ISL6209 driver delivers shoot-through protection by
incorporating gate threshold monitoring and programmable
dead-time to prevent upper and lower MOSFETs from
conducting simultaneously, thereby shorting the input supply
to ground. Gate threshold monitoring ensures that one gate
is OFF before the other is allowed to turn ON.
45
DEAD-TIME (ns)
During turn-off of the lower MOSFET, the LGATE voltage is
monitored until it reaches a 1V threshold, at which time the
UGATE is released to rise. Internal circuitry monitors the
upper MOSFET gate-to-source voltage during UGATE
turn-off. Once the upper MOSFET gate-to-source voltage
has dropped below a threshold of 1V, the LGATE is allowed
to rise.
40
35
30
tDELAY
25
20
15
10
5
0
0
In addition to gate threshold monitoring, a programmable
delay between MOSFET switching can be accomplished by
placing a resistor from the DELAY pin to ground. This delay
allows for maximum design flexibility over MOSFET
selection. The delay can be programmed from 5ns to 50ns. If
not desired, the DELAY pin must be tied to VCC to disable
the delay circuitry. Gate threshold monitoring is not affected
6
50
100
150
200
250
RDELAY (kΩ)
FIGURE 4. ADDITIONAL PROGRAMMED DEAD-TIME
(tDELAY) vs DELAY RESISTOR VALUE
300
ISL6209
The equation governing the dead-time seen in Figure 4 is
expressed as:
T DELAY = [ ( 160 × 10
– 15
) × R DELAY ] + 6ns
The equation can be rewritten to solve for RDELAY as
follows:
( T DELAY – 6ns )
R DELAY = -------------------------------------------160 × 10 – 15
will push the IC beyond the maximum recommended
operating junction temperature of 125°C. The maximum
allowable IC power dissipation for the SO-8 package is
approximately 800mW. When designing the driver into an
application, it is recommended that the following calculation
be performed to ensure safe operation at the desired
frequency for the selected MOSFETs. The power dissipated
by the driver is approximated as:
P = f sw ( 1.5V U Q + V L Q ) + I VCC V
U
L
CC
Internal Bootstrap Diode
This driver features an internal bootstrap Schottky diode.
Simply adding an external capacitor across the BOOT and
PHASE pins completes the bootstrap circuit.
The bootstrap capacitor must have a maximum voltage
rating above the maximum battery voltage plus 5V. The
bootstrap capacitor can be chosen from the following
equation:
where fsw is the switching frequency of the PWM signal. VU
and VL represent the upper and lower gate rail voltage. QU
and QL is the upper and lower gate charge determined by
MOSFET selection and any external capacitance added to
the gate pins. The IVCC VCC product is the quiescent power
of the driver and is typically negligible.
1000
Q GATE
C BOOT ≥ -----------------------ΔV BOOT
QL = 100nC
QU =100nC
800
As an example, suppose an upper MOSFET has a gate
charge, QGATE , of 25nC at 5V and also assume the droop in
the drive voltage over a PWM cycle is 200mV. One will find
that a bootstrap capacitance of at least 0.125μF is required.
The next larger standard value capacitance is 0.22μF. A
good quality ceramic capacitor is recommended.
QU = 50nC
QL = 50nC
QL = 200nC
700
POWER (mW)
where QGATE is the amount of gate charge required to fully
charge the gate of the upper MOSFET. The ΔVBOOT term is
defined as the allowable droop in the rail of the upper drive.
600
QU = 20nC
500
QL = 50nC
400
300
200
100
0
2.0
0
1.8
200
400
600
800
1000 1200 1400 1600 1800 2000
FREQUENCY (kHz)
1.6
CBOOT_CAP (µF)
QU =50nC
900
FIGURE 6. POWER DISSIPATION vs FREQUENCY
1.4
Layout Considerations
1.2
1.0
Reducing Phase Ring
0.8
QGATE = 100nC
0.6
nC
50
0.4
0.2
20nC
0.0
0.0
0.1
0.2
0.3
0.4 0.5 0.6 0.7
ΔVBOOT_CAP (V)
0.8
0.9
1.0
FIGURE 5. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
Power Dissipation
Package power dissipation is mainly a function of the
switching frequency and total gate charge of the selected
MOSFETs. Calculating the power dissipation in the driver for
a desired application is critical to ensuring safe operation.
Exceeding the maximum allowable power dissipation level
7
The parasitic inductances of the PCB and power devices
(both upper and lower FETs) could cause increased PHASE
ringing, which may lead to voltages that exceed the absolute
maximum rating of the devices. When PHASE rings below
ground, the negative voltage could add charge to the
bootstrap capacitor through the internal bootstrap diode.
Under worst-case conditions, the added charge could
overstress the BOOT and/or PHASE pins. To prevent this
from happening, the user should perform a careful layout
inspection to reduce trace inductances, and select low lead
inductance MOSFETs and drivers. D2PAK and DPAK
packaged MOSFETs have high parasitic lead inductances,
as opposed to SOIC-8. If higher inductance MOSFETs must
be used, a Schottky diode is recommended across the lower
MOSFET to clamp negative PHASE ring.
ISL6209
A good layout would help reduce the ringing on the phase
and gatenodes significantly:
1. Avoid using vias for decoupling components where
possible, especially in the BOOT-to-PHASE path. Little or
no use of vias for VCC and GND is also recommended.
Decoupling loops should be short.
2. All power traces (UGATE, PHASE, LGATE, GND, VCC)
should be short and wide, and avoid using vias. If vias
must be used, two or more vias per layer transition is
recommended.
3. Keep the SOURCE of the upper FET as close as
thermally possible to the DRAIN of the lower FET.
4. Keep the connection in between the SOURCE of lower
FET and power ground wide and short.
5. Input capacitors should be placed as close to the DRAIN
of the upper FET and the SOURCE of the lower FET as
thermally possible.
NOTE: Refer to Intersil Tech Brief TB447 for more information.
8
Thermal Management
For maximum thermal performance in high current, high
switching frequency applications, connecting the thermal
pad of the QFN part to the power ground with multiple vias,
or placing a low noise copper plane underneath the SOIC
part is recommended. This heat spreading allows the part to
achieve its full thermal potential.
Suppressing MOSFET Gate Leakage
With VCC at ground potential, UGATE and LGATE are high
impedance. In this state, any stray leakage has the potential
to deliver charge to either gate. If UGATE receives sufficient
charge to bias the device on (Note: Internal circuitry prevents
leakage currents from charging above 1.8V), a low
impedance path will be connected between the MOSFET
drain and PHASE. If the input power supply is present and
active, the system could see potentially damaging currents.
Worst-case leakage currents are on the order of pico-amps;
therefore, a 10kΩ resistor, connected from UGATE to
PHASE, is more than sufficient to bleed off any stray leakage
current. This resistor will not affect the normal performance
of the driver or reduce its efficiency.
ISL6209
Package Outline Drawing
L8.3x3
8 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 3/07
3.00
4X 0.65
A
B
6
PIN #1 INDEX AREA
8
7
6
PIN 1
INDEX AREA
1
5
2
3.00
6
(4X)
1 .10 ± 0 . 15
0.15
4
3
0.10 M C A B
4 8X 0.28 ± 0.05
TOP VIEW
8X 0.60 ± 0.15
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0 . 90 ± 0.1
( 4X 0 . 65 )
( 2. 60 TYP )
C
BASE PLANE
SEATING PLANE
0.08 C
(
1. 10 )
SIDE VIEW
( 8X 0 . 28 )
C
0 . 2 REF
5
0 . 00 MIN.
0 . 05 MAX.
( 8X 0 . 80)
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
9
ISL6209
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
N
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
H
0.25(0.010) M
B M
INCHES
E
SYMBOL
-B-
1
2
3
L
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
MIN
MAX
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.1890
0.1968
4.80
5.00
3
E
0.1497
0.1574
3.80
4.00
4
e
α
B S
0.050 BSC
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
N
α
NOTES:
MILLIMETERS
8
0°
8
8°
0°
7
8°
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
10
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