DATASHEET

ISL6594D
®
Data Sheet
December 3, 2007
Advanced Synchronous Rectified Buck
MOSFET Drivers with Protection Features
The ISL6594D is high frequency MOSFET driver specifically
designed to drive upper and lower power N-Channel
MOSFETs in a synchronous rectified buck converter
topology. This driver combined with the ISL6594D Digital
Multi-Phase Buck PWM controller and N-Channel MOSFETs
forms a complete core-voltage regulator solution for
advanced microprocessors.
The ISL6594D drives both upper and lower gates over a range
of 4.5V to 13.2V. This drive-voltage provides the flexibility
necessary to optimize applications involving trade-offs between
gate charge and conduction losses.
An advanced adaptive zero shoot-through protection is
integrated to prevent both the upper and lower MOSFETs
from conducting simultaneously and to minimize the dead
time. The ISL6594D includes an overvoltage protection
feature operational before VCC exceeds its turn-on
threshold, at which the PHASE node is connected to the
gate of the low side MOSFET (LGATE). The output voltage
of the converter is then limited by the threshold of the low
side MOSFET, which provides some protection to the
microprocessor if the upper MOSFET(s) is shorted.
The ISL6594D also features an input that recognizes a
high-impedance state, working together with Intersil multiphase PWM controllers to prevent negative transients on the
controlled output voltage when operation is suspended. This
feature eliminates the need for the Schottky diode that may
be utilized in a power system to protect the load from
negative output voltage damage.
Ordering Information
Features
• Dual MOSFET Drives for Synchronous Rectified Bridge
• Pin-to-pin Compatible with ISL6596
• Advanced Adaptive Zero Shoot-Through Protection
- Body Diode Detection
- Auto-zero of rDS(ON) Conduction Offset Effect
• Adjustable Gate Voltage for Optimal Efficiency
• 36V Internal Bootstrap Schottky Diode
• Bootstrap Capacitor Overcharging Prevention
• Supports High Switching Frequency (up to 2MHz)
- 3A Sinking Current Capability
- Fast Rise/Fall Times and Low Propagation Delays
• Optimized for 3.3V PWM Input
• Three-State PWM Input for Output Stage Shutdown
• Three-State PWM Input Hysteresis for Applications With
Power Sequencing Requirement
• Pre-POR Overvoltage Protection
• VCC Undervoltage Protection
• Expandable Bottom Copper Pad for Enhanced Heat
Sinking
• Dual Flat No-Lead (DFN) Package
- Near Chip-Scale Package Footprint; Improves PCB
Efficiency and Thinner in Profile
• Pb-Free (RoHS Compliant)
Applications
• Optimized for POL DC/DC Converters for IBA Systems
PART NUMBER
PART
TEMP.
(Note)
MARKING RANGE (°C)
ISL6594DCBZ
FN9282.1
PACKAGE
(Pb-free)
PKG.
DWG. #
• Core Regulators for Intel® and AMD® Microprocessors
M8.15
• High Current DC/DC Converters
6594 DCBZ
0 to +85
8 Ld SOIC
ISL6594DCBZ-T* 6594 DCBZ
0 to +85
8 Ld SOIC
M8.15
Tape and Reel
ISL6594DCRZ
94DZ
0 to +85
10 Ld 3x3 DFN L10.3x3
ISL6594DCRZ-T* 94DZ
0 to +85
10 Ld 3x3 DFN L10.3x3
Tape and Reel
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets; molding compounds/die attach
materials and 100% matte tin plate PLUS ANNEAL - e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the
Pb-free requirements of IPC/JEDEC J STD-020.
1
• High Frequency and High Efficiency VRM and VRD
Related Literature
Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
Technical Brief TB389 “PCB Land Pattern Design and
Surface Mount Guidelines for QFN (MLFP) Packages”
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006, 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL6594D
Pinouts
ISL6594DCR
(10 LD 3x3 DFN)
TOP VIEW
ISL6594DCB
(8 LD SOIC)
TOP VIEW
UGATE
1
8
PHASE
BOOT
2
7
PVCC
PWM
3
6
VCC
GND
4
5
LGATE
1
UGATE
BOOT
2
N/C
3
PWM
4
GND
5
10 PHASE
9 PVCC
GND
8
N/C
7
VCC
6 LGATE
Block Diagram
ISL6594D
UVCC
BOOT
VCC
UGATE
Pre-POR OVP
FEATURES
+5V
13.6k
PWM
6.4k
SHOOTTHROUGH
PROTECTION
POR/
CONTROL
LOGIC
PHASE
(LVCC)
PVCC
UVCC = PVCC FOR ISL6594D
LGATE
GND
PAD
2
FOR DFN DEVICES, THE PAD ON THE BOTTOM SIDE OF
THE PACKAGE MUST BE SOLDERED TO THE CIRCUIT’S GROUND.
FN9282.1
December 3, 2007
Typical Application - 4 Channel Converter Using ISL6592 and ISL6594D Gate Drivers
+12V
ISL6594D
+5V
1 UGATE
PHASE 8
2 BOOT
PVCC 7
3 PWM
VCC 6
4 GND
LGATE 5
3
+3.3V
VDD
V12_SEN
1 UGATE
PHASE 8
OUT1
2 BOOT
PVCC 7
VID4
OUT2
3 PWM
VCC 6
VID3
ISEN1
4 GND
LGATE 5
VID2
OUT3
ISL6592
VID1
OUT4
VID0
ISEN2
VID5
OUT5
LL0
OUT6
LL1
ISEN3
OUTEN
OUT7
OUT8
TO µP
VCC_PWRGD
Vout
ISL6594D
1 UGATE
PHASE 8
2 BOOT
PVCC 7
3 PWM
VCC 6
4 GND
LGATE 5
RTN
ISEN4
OUT9
RESET_N
OUT10
ISL6594D
ISEN5
1 UGATE
PHASE 8
PVCC 7
FAULT
FAULT1
OUT11
2 BOOT
OUTPUTS
FAULT2
OUT12
3 PWM
VCC 6
ISEN6
4 GND
LGATE 5
FN9282.1
December 3, 2007
I2C I/F
BUS
SDA
TEMP_SEN
SCL
CAL_CUR_EN
RTHERM
SADDR
CAL_CUR_SEN
VSENP
VSENN
ISL6594D
FROM µP
ISL6594D
GND
ISL6594D
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V
Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3V
BOOT Voltage (VBOOT-GND). . . . . . . . . . . . . . . . . . . . . . . . . . . .36V
Input Voltage (VPWM) . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 7V
UGATE. . . . . . . . . . . . . . . . . . . VPHASE - 0.3VDC to VBOOT + 0.3V
VPHASE - 3.5V (<100ns Pulse Width, 2µJ) to VBOOT + 0.3V
LGATE . . . . . . . . . . . . . . . . . . . . . . GND - 0.3VDC to VPVCC + 0.3V
GND - 5V (<100ns Pulse Width, 2µJ) to VPVCC + 0.3V
PHASE. . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3VDC to 15VDC
GND - 8V (<400ns, 20µJ) to 30V (<200ns, VBOOT-GND<36V))
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . Class I JEDEC STD
Thermal Resistance
θJA (°C/W)
θJC (°C/W)
SOIC Package (Note 1) . . . . . . . . . . . .
100
N/A
DFN Package (Notes 2, 3) . . . . . . . . . .
48
7
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . 0°C to +85°C
Maximum Operating Junction Temperature. . . . . . . . . . . . . +125°C
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8V to 13.2V
Supply Voltage Range, PVCC . . . . . . . . . . . . . . . . 5V to 12V ±10%
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
3. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
IVCC
ISL6594D, fPWM = 300kHz, VVCC = 12V
-
4.5
-
mA
IVCC
ISL6594D, fPWM = 1MHz, VVCC = 12V
-
5
-
mA
IPVCC
ISL6594D, fPWM = 300kHz, VPVCC = 12V
-
7.5
-
mA
IPVCC
ISL6594D, fPWM = 1MHz, VPVCC = 12V
-
8.5
-
mA
VCC Rising Threshold
6.1
6.4
6.7
V
VCC Falling Threshold
4.7
5.0
5.3
V
VPWM = 3.3V
-
400
-
µA
VPWM = 0V
-
-350
-
µA
PWM Rising Threshold (Note 4)
VCC = 12V
-
1.70
-
V
PWM Falling Threshold (Note 4)
VCC = 12V
-
1.30
-
V
Typical Three-State Shutdown Window
VCC = 12V
1.23
-
1.82
V
Three-State Lower Gate Falling Threshold
VCC = 12V
-
1.18
-
V
Three-State Lower Gate Rising Threshold
VCC = 12V
-
0.76
-
V
Three-State Upper Gate Rising Threshold
VCC = 12V
-
2.36
-
V
Three-State Upper Gate Falling Threshold
VCC = 12V
-
1.96
-
V
-
245
-
ns
VCC SUPPLY CURRENT
Bias Supply Current
Gate Drive Bias Current
POWER-ON RESET AND ENABLE
PWM INPUT (See Timing Diagram on page 6)
Input Current
IPWM
Shutdown Hold-off Time
tTSSHD
UGATE Rise Time (Note 4)
tRU
VPVCC = 12V, 3nF Load, 10% to 90%
-
26
-
ns
LGATE Rise Time (Note 4)
tRL
VPVCC = 12V, 3nF Load, 10% to 90%
-
18
-
ns
UGATE Fall Time (Note 4)
tFU
VPVCC = 12V, 3nF Load, 90% to 10%
-
18
-
ns
LGATE Fall Time (Note 4)
tFL
VPVCC = 12V, 3nF Load, 90% to 10%
-
12
-
ns
VPVCC = 12V, 3nF Load, Adaptive
-
10
-
ns
UGATE Turn-On Propagation Delay (Note 4)
4
tPDHU
FN9282.1
December 3, 2007
ISL6594D
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
LGATE Turn-On Propagation Delay (Note 4)
tPDHL
VPVCC = 12V, 3nF Load, Adaptive
-
10
-
ns
UGATE Turn-Off Propagation Delay (Note 4)
tPDLU
VPVCC = 12V, 3nF Load
-
10
-
ns
LGATE Turn-Off Propagation Delay (Note 4)
tPDLL
VPVCC = 12V, 3nF Load
-
10
-
ns
LG/UG Three-State Propagation Delay (Note 4)
tPDTS
VPVCC = 12V, 3nF Load
-
10
-
ns
Upper Drive Source Current
IU_SOURCE VPVCC = 12V, 3nF Load
-
1.25
-
A
Upper Drive Source Impedance
RU_SOURCE 150mA Source Current
1.4
2.0
3.0
Ω
-
2
-
A
0.9
1.65
3.0
Ω
-
2
-
A
0.85
1.3
2.2
Ω
-
3
-
A
0.60
0.94
1.35
Ω
OUTPUT (Note 4)
Upper Drive Sink Current
IU_SINK
VPVCC = 12V, 3nF Load
Upper Drive Sink Impedance
RU_SINK
150mA Sink Current
Lower Drive Source Current
IL_SOURCE
Lower Drive Source Impedance
RL_SOURCE 150mA Source Current
VPVCC = 12V, 3nF Load
Lower Drive Sink Current
IL_SINK
VPVCC = 12V, 3nF Load
Lower Drive Sink Impedance
RL_SINK
150mA Sink Current
NOTE:
4. Limits should be considered typical and are not production tested.
Functional Pin Description
PACKAGE PIN #
SOIC
DFN
PIN
SYMBOL
1
1
UGATE
Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.
2
2
BOOT
Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See “Internal Bootstrap
Device” on page 7 for guidance in choosing the capacitor value.
-
3, 8
N/C
3
4
PWM
The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation, see
“Three-State PWM Input” on page 6 for further details. Connect this pin to the PWM output of the controller.
4
5
GND
Bias and reference ground. All signals are referenced to this node. It is also the power ground return of the driver.
5
6
LGATE
6
7
VCC
7
9
PVCC
This pin supplies power to both upper and lower gate drives. Its operating range is +4.5V to 13.2V. Place a high
quality low ESR ceramic capacitor from this pin to GND.
8
10
PHASE
Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides
a return path for the upper gate drive.
9
11
PAD
FUNCTION
No Connection.
Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.
Its operating range is +6.8V to 13.2V. Place a high quality low ESR ceramic capacitor from this pin to GND.
Connect this pad to the power ground plane (GND) via thermally enhanced connection.
5
FN9282.1
December 3, 2007
ISL6594D
Description
1.18V < PWM < 2.36V
0.76V < PWM < 1.96V
PWM
tPDLU
tPDHU
tTSSHD
tPDTS
tPDTS
UGATE
tFU
tRU
LGATE
tFL
tRL
tTSSHD
tPDLL
tPDHL
FIGURE 1. TIMING DIAGRAM
Operation
Designed for versatility and speed, the ISL6594D MOSFET
driver controls both high-side and low-side N-Channel FETs
of a half-bridge power train from one externally provided
PWM signal.
Prior to VCC exceeding its POR level, the Pre-POR
overvoltage protection function is activated during initial
start-up; the upper gate (UGATE) is held low and the lower
gate (LGATE), controlled by the Pre-POR overvoltage
protection circuits, is connected to the PHASE. Once the
VCC voltage surpasses the VCC Rising Threshold (see
“Electrical Specifications” on page 4), the PWM signal takes
control of gate transitions. A rising edge on PWM initiates
the turn-off of the lower MOSFET (see Timing Diagram on
page 6). After a short propagation delay [tPDLL], the lower
gate begins to fall. Typical fall times [tFL] are provided in the
“Electrical Specifications” on page 4. Adaptive shoot-through
circuitry monitors the LGATE voltage and determines the
upper gate delay time [tPDHU]. This prevents both the lower
and upper MOSFETs from conducting simultaneously. Once
this delay period is complete, the upper gate drive begins to
rise [tRU] and the upper MOSFET turns on.
A falling transition on PWM results in the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
propagation delay [tPDLU] is encountered before the upper
gate begins to fall [tFU]. Again, the adaptive shoot-through
circuitry determines the lower gate delay time, tPDHL. The
PHASE voltage and the UGATE voltage are monitored, and
the lower gate is allowed to rise after PHASE drops below a
level or the voltage of UGATE to PHASE reaches a level
depending upon the current direction (See next section for
details). The lower gate then rises [tRL], turning on the lower
MOSFET.
6
Advanced Adaptive Zero Shoot-Through Deadtime
Control (Patent Pending)
The ISL6594D driver incorporates a unique adaptive
deadtime control technique to minimize deadtime, resulting
in high efficiency from the reduced freewheeling time of the
lower MOSFETs’ body-diode conduction, and to prevent the
upper and lower MOSFETs from conducting simultaneously.
This is accomplished by ensuring either rising gate turns on
its MOSFET with minimum and sufficient delay after the
other has turned off.
During turn-off of the lower MOSFET, the PHASE voltage is
monitored until it reaches a -0.2V/+0.8V trip point within
15ns for a forward/reverse current, at which time the UGATE
turns on after 10ns propagation delay. An auto-zero
comparator is used to correct the rDS(ON) drop in the phase
voltage preventing from false detection of the -0.2V phase
level during rDS(ON) conduction period. In the case of zero
current and/or 15ns phase detect expired, the UGATE turns
on after 10ns propagation delay. During the phase detection,
the disturbance of LGATE’s falling transition on the PHASE
node is blanked out to prevent falsely tripping. Once the
PHASE is high, the advanced adaptive shoot-through
circuitry monitors the PHASE and UGATE voltages during a
PWM falling edge and the subsequent UGATE turn-off. If
either the UGATE falls to less than 1.75V above the PHASE
or the PHASE falls to less than +0.8V, the LGATE is
released to turn on after 10ns propagation delay.
Three-State PWM Input
A unique feature of these drivers and other Intersil drivers is
the addition of a shutdown window to the PWM input. If the
PWM signal enters and remains within the shutdown window
for a set hold-off time, the driver outputs are disabled and
both MOSFET gates are pulled and held low. The shutdown
state is removed when the PWM signal moves outside the
shutdown window. Otherwise, the PWM rising and falling
FN9282.1
December 3, 2007
ISL6594D
thresholds outlined in the “Electrical Specifications” on
page 4 determine when the lower and upper gates are
enabled.
This feature helps prevent a negative transient on the output
voltage when the output is shut down, eliminating the
Schottky diode that is used in some systems for protecting
the load from reversed output voltage events.
In addition, more than 400mV hysteresis also incorporates
into the three-state shutdown window to eliminate PWM
input oscillations due to the capacitive load seen by the
PWM input through the body diode of the controller’s PWM
output when the power-up and/or power-down sequence of
bias supplies of the driver and PWM controller are required.
where QG1 is the amount of gate charge per upper MOSFET
at VGS1 gate-source voltage and NQ1 is the number of
control MOSFETs. The DVBOOT_CAP term is defined as the
allowable droop in the rail of the upper gate drive.
As an example, suppose two IRLR7821 FETs are chosen as
the upper MOSFETs. The gate charge, QG, from the data
sheet is 10nC at 4.5V (VGS) gate-source voltage. Then the
QGATE is calculated to be 53nC for PVCC = 12V. We will
assume a 200mV droop in drive voltage over the PWM
cycle. We find that a bootstrap capacitance of at least
0.267µF is required.
1.6
1.4
Power-On Reset (POR) Function
Pre-POR Overvoltage Protection
Internal Bootstrap Device
Both drivers feature an internal bootstrap Schottky diode.
Simply adding an external capacitor across the BOOT and
PHASE pins completes the bootstrap circuit. The bootstrap
function is also designed to prevent the bootstrap capacitor
from overcharging due to the large negative swing at the
trailing-edge of the PHASE node. This reduces voltage
stress on the boot to phase pins.
The bootstrap capacitor must have a maximum voltage
rating above PVCC + 5V and its capacitance value can be
chosen from Equation 1:
(EQ. 1)
Q G1 • PVCC
Q GATE = ------------------------------------ • N Q1
V GS1
7
1.0
0.8
0.6
QGATE = 100nC
0.4
Prior to VCC exceeding its POR level, the upper gate is held
low and the lower gate is controlled by the overvoltage
protection circuits. The upper gate driver is powered from
PVCC and will be held low when a voltage of 2.75V or higher
is present on PVCC as VCC surpasses its POR threshold.
The PHASE is connected to the gate of the low side
MOSFET (LGATE), which provides some protection to the
microprocessor if the upper MOSFET(s) is shorted during
start-up, normal, or shutdown conditions. For complete
protection, the low side MOSFET should have a gate
threshold well below the maximum voltage rating of the
load/microprocessor.
Q GATE
C BOOT_CAP ≥ -------------------------------------ΔV BOOT_CAP
1.2
CBOOT_CAP (µF)
During initial start-up, the VCC voltage rise is monitored.
Once the rising VCC voltage exceeds 6.4V (typically),
operation of the driver is enabled and the PWM input signal
takes control of the gate drives. If VCC drops below the
falling threshold of 5.0V (typically), operation of the driver is
disabled.
50nC
0.2
20nC
0.0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
ΔVBOOT_CAP (V)
FIGURE 2. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
Gate Drive Voltage Versatility
The ISL6594D provides the user flexibility in choosing the
gate drive voltage for efficiency optimization. The ISL6594D
ties the upper and lower drive rails together. Simply applying
a voltage from +4.5V up to 13.2V on PVCC sets both gate
drive rail voltages simultaneously, while VCC’s operating
range is from +6.8V up to 13.2V. For 5V operation,
ISL6596/ISL6609 is recommended.
Power Dissipation
Package power dissipation is mainly a function of the
switching frequency (fSW), the output drive impedance, the
external gate resistance, and the selected MOSFET’s internal
gate resistance and total gate charge. Calculating the power
dissipation in the driver for a desired application is critical to
ensure safe operation. Exceeding the maximum allowable
power dissipation level will push the IC beyond the maximum
recommended operating junction temperature of +125°C. The
maximum allowable IC power dissipation for the SO8 package
is approximately 800mW at room temperature, while the
power dissipation capacity in the DFN package, with an
exposed heat escape pad, is more than 1.5W. The DFN
package is more suitable for high frequency applications. See
“Layout Considerations” on page 8 for thermal transfer
FN9282.1
December 3, 2007
ISL6594D
improvement suggestions. When designing the driver into an
application, it is recommended that the following calculations
are used to ensure safe operation at the desired frequency for
the selected MOSFETs. The total gate drive power losses due
to the gate charge of MOSFETs and the driver’s internal
circuitry and their corresponding average driver current can
be estimated with Equations 2 and 3, respectively:
P Qg_TOT = P Qg_Q1 + P Qg_Q2 + I Q • VCC
BOOT
PVCC
D
CGD
RHI1
RLO1
G
RG1
CDS
RGI1
CGS
Q1
S
(EQ. 2)
PHASE
Q G1 • PVCC 2
P Qg_Q1 = --------------------------------------- • f SW • N Q1
V GS1
FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
Q G2 • PVCC 2
P Qg_Q2 = --------------------------------------- • f SW • N Q2
V GS2
PVCC
D
⎛ Q G1 • PVCC • N Q1 Q G2 • PVCC • N Q2⎞
I DR = ⎜ ----------------------------------------------------- + -----------------------------------------------------⎟ • f SW + I Q
V GS1
V GS2
⎝
⎠
CGD
RHI2
G
CDS
(EQ. 3)
RLO2
where the gate charge (QG1 and QG2) is defined at a
particular gate to source voltage (VGS1and VGS2) in the
corresponding MOSFET datasheet; IQ is the driver’s total
quiescent current with no load at both drive outputs; NQ1
and NQ2 are number of upper and lower MOSFETs,
respectively; PVCC is the drive voltage for both upper and
lower FETs. The IQ*VCC product is the quiescent power of
the driver without capacitive load and is typically 116mW at
300kHz and VCC = PVCC = 12V.
The total gate drive power losses are dissipated among the
resistive components along the transition path. The drive
resistance dissipates a portion of the total gate drive power
losses, the rest will be dissipated by the external gate
resistors (RG1 and RG2) and the internal gate resistors
(RGI1 and RGI2) of MOSFETs. Figures 3 and 4 show the
typical upper and lower gate drives turn-on transition path.
The power dissipation on the driver can be roughly
estimated as:
P DR = P DR_UP + P DR_LOW + I Q • VCC
(EQ. 4)
R LO1
R HI1
⎛
⎞ P Qg_Q1
P DR_UP = ⎜ -------------------------------------- + ----------------------------------------⎟ • --------------------R
+
R
R
+
R
2
⎝ HI1
EXT1
LO1
EXT1⎠
R LO2
R HI2
⎛
⎞ P Qg_Q2
P DR_LOW = ⎜ -------------------------------------- + ----------------------------------------⎟ • --------------------R
+
R
R
+
R
2
⎝ HI2
EXT2
LO2
EXT2⎠
R GI1
R EXT1 = R G1 + ------------N
Q1
R GI2
R EXT2 = R G2 + ------------N
Q2
RG2
RGI2
CGS
Q2
S
FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
Application Information
Layout Considerations
The parasitic inductances of the PCB and of the power
devices’ packaging (both upper and lower MOSFETs) can
cause serious ringing, exceeding absolute maximum rating
of the devices. Careful layout can help minimize such
unwanted stress. The following advice is meant to lead to an
optimized layout:
• Keep decoupling loops (PVCC-GND and BOOT-PHASE)
as short as possible.
• Minimize trace inductance, especially on low-impedance
lines. All power traces (UGATE, PHASE, LGATE, GND,
PVCC) should be short and wide, as much as possible.
• Minimize the inductance of the PHASE node. Ideally, the
source of the upper and the drain of the lower MOSFET
should be as close as thermally allowable.
• Minimize the current loop of the output and input power
trains. Short the source connection of the lower MOSFET
to ground as close to the transistor pin as feasible. Input
capacitors (especially ceramic decoupling) should be
placed as close to the drain of upper and source of lower
MOSFETs as possible.
In addition, for heat spreading, place copper underneath the
IC whether it has an exposed pad or not. The copper area
can be extended beyond the bottom area of the IC and/or
connected to buried power ground plane(s) with thermal
8
FN9282.1
December 3, 2007
ISL6594D
vias. This combination of vias for vertical heat escape,
extended copper plane, and buried planes for heat
spreading allows the IC to achieve its full thermal potential.
PVCC
VIN
BOOT
D
CBOOT
CGD
DU
DL
UGATE
RUGPH
Should the driver have insufficient bias voltage applied, its
outputs are floating. If the input bus is energized at a high
dV/dt rate while the driver outputs are floating, because of
self-coupling via the internal CGD of the MOSFET, the
UGATE could momentarily rise up to a level greater than the
threshold voltage of the MOSFET. This could potentially turn
on the upper switch and result in damaging inrush energy.
Therefore, if such a situation (when input bus powered up
before the bias of the controller and driver is ready) could
conceivably be encountered, it is a common practice to
place a resistor (RUGPH) across the gate and source of the
upper MOSFET to suppress the Miller coupling effect. The
value of the resistor depends mainly on the input voltage’s
rate of rise, the CGD/CGS ratio, as well as the gate-source
threshold of the upper MOSFET. A higher dV/dt, a lower
CDS/CGS ratio, and a lower gate-source threshold upper
FET will require a smaller resistor to diminish the effect of
the internal capacitive coupling. For most applications, a
5kΩ to 10kΩ resistor is typically sufficient, not affecting
normal performance and efficiency.
ISL6594D
Upper MOSFET Self Turn-On Effects at Start-up
G
CDS
RGI
CGS
QUPPER
S
PHASE
FIGURE 5. GATE TO SOURCE RESISTOR TO REDUCE
UPPER MOSFET MILLER COUPLING
The coupling effect can be roughly estimated using
Equation 5, which assume a fixed linear input ramp and
neglect the clamping effect of the body diode of the upper
drive and the bootstrap capacitor. Other parasitic
components such as lead inductances and PCB
capacitances are also not taken into account. These
equations are provided for guidance purpose only.
Therefore, the actual coupling effect should be examined
using a very high impedance (10MΩ or greater) probe to
ensure a safe design margin.
–V
DS
⎛
----------------------------------⎞
dV
⎜
-----⋅
R
⋅C ⎟
dV
iss⎟
V GS_MILLER = ------- ⋅ R ⋅ C rss ⎜ 1 – e dt
⎜
⎟
dt
⎜
⎟
⎝
⎠
R = R UGPH + R GI
C rss = C GD
9
(EQ. 5)
C iss = C GD + C GS
FN9282.1
December 3, 2007
ISL6594D
Dual Flat No-Lead Plastic Package (DFN)
2X
0.15 C A
D
A
L10.3x3
10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
MILLIMETERS
2X
0.15 C B
SYMBOL
MIN
6
INDEX
AREA
0.80
0.90
1.00
-
-
-
0.05
-
0.28
5,8
2.05
7,8
1.65
7,8
0.20 REF
0.18
D
1.95
E
0.10 C
0.08 C
SIDE VIEW
C
SEATING
PLANE
1
e
1.60
-
0.50 BSC
-
k
0.25
-
-
L
0.30
0.35
0.40
N
10
Nd
5
3
3. Nd refers to the number of terminals on D.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
E2/2
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
NX L
N-1
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
NX b
5
(Nd-1)Xe
REF.
8
2
2. N is the number of terminals.
E2
e
-
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
NX k
8
1.55
NOTES:
D2/2
2
N
-
Rev. 3 6/04
D2
(DATUM B)
2.00
8
7
6
INDEX
AREA
(DATUM A)
A3
-
3.00 BSC
E2
A
0.23
3.00 BSC
D2
B
NOTES
A
b
TOP VIEW
MAX
A1
A3
E
NOMINAL
0.10 M C A B
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
BOTTOM VIEW
C
L
0.415
NX (b)
(A1)
0.200
5
L
NX L
e
SECTION "C-C"
NX b
C
C C
TERMINAL TIP
FOR ODD TERMINAL/SIDE
10
FN9282.1
December 3, 2007
ISL6594D
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
N
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
H
0.25(0.010) M
B M
INCHES
E
SYMBOL
-B-
1
2
3
L
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
MIN
MAX
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.1890
0.1968
4.80
5.00
3
E
0.1497
0.1574
3.80
4.00
4
e
α
B S
0.050 BSC
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
N
α
NOTES:
MILLIMETERS
8
0°
8
8°
0°
7
8°
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
11
FN9282.1
December 3, 2007
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