DATASHEET

ISL6617
Features
The ISL6617 utilizes Intersil’s proprietary Phase Doubler
scheme to modulate two-phase power trains with single
PWM input. It doubles the number of phases that
Intersil’s multi-phase controllers ISL63xx can support.
When the enable pin (EN_PH_SYNC) is pulled low, the
PWM input is pulled high. This simplifies the phase
shedding implementation for some Intersil controllers
(VR10, VR11, VR11.1, and VR12 family) that can disable
the respective and higher phase(s) by pulling the
respective PWM line high.
• Proprietary Phase Doubler scheme with Phase
Shedding Function (Patent Pending)
• Enhanced Light to Full Load Efficiency
• Double or Quadruple Phase Count
• Patented Current Balancing with DCR Current
Sensing and Adjustable Gain
• Current Monitoring Output (IOUT) to Simplify
System Interface and Layout
• Triple-Level Enable Input for Mode Selection
• Dual PWM Output Drives for Two Synchronous
Rectified Bridges with Single PWM Input
• Channel Synchronization and Two Interleaving Options
• Tri-State PWM Input and Outputs for Output Stage
Shutdown
• Phase Enable Input and PWM Forced High Output to
Interface with Intersil’s Controller for Phase Shedding
• Overvoltage Protection
• Dual Flat No-Lead (DFN) Package
- Near Chip-Scale Package Footprint; Improves PCB
Utilization, Thinner Profile
- Pb-Free (RoHS Compliant)
The ISL6617 is designed to minimize the number of
analog signals that interface between the controller and
drivers in high phase count scalable applications. The
common COMP signal, which is usually seen in
conventional cascaded configuration, is not required; this
improves noise immunity and simplifies the layout.
Furthermore, the ISL6617 provides low part count and
low cost advantage over the conventional cascaded
technique.
By cascading the ISL6617 with another ISL6617 or
ISL6611A, it can quadruple the number of phases that
Intersil’s multi-phase controllers ISL63xx can support.
The ISL6617 also features Tri-State input and outputs
that recognize a high-impedance state, working together
with Intersil multiphase PWM controllers and driver
stages to prevent negative transients on the controlled
output voltage when operation is suspended. This feature
eliminates the need for the schottky diode that may be
utilized in a power system to protect the load from
excessive negative output voltage damage.
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
Applications
•
•
•
•
High Current Low Voltage DC/DC Converters
High Frequency and High Efficiency VRM and VRD
High Phase Count and Phase Shedding Applications
5V PWM Input Integrated Power Stage or DrMOS
Pin Configuration
ISL6617
(10 LD DFN)
TOP VIEW
February 4, 2010
FN7564.0
1
ISENA+
1
ISENA-
2
PWMIN
3
ISENB+
4
7 EN_PH_SYNC
ISENB-
5
6 PWMB
10 PWMA
11
GND
9 VCC
8 IOUT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2010. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL6617
PWM Doubler with Phase Shedding Function and
Output Monitoring Feature
ISL6617
Functional Pin Descriptions
PIN # PIN SYMBOL
FUNCTION
1
ISENA+
Output of the differential amplifier for Channel A. Connect a resistor on this pin to the negative rail of
the sensed voltage to set the current gain.
2
ISENA-
Input of the differential amplifier for Channel A. Typically, the positive rail of sensed voltage via DCR
sensing network connects to this node.
3
PWMIN
The PWM input signal triggers the J-K flip flop and alternates its input to channel A and B. Both channels
are effectively modulated. The PWM signal can enter three distinct states during operation, see
Operation section for further details. Connect this pin to the PWM output of the controller. The pin is
pulled to VCC when EN_PH_SYNC is low.
4
ISENB+
Output of the differential amplifier for Channel B. Connect a resistor on this pin to the negative rail of
the sensed voltage to set the current gain.
5
ISENB-
Input of the differential amplifier for Channel B. Typically, the positive rail of sensed voltage via DCR
sensing network connects to this node.
6
PWMB
PWM output of Channel B with Tri-state feature.
7
EN_PH_SYNC Driver Enable and Mode Selection Input. See Enable and Mode Operation for more details.
8
IOUT
Current monitoring Output. It sources out the average current of both Channel A and B.
9
VCC
Connect this pin to a +5V bias supply. It supplies power to internal analog circuits. Place a high quality
low ESR ceramic capacitor from this pin to GND.
10
PWMA
11
GND
PWM output of Channel A with Tri-state feature.
Bias and reference ground. All signals are referenced to this node. Place a high quality low ESR ceramic
capacitor from this pin to VCC. Connect this pad to the power ground plane (GND) via thermally
enhanced connection.
Block Diagram
VCC
55k
ISENA-
PWMIN
ISENA+
48k
CONTROL
LOGIC
EN_PH_SYNC
PWMA
PWMB
ISENB-
GND
CHANNEL A
CHANNEL B
ISENB+
IOUT
2
CURRENT
BALANCE BLOCK
FN7564.0
February 4, 2010
ISL6617
Typical Application (2 Phase Controller for 4 Phase Operation)
+5V
+12V
POWER STAGE
+5V
VIN
VCC
PWMA
FB
+5V
COMP
EN_PH_SYNC
PWM PHASE
GND
ISENAVSEN
PWM1
VCC
PWMIN
ISENB-
VR_RDY
ISL6617
ISEN1-
EN
IOUT
PWMB
ISEN1+
+VCORE
ISENA+
ISENB+
GND
+12V
POWER
STAGE
VIN
PWM PHASE
GND
VID
MAIN
CONTROL
ISL63XX
FS
+12V
POWER STAGE
+5V
EN_PH_SYNC2
VIN
VCC
PWMA
EN_PH_SYNC
PWM PHASE
GND
ISENA-
PWM2
PWMIN
ISENA+
ISENB+
ISENB-
ISL6617
ISEN2ISEN2+
IOUT
PWMB
GND
+12V
POWER
STAGE
VIN
PWM PHASE
GND
GND
3
FN7564.0
February 4, 2010
ISL6617
Typical Application II (2-Phase Controller to 8-Phase Operation)
+5V
+5V
VCC
PWMA
EN_PH_SYNC
+5V
+12V
POWER STAGE
VIN
PWM PHASE
GND
+5V
+5V
ISENA-
VCC
COMP
FB
ISENA+
PWMINISENB+
PWMA
ISENB-
EN_PH_SYNC
VSEN
ISL6617
ISENA-
VCC
IOUT
PWMB
GND
ISENA+
PWM1
PWMIN
+5V
VID
ISEN1-
VCC
PWMA
EN_PH_SYNC
IOUT
IOUT
ISENB-
ISEN1+
ISENB-
PWMIN
ISL6617
GND
PWMB
GND
+5V
+5V
VCC
PWMA
+5V
EN_PH_SYNC
EN_PH_SYNC2
ISENA+
PWMIN ISENB+
ISENB-
PWMA
EN_PH_SYNC
ISL6617
ISENA-
IOUT
ISENA+
PWMIN
+5V
ISL6617
ISEN2ISEN2+
PWMB
GND
ISENB-
PWMA
IOUT
PWMIN
ISENA+
ISENB+
ISENB-
ISL6617
PWMB
GND
4
PWM PHASE
GND
+12V
POWER STAGE
VIN
PWM PHASE
GND
+12V POWER
STAGE
VIN
PWM PHASE
GND
PWM PHASE
GND
ISENA-
GND
GND
+12V POWER
STAGE
VIN
VIN
VCC
ISENB+
PWMB
GND
+12V
POWER STAGE
+5V
EN_PH_SYNC
IOUT
PWM PHASE
ISENA-
VCC
PWM2
GND
ISENA+
ISENB+
PWMB
MAIN
CONTROL
ISL6336G
PWM PHASE
ISENA-
ISENB+
FS
+VCORE
+12V
POWER STAGE
VIN
+5V
ISL6617
+12V POWER
STAGE
VIN
+12V POWER
STAGE
VIN
PWM PHASE
GND
FN7564.0
February 4, 2010
ISL6617
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL6617CRZ
617C
0 to +70
10 Ld 3x3 DFN
L10.3x3
ISL6617IRZ
617I
-40 to +85
10 Ld 3x3 DFN
L10.3x3
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6617. For more information on MSL, please
see Technical Brief TB363.
5
FN7564.0
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ISL6617
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . -0.3V to 6.7V
Input Voltage (VENx, VPWMIN, ISENx) . . -0.3V to VCC + 0.3V
Ambient Temperature Range . . . . . . . . . . . -40°C to +125°C
ESD Rating
Human Body Model (JEDEC Class 2) . . . . . . . . . . . . . 2kV
Machine Model (JEDEC Class B). . . . . . . . . . . . . . . . 200V
Charged Device Model (JEDEC Class IV) . . . . . . . . . . . 2kV
Latch Up (JEDEC Class II) . . . . . . . . . . . . . . . . . . . . +85°C
Thermal Resistance (Typical)
θJA(°C/W) θJC(°C/W)
10 Ld DFN (Notes 4, 5) . . . . . . .
48
7
Maximum Junction Temperature . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature
ISL6617CRZ . . . . . . . . . .
ISL6617IRZ . . . . . . . . . . .
Maximum Operating Junction
Supply Voltage, VCC . . . . . .
..........
..........
Temperature.
..........
.
.
.
.
. . 0°C to +70°C
-40°C to +85°C
. . . . . +125°C
. . . . . 5V ±10%
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
features.
5. θJC, “case temperature” location is at the center of the package underside exposed pad. See Tech Brief TB379 for details.
Electrical Specifications
These specifications apply for recommended ambient temperature, unless otherwise noted.
Boldface limits apply over the operating temperature range.
PARAMETER
MIN
MAX
(Note 6) TYP (Note 6) UNITS
SYMBOL
TEST CONDITIONS
IVCC
PWM pin floating, VVCC = 5V, EN_PH = 5V
5
6.5
mA
PWM pin floating, VVCC = 5V, EN_PH = 0V
5
6.5
mA
FPWM = 600kHz, VVCC = 5V,
EN_PH_SYNC = 5V
6
7.5
mA
FPWM = 600kHz, VVCC = 5V,
EN_PH_SYNC = 4.25V
6
7.5
mA
FPWM = 300kHz, VVCC = 5V,
EN_PH_SYNC = 3.25V
6
7.5
mA
3.4
4.2
V
SUPPLY CURRENT
Bias Supply Current
POWER-ON RESET
POR Rising
POR Falling
2.3
Hysteresis
3.0
V
350
mV
EN_PH_SYNC INPUT
ENx Minimum LOW Threshold
VENx
ENx Maximum HIGH Threshold
VENx
2.0
V
Interleaving Mode 1 Window
VENx
97%
VCC
Interleaving Mode 2 Window
VENx
78%
85%
VCC
Synchronous Mode Window
VENx
54%
64%
VCC
0.8
V
SYNC AND INTERLEAVING MODE
Typical Threshold Hysteresis
-5%
Minimum SYNC Pulse
VCC
40
Maximum Synchronization Delay
Interleaving Mode Phase Shift
6
50
SYNC = 5V, PWM = 300kHz, 10% Width
ns
ns
180
°
FN7564.0
February 4, 2010
ISL6617
Electrical Specifications
These specifications apply for recommended ambient temperature, unless otherwise noted.
Boldface limits apply over the operating temperature range. (Continued)
PARAMETER
SYMBOL
Synchronization Mode Phase Shift
TEST CONDITIONS
MIN
MAX
(Note 6) TYP (Note 6) UNITS
SYNC = 0V, PWM = 300kHz, 10% Width
0
°
PWM INPUT (PWMIN)
Sinking Impedance
RPWM_SNK
55
kΩ
Source Impedance
RPWM_SRC
48
kΩ
Minimum Pull-Up Current
IPWM_SRC EN_PH_SYNC = LOW
40
mA
Tri-State Rising Threshold
VVCC = 5V (250mV Hysteresis)
0.95
1.20
1.45
V
Tri-State Falling Threshold
VVCC = 5V (300mV Hysteresis)
3.00
3.40
3.7
V
PWM Pulled High Threshold
EN_PH = LOW, Ramping PWM low
3.4
V
CURRENT SENSE (ISENA±, ISENB±, IOUT) AND PROTECTION (IOUT)
Sensed Current Tolerance
IOUT
Un-Tri State Trip For OVP
IOUT
ISENA = ISENB = 0µA
-6
0
6
µA
ISENA = ISENB = 20µA
14
20
26
µA
ISENA = ISENB = 50µA
43
50
57
µA
ISENA = ISENB = 100µA
90
100
110
µA
ENx = LOW TO HIGH, PWM = LOW
40
60
90
µA
PWM OUTPUT (PWMA AND PWMB)
Sourcing Impedance
RPWM_SRC VCC = 5V
45
100
200
Ω
Sink Impedance
RPWM_SNK VCC = 5V
45
100
125
Ω
1.65
2.00
2.6
V
Tri-State Level
VPWMA/B
VCC = 5V, EN_PH = LOW
SWITCHING TIME (See Figure 1 on Page 8)
PWMA/B Low to High Rise Time
tR1
Unloaded, 10% to 90%
4.5
ns
PWMA/B Tri-State to High Rise Time
tR2
Unloaded, 10% to 90%
4.5
ns
PWMA/B High to Low Fall Time
tF1
Unloaded, 90% to 10%
4.0
ns
PWMA/B High to Tri-State Fall Time
tF2
100% to 60% (3V), Assume Equavilent
Loading of RC = 50kΩ*10pF = 500ns
255
ns
PWMA/B Turn-On Propagation Delay
tPDH
Outputs Unloaded
35
ns
PWMA/B Turn-Off Propagation Delay
tPDL
Outputs Unloaded, excluding extension
35
ns
PWMA/B Extension
tEXT
ENx = VCC, IPWMA > IPWMB
70
ns
ENx = VCC, IPWMA < IPWMB
70
ns
ENx = 80%*VCC, IPWMA > IPWMB
190
ns
ENx = 80%*VCC, IPWMA < IPWMB
190
ns
Outputs Unloaded, excluding extension
10
ns
Including Propagation Delay
65
ns
Tri-State to High or Low Propagation
Delay
Tri-State Shutdown Holdoff Time
tPTS
tTSSHD
NOTE:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
7
FN7564.0
February 4, 2010
ISL6617
Timing Diagram
2.5V
PWMIN
tPDL
tPDH
15ns
tTSSHD
tTSSHD
tF2
tR1
PWMA/B
10%
90%
90%
tPTS
tR2
10%
60%
90%
tPTS
10%
tF1
FIGURE 1. TIMING DIAGRAM
Operation
Designed for high phase count and phase shedding
applications, the ISL6617 driverless phase doubler is
meant to double or quadruple (cascaded option using
two ISL6617s) the number of phases that Intersil’s
multi-phase controllers ISL63xx can support. Further, the
PWM line can be pulled high to disable the respective
phase and higher phase(s) when the enable pin
(EN_PH_SYNC) is pulled low. This simplifies the phase
shedding implementation for the controller that can
disable the respective and higher phase(s) by pulling the
respective PWM input high.
A rising transition on PWMIN initiates the turn-on of the
PWMA/B (see Figure 1). After a short propagation delay
[tPDH], the PWMA/B begins to rise. Typical rise times
[tR1] are provided in the “Electrical Specifications” table
on page 7.
A falling transition on PWMIN indicates the turn-off of
the PWMA/B. The PWMA/B begins to fall [tF1] after a
propagation delay [tPDL], which is modulated by the
current balance circuits.
When the PWMIN stays in the tri-state window for longer
than [tTSSHD], both PWMA/B will pull to ~2V so that the
cascaded 5V PWM input MOSFET driver or integrated
power stage can recognize tri-state.
EN_PH_SYNC Operation
The EN_PH_SYNC pin features multiple functions. It is
the enable input of the device and the input to select
various operational modes.
A. ENABLE OPERATION
As shown in Figure 2, the ISL6617 disables the doubler
operation when the EN_PH_SYNC pin is pulled to
ground, while the PWMIN pin is pulled to VCC. With the
PWM line pulled high, some Intersil controllers such as
VR10, VR11, VR11.1 and VR12 family can disable the
respective and higher phase(s). When the
EN_PH_SYNC returns high, the phase doubler will pull
the PWM line into tri-state window, and then will be
enabled only at the leading edge of PWM input. Prior to
the first PWMin rising edge, both the PWMA and PWMB
output will remain in tri-state unless an overvoltage
fault is detected. This fault is defined as when a phase
is detected to have more than 60% of the maximum
IOUT current. This provides additonal protection to the
load if the upper MOSFET experiences a short while the
doubler is enabled.
The EN_PH_SYNC pin should remain high if driving the
PWM line high is prohibited for the associated
controller. For proper system interface, please refer to
the device data sheets.
B. SYNCHRONOUS OPERATION
The ISL6617 can be set in interleaving mode or
synchronous mode by pulling the EN_PH_SYNC pin to the
respective level, shown in Table 1. A synchronous pulse
can be sent to the phase doubler during the load
application to improve the voltage droop and current
balance while still maintaining interleaving operation at DC
load conditions. However, excessive ringback can occur;
hence, the synchronous mode operation should be
carefully investigated. Figure 3 shows how to generate a
synchronous pulse when a transient load is applied. The
comparator should be a fast comparator with a minimum
delay.
49.9kΩ
EN_PH_SYNC
20kΩ
+
PWMIN
2kΩ
COMP
PWMA/B
FIGURE 2. TYPICAL ENABLE OPERATION TIMING
DIAGRAM
8
-
VCC
1kΩ
0Ω
SYNC
DNP
1.0nF
FIGURE 3. TYPICAL SYNC PULSE GENERATOR
FN7564.0
February 4, 2010
ISL6617
C. VARIOUS OPERATIONAL MODES
The ISL6617 has three distinct operating modes
depending upon the voltage level of the EN_PH_SYNC
pin. To ensure that the ISL6617 is in operation, the pin
must be above 2V. When the EN_PH_SYNC pin is set to
above 97% of VCC, the ISL6617 will operate in
interleaving mode with a maximum extension of 70ns.
When VCC is between 78% and 85% of VCC, the ISL6617
operates in interleaving mode with a fixed extension of
120ns and a variable extension of up to 70ns. This
results in a minimum extension of 120ns and a max of
190ns. To enter this 2nd interleaving mode, the pin must
remain in the 78% to 85% range for at least 4 cycles.
Between 54% and 64% of VCC, the device operates in
synchronous mode. Figures 4 and 5 show simplified
synchronous and interleaving modes’ operational
waveforms, respectively.
TABLE 1. ISL6617 OPERATIONAL MODES
MODE
MIN
TYP
MAX
Enable Low
Enable High
Not Used
54%*VCC 60%*VCC 64%*VCC
PWMB
FIGURE 4. INTERLEAVING MODE’S OPERATIONAL
WAVEFORMS (ENx = VCC, OR 81%*VCC)
PWMA
0ns to 70ns
Interleaving#2 78%*VCC 81%*VCC 85%*VCC 120ns + (0ns
to 70ns)
Synchronous
PWMA
PWM
2V
VCC
PWM
EXTENSION
0.8V
Interleaving#1 97%*VCC
To transition between two different modes, the
EN_PH_SYNC pin voltage level needs to be set
accordingly. Figures 6 and 7 show an example of external
circuits for mode transition between synchronous mode
and interleaving #1 or #2 mode, respectively. The R
should be less than 50kΩ to improve transition time.
PWMB
FIGURE 5. SYNCHRONOUS MODE’S OPERATIONAL
WAVEFORMS (EN_PH_SYNC = 60%*VCC)
0ns to 70ns
From 0.8V to 2V or 54% of VCC is not
recommended Region.
VCC
ISL6617
INTERLEAVING
0ns TO 70ns
40%*R
EN_PH_ SYNC
+
-
60%*R
4 CYCLES
BLANKING
INTERLEAVING
+120+(0ns TO 70ns)
+
SYNC
-
SYNC
0ns TO 70ns
+
+
TTL
EN_PH
-
FIGURE 6. CONFIGURATION FOR TRANSITION BETWEEN SYNCHRONOUS AND INTERLEAVING #1 MODES
9
FN7564.0
February 4, 2010
ISL6617
ISL6617
VCC
INTERLEAVING
0ns TO 70ns
19%*R
EN_PH_ SYNC
+
4 CYCLES
BLANKING
-
28.5%*R
INTERLEAVING
+120+(0ns TO 70ns)
+
52.5%*R
SYNC
SYNC
0ns TO 70ns
+
+
TTL
EN_PH
-
FIGURE 7. CONFIGURATION FOR TRANSITION BETWEEN SYNCHRONOUS AND INTERLEAVING #2 MODES
PWMA PWM1A
VCC
EN_X
ISENA
PWMIN
PWM1B
IOUT
PWMB
POWER
STAGE
PWMA
ISENB
ISENA
PHASE1B
PWMIN
IOUT
VOUT
PWMB
PWMB
PWMA
ISENB
PWM1C
POWER
STAGE
TO CONTROLLER
PHASE1A
PWMA
ISL6617
PWM1
POWER
STAGE
ISL6617/ISL6611A
PHASE1C
ISENA
PWMIN
VCC
EN_X
PWMB
PWM1D
POWER
STAGE
IOUT
ISENB
PHASE1D
ISL6617/ISL6611A
FIGURE 8. CASCADED PHASE DOUBLER SIMPLIFIED DIAGRAM
The ISL6617 can further be cascaded with itself or
ISL6611A (phase doubler with integrated 5V drivers), as
shown in Figure 8. This can quadruple the number of
phase each PWM line can support. Figure 9 shows the
operational waveforms of the cascaded doublers. The
PWMIN pin will be pulled to VCC when the doubler is
disabled (EN_x = Low). To avoid driving the PWM outputs
of the 1st stage ISL6617 by the 2nd stage’s PWMIN, the
2nd stage doubler’s enable input should remain high, i.e,
tied to VCC, as shown in Figure 8.
To operate each phase at the switching frequency of FSW,
the operational frequency of the controller needs to be
scaled accordingly for different modes, as shown in
Table 2.
10
TABLE 2. CONTROLLER FREQUENCY AND MAXIMUM
DUTY CYCLE
ISL6617
DMAX
MAXIMUM
DUTY CYCLE
WITH
OPERATIONAL
MODES
FCONTROLLER PER PHASE ISL6336G
Interleaving
2 x FSW
50%
45%
Synchronous
FSW
100%
90%
Cascaded
Interleaving
4 x Fsw
25%
22.5%
FN7564.0
February 4, 2010
ISL6617
The internal circuitry, shown in Figures 10 and 11,
represents one channel. This circuitry is repeated for
each channel in the doubler. The input bias current of the
current sensing amplifier is typically 60nA; less than 5kΩ
input impedance is preferred to minimize the offset error.
In addition, the common mode input voltage to the
amplifier should be less than VCC-3V.
A. INDUCTOR DCR SENSING
An inductor’s winding is characteristic of a distributed
resistance, as measured by the DCR (Direct Current
Resistance) parameter. Consider the inductor DCR as a
separate lumped quantity, as shown in Figure 10.
VIN
I (s)
L
L
POWER
STAGE
DCR
VL
+
R
PWMA/B
DOUBLER #1
PWMA
PWM1A
DOUBLER #2
PWM1B
PWMB
PWM1C
PWM1D
ISL6617
RISEN(A/B)
IA/B
CURRENT
SENSE
+
ISEN-(A/B)
-
ISEN+(A/B)
CT
FIGURE 10. DCR SENSING CONFIGURATION
To properly compensate the system that uses phase
doublers, the effective system sawtooth to calculate the
modulator gain should factor in the duty cycle limitation
(DMAX) as Equation 1. For instance, when using
ISL6336G and ISL6617s in cascaded interleaving mode,
the effective sawtooth amplitude should be scaled as
3V/22.5% = 13.33V.
(EQ. 1)
Current Sensing
The ISL6617 senses current continuously for fast
response. The ISL6617 supports inductor DCR sensing,
or resistive sensing techniques. The associated channel
current sense amplifier uses the ISEN inputs to
reproduce a signal proportional to the inductor current,
IL. The sensed current, ISEN, is proportional to the
inductor current. The sensed current is used for current
balance and load-line regulation.
11
C
DCR
I SEN = I ----------------LR
ISEN
FIGURE 9. CASCADED DOUBLER OPERATIONAL
WAVEFORMS
V RAMP
V RAMP_EFFECTIVE = -------------------D MAX
COUT
-
+
INDUCTOR
VC(s)
PWM1
VOUT
-
When the doubler operates in interleaving mode, the
PWM controller frequency should be set at two times the
desired phase frequency (FSW). Since the input PWM
pulse is divided into half to feed into each phase of the
doubler, the operational duty cycle of each phase should
be less than 50%. In synchronous mode, the PWM
controller should be operated at the same frequency as
the desired phase frequency. In this mode, the allowable
duty cycle is up to 100%. For cascaded interleaving, the
controller switching frequency needs to be set at four
times the phase frequency. During cascaded operation,
the maximum allowable duty cycle will be less than 25%.
All of the maximum allowable duty cycle numbers
referenced assume that the PWM controller can send out
a 100% duty cycle pulse. In many cases, this is not
achievable because the controller needs time to reset it's
internal sawtooth ramp or internal max duty limit.
However, the fixed 120ns extension of interleaving mode
2 helps recover the typical 1% duty cycle loss associated
with the ramp reset time. In addition, Intersil has
developed a dedicated controller, the ISL6336G with
90% duty cycle, to work with the ISL6617 for high-phase
count and overclocking applications.
The channel current IL, flowing through the inductor, will
also pass through the DCR. Equation 2 shows the sdomain equivalent voltage across the inductor VL.
V L ( s ) = I L ⋅ ( s ⋅ L + DCR )
(EQ. 2)
A simple R-C network across the inductor extracts the
DCR voltage, as shown in Figure 10.
The voltage on the capacitor VC, can be shown to be
proportional to the channel current IL. See Equation 3.
L
⎛ s ⋅ ------------+ 1⎞ ⋅ ( DCR ⋅ I L )
⎝ DCR
⎠
V C ( s ) = --------------------------------------------------------------------( s ⋅ RC + 1 )
(EQ. 3)
If the R-C network components are selected such that
the RC time constant matches the inductor time constant
(RC = L/DCR), the voltage across the capacitor VC is
equal to the voltage drop across the DCR, i.e.,
proportional to the channel current.
With the internal low-offset current amplifier, the
capacitor voltage VC is replicated across the sense
FN7564.0
February 4, 2010
ISL6617
resistor RISEN. Therefore, the current out of ISEN+ pin,
ISEN, is proportional to the inductor current.
current balance, the power loss is equally dissipated over
multiple devices and a greater area.
Because of the internal filter at ISEN- pin, one capacitor,
CT, is needed to match the time delay between the ISENand ISEN+ signals. Select the proper CT to keep the time
constant of RISEN and CT (RISEN x CT) close to 27ns.
The resulting average current IAVG also goes out from
the IOUT pin for current monitoring and can also be fed
back to the controller’s ISEN lines for current balance,
load-line regulation, and overcurrent protection. For fast
response to the current information, the IOUT pin should
have minimum decoupling; no more than 50ns filter is
recommended. The full scale of IOUT is 100µA; it
typically should set resistor gain around 50µA to 80µA at
the full load to ensure that it will not hit the full scale
prior to the overcurrent trip point. At the same time, the
current signal accuracy is maximized.
Equation 4 shows that the ratio of the channel current to
the sensed current, ISEN, is driven by the value of the
sense resistor and the DCR of the inductor.
DCR
I SEN = I L ⋅ -----------------R ISEN
(EQ. 4)
B. RESISTIVE SENSING
For more accurate current sensing, a dedicated resistor
RSENSE in series with each output inductor can serve as
the current sense element (see Figure 11). This
technique reduces overall converter efficiency due to the
additional power loss on the current sense element
RSENSE.
L
IL
RSENSE VOUT
COUT
ISL6617
RISEN(A/B)
IA/B
SENSE
ISEN-(A/B)
-
ISEN+(A/B)
CT
R
SENSE
I SEN = I ------------------------L R
ISEN
FIGURE 11. SENSE RESISTOR IN SERIES WITH
INDUCTORS
The same capacitor CT is needed to match the time
delay between ISEN- and ISEN+ signals. Select the
proper CT to keep the time constant of RISEN and CT
(RISEN x CT) close to 27ns.
Equation 5 shows the ratio of the channel current to the
sensed current ISEN.
R SENSE
I SEN = I L ⋅ ----------------------R
(EQ. 5)
ISEN
Current Balance and Current Monitoring
The sensed currents IA and IB from each respective
channel are summed together and divided by 2. The
resulting average current IAVG provides a measure of the
total load current. Channel current balance is achieved
by comparing the sensed current of each channel to the
average current to make an appropriate adjustment to
the PWMA and PWMB duty cycle with Intersil’s patented
current-balance method.
Channel current balance is essential in achieving the
thermal advantage of multiphase operation. With good
12
At heavy load condition, efficiency can be improved by
spreading the load across many phases. This is primarily
because the resistive loss becomes the dominant
component of total loss budget at high current levels.
Since the load is carried by more phases, each power
device handles less current. In addition, the devices are
likely to be spread over a larger area on the Printed
Circuit Board (PCB). Both these factors result in
improved heat dissipation for higher phase count
systems. By reducing the system’s operating
temperature, components reliability is improved.
Furthermore, increasing the phase count also reduces
the size of ripple on both the input and output currents.
It reduces EMI and improves the efficiency. Figures 12
and 13 show the ripple values for a 24-Phase voltage
regulator with the following parameters:
CURRENT
+
Benefits of a High Phase Count System
• Input voltage: 12V
• Output voltage: 1.6V
• Duty cycle: 13.3%
• Load current: 200A
• Output Phase Inductor: 500nH
• Phase switching frequency: 200kHz
In this example, the 24-phase voltage regulator (VR) can
run in 6-phase, 8-phase, 12-phase, 24-phase
interleaving mode. In 6-phase interleaving mode, every
4 phases runs synchronously, which yields 18.73A and
12.93A input and output ripple currents, respectively.
The 24-phase interleaving regulator significantly drops
these values to 4.05A and 0.78A, respectively. As shown
in Table 3, both input and output ripple currents are
reduced when more phases are running in interleaving
mode. Note that the 8-phase VR has lower output ripple
current than the 12-phase VR since the 8-phase VR has
better output ripple cancellation factor close to the duty
cycle of 1/8.
TABLE 3. RIPPLE CURRENT (UNIT: A)
INTERLEAVED PHASES
6
8
12
24
Input Ripple Current
18.73
11.64
8.79
4.05
Output Ripple Current
12.93
2.70
4.83
0.78
FN7564.0
February 4, 2010
ISL6617
Figure 14 shows the efficiency of a 12-phase VR design,
which runs the doubler in interleaving and synchronous
modes. For comparison, a 6-phase VR with the same
number of MOSFETs and inductors is also plotted, clearly
demonstrating the efficiency improvement of a high-phase
count system and interleaving mode over synchronous
mode resulting from the better ripple cancellation.
20
20
OUTPUT CURRENT RIPPLE (A)
INPUT RIPPLE CURRENT (A)
15
15
24 CHANNELS, 8 INTERLEAVING
10
10
24 CHANNELS, 12 INTERLEAVING
24 INTERLEAVING PHASES
55
00 0
80
24 CHANNELS, 6 INTERLEAVING
10
20
30
40
50
24 CHANNELS, 6 INTERLEAVING
60
24 CHANNELS, 8 INTERLEAVING
24 CHANNELS, 12 INTERLEAVING
40
24 INTERLEAVING PHASES
20
0
0
10
DUTY CYCLE (%)
FIGURE 12. INPUT CURRENT RIPPLE VS DUTY CYCLE,
PHASE COUNT
20
30
DUTY CYCLE (%)
40
50
FIGURE 13. OUTPUT CURRENT RIPPLE VS DUTY CYCLE,
PHASE COUNT
93
92
EFFICIENCY (%)
91
90
PHASE DOUBLER IN
INTERLEAVING MODE
89
PHASE DOUBLER IN
SYNCHRONOUS MODE
88
6-PHASE, SAME AMOUNT
OF MOSFETS AND INDUCTORS
87
86
85
0
20
40
60
80 100 120 140 160 180
LOAD (A)
FIGURE 14. EFFICIENCY COMPARISON IN 12-PHASE DESIGN
13
FN7564.0
February 4, 2010
ISL6617
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
2/4/10
FN7564.0
CHANGE
Initial release.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
handheld products, and notebooks. Intersil's product families address power management and analog signal
processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: ISL6617
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
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14
FN7564.0
February 4, 2010
ISL6617
Package Outline Drawing
L10.3x3
10 LEAD DUAL FLAT PACKAGE (DFN)
Rev 6, 09/09
3.00
6
PIN #1 INDEX AREA
A
B
1
6
PIN 1
INDEX AREA
(4X)
3.00
2.00
8x 0.50
2
10 x 0.23
4
0.10
1.60
TOP VIEW
10x 0.35
BOTTOM VIEW
4
(4X)
0.10 M C A B
0.415
PACKAGE
OUTLINE
0.200
0.23
0.35
(10 x 0.55)
SEE DETAIL "X"
(10x 0.23)
1.00
MAX
0.10 C
BASE PLANE
2.00
0.20
C
SEATING PLANE
0.08 C
SIDE VIEW
(8x 0.50)
C
0.20 REF
5
1.60
0.05
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Lead width applies to the metallized terminal and is measured
between 0.18mm and 0.30mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
15
FN7564.0
February 4, 2010
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