DATASHEET

DATASHEET
PWM Doubler with Output Monitoring Feature
ISL6617A
Features
The ISL6617A utilizes Intersil’s proprietary Phase Doubler
scheme to modulate two-phase power trains with single PWM
input. It doubles the number of phases that 3.3V multiphase
controllers can support.
• Proprietary phase doubler scheme
The ISL6617A is designed to minimize the number of analog
signals that interface between the controller and drivers in high
phase count scalable applications. The common COMP signal,
which is usually seen in conventional cascaded configurations, is
not required; this improves noise immunity and simplifies the
layout. Furthermore, the ISL6617A provides low part count and
low cost advantage over the conventional cascaded technique.
By cascading the ISL6617A with another ISL6617 or ISL6611A, it
can quadruple the number of phases that 3.3V multiphase
controllers can support.
The ISL6617A also features tri-state input and outputs that
recognize a high-impedance state, working together with Intersil
multiphase PWM controllers and driver stages to prevent
negative transients on the controlled output voltage when
operation is suspended. This feature eliminates the need for the
Schottky diode that may be utilized in a power system to protect
the load from excessive negative output voltage damage.
Applications
• Enhanced light to full load efficiency
• Double or quadruple phase count
• Patented current balancing with DCR current sensing and
adjustable gain
• Current monitoring output (IOUT) to simplify system interface
and layout
• Triple-level enable input for mode selection
• Dual PWM output drives for two synchronous rectified bridges
with single PWM input
• Channel synchronization and two interleaving options
• Support 3.3V PWM input
• Support 5V PWM output
• Tri-state PWM input and outputs for output stage shutdown
• Overvoltage protection
• Dual flat no-lead (DFN) package
- Near chip-scale package footprint; improves PCB utilization,
thinner profile
- Pb-free (RoHS compliant)
Related Literature
• High current low voltage DC/DC converters
• High frequency and high efficiency VRM and VRD
• TB363, “Guidelines for Handling and Processing Moisture
Sensitive Surface Mount Devices (SMDs)”
• High phase count and phase shedding applications
• 3.3V PWM input integrated power stage or DrMOS
Phase Doubler Selection Guide
PART
NUMBER
PWM
INPUT
PWM
OUTPUT
INTEGRATED
DRIVER
ISL6617
5.0V
5.0V
N/A
5.0V PWM DrMOS;
ISL6617, ISL6611A
ISL6336G, ISL6372/3/4/5/6, ISL6364/67/67H;
ISL6388/98 with 5V PWM Option
ISL6617A
3.3V
5.0V
N/A
5.0V PWM DrMOS;
ISL6617, ISL6611A
3.3V PWM Digital Controllers with Phase Doubler Compatibility;
ISL6388/98 with 3.3V PWM Option
ISL6611A
5V
N/A
5.0V
Discrete MOSFET;
Dual FETS
ISL6336G, ISL6372/3/4/5/6, ISL6364/67/67H;
ISL6388/98 with 5V PWM Option
December 19, 2014
FN7844.0
1
CASCADED DEVICES
COMPATIBLE CONTROLLERS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2014. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL6617A
Internal Block Diagram
VCC
10k
CSENA
PWMIN
5.5k
CSRTNA
CHANNEL A
PWMA
CONTROL
LOGIC
PWMB
EN_SYNC
CSENB
GND
CHANNEL B
CSRTNB
CURRENT
BALANCE BLOCK
IOUT
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
ISL6617AFRZ
PART
MARKING
17AF
TEMP. RANGE
(°C)
-40 to +125
PACKAGE
(RoHS Compliant)
10 Ld 3x3 DFN
PKG.
DWG. #
L10.3x3
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For information on MSL please see techbrief TB363.
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ISL6617A
Pin Configuration
ISL6617A
(10 LD DFN)
TOP VIEW
CSRTNA
1
CSENA
2
PWMIN
3
CSRTNB
CSENB
10 PWMA
9
VCC
8
IOUT
4
7
EN_SYNC
5
6
PWMB
11
GND
Functional Pin Descriptions
PIN #
PIN SYMBOL
FUNCTION
1
CSRTNA
Output of the differential amplifier for Channel A. Connect a resistor on this pin to the negative rail of the sensed voltage to
set the current gain.
2
CSENA
Input of the differential amplifier for Channel A. Typically, the positive rail of sensed voltage via DCR sensing network
connects to this node.
3
PWMIN
The PWM input signal (3.3V) triggers the J-K flip flop and alternates its input to Channel A and B. Both channels are
effectively modulated. The PWM signal can enter three distinct states during operation; see “Operation” on page 8 for
further details. Connect this pin to the PWM output of the controller.
4
CSRTNB
Output of the differential amplifier for Channel B. Connect a resistor on this pin to the negative rail of the sensed voltage to
set the current gain.
5
CSENB
Input of the differential amplifier for Channel B. Typically, the positive rail of sensed voltage via DCR sensing network
connects to this node.
6
PWMB
PWM output of Channel B with 5V PWM tri-state compatibility.
7
EN_SYNC
8
IOUT
Current monitoring Output. It sources out the average current of both Channel A and B.
9
VCC
Connect this pin to a +5V bias supply. It supplies power to internal analog circuits. Place a high quality low ESR ceramic
capacitor from this pin to GND.
10
PWMA
11
GND
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Driver Enable and Mode Selection Input. See “EN_SYNC Operation” on page 8 for more details.
PWM output of Channel A with 5V PWM tri-state compatibility.
Bias and reference ground. All signals are referenced to this node. Place a high quality low ESR ceramic capacitor from this
pin to VCC. Connect this pad to the power ground plane (GND) via thermally enhanced connection.
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ISL6617A
Typical Application (2-Phase Controller for 4-Phase Operation)
+5V
+12V
POWER STAGE
+5V
VIN
VCC
PWMA
EN_SYNC
PWM
PHASE
GND
+3.3V
CSENA
PWM0
VCC
PWMIN
CSENB
VR_RDY
+VCORE
CSRTNA
CSRTNB
VSEN
+12V
ISL6617A
CS0
EN
PWMB
GND
PWM
PHASE
GND
+12V
POWER STAGE
+5V
MAIN
CONTROL
ISL69xxx
VIN
IOUT
CSRTN0
POWER
STAGE
+5V
VIN
VCC
PWMA
EN_SYNC
PHASE
PWM
GND
CSENA
PWM1
PWMIN
CSRTNA
CSRTNB
CSENB
ISL6617A
CS1
IOUT
PWMB
CSRTN1
GND
+12V
POWER
STAGE
VIN
PWM
PHASE
GND
GND
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ISL6617A
Typical Application II (2-Phase Controller to 8-Phase Operation)
+12V
+5V
+5V
VCC
PWMA
EN_SYNC
+5V
POWER STAGE
VIN
PWM
PHASE
GND
+5V
ISENA-
VCC
+3.3V
ISENA+
ISENB+
PWMIN
PWMA
ISENB-
EN_SYNC
VSEN
CSENA
VCC
IOUT
PWMB
GND
CSRTNA
PWMIN
PWM0
VCC
PWMA
EN_SYNC
IOUT
CS0
CSRTN0
ISENB-
PWMIN
GND
ISL6617
PWMB
GND
PWMA
+5V
PWMA
ISENA+
ISENB+
ISENB-
PWMIN
EN_SYNC
ISL6617
CSENA
IOUT
PWMB
CSRTNA
GND
PWMIN
PWMA
EN_SYNC
IOUT
GND
5
PWM PHASE
GND
POWER STAGE
PWM PHASE
GND
PWMIN
ISENA+
ISENB+
ISENB-
ISL6617
PWMB
GND
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+12V POWER
STAGE
VIN
ISENA-
CSRTNB
GND
PWM PHASE
VIN
VCC
ISL6617A
PWMB
POWER STAGE
+12V
+5V
+5V
CSENB
GND
ISENA-
VCC
CSRTN1
PWM PHASE
GND
EN_SYNC
+5V
+12V POWER
STAGE
VIN
VIN
VCC
IOUT
PWM PHASE
+12V
+5V
+5V
CS1
GND
ISENA+
ISENB+
PWMB
PWM1
PWM PHASE
ISENA-
CSRTNB
MAIN
CONTROL
ISL69xxx
+VCORE
GND
IOUT
CSENB
VIN
+12V
POWER STAGE
VIN
+5V
+5V
ISL6617A
POWER
STAGE
+12V
ISL6617
+12V POWER
STAGE
VIN
PWM
PHASE
GND
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ISL6617A
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.7V
Input Voltage (VENx, VPWMIN, ISENx). . . . . . . . . . . . . . . -0.3V to VCC + 0.3V
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
ESD Rating
Human Body Model (JEDEC Class 2) . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV
Machine Model (JEDEC Class B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V
Charged Device Model (JEDEC Class IV) . . . . . . . . . . . . . . . . . . . . . . . 2kV
Latch-up (JEDEC Class II) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+85°C
Thermal Resistance (Typical)
JA(°C/W)
JC(°C/W)
10 Ld DFN (Notes 4, 5) . . . . . . . . . . . . . .
48
7
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . . +125°C
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V 10%
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. JC, “case temperature” location is at the center of the package underside exposed pad.
Electrical Specifications These specifications apply for recommended ambient temperature, unless otherwise noted. Boldface limits
apply over the operating temperature range.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6) UNITS
SUPPLY CURRENT
Bias Supply Current
IVCC
PWM pin floating, VVCC = 5V, EN_SYNC = 5V
5
6.5
mA
PWM pin floating, VVCC = 5V, EN_SYNC = 0V
5
6.5
mA
FPWM = 600kHz, VVCC = 5V, EN_SYNC = 5V
6
7.5
mA
FPWM = 600kHz, VVCC = 5V, EN_SYNC = 4.25V
6
7.5
mA
FPWM = 300kHz, VVCC = 5V, EN_SYNC = 3.25V
6
7.5
mA
3.4
4.2
V
POWER-ON RESET
POR Rising
POR Falling
2.3
Hysteresis
3.0
V
350
mV
EN_SYNC INPUT
0.8
V
ENx Minimum LOW Threshold
VENx
ENx Maximum HIGH Threshold
VENx
2.0
V
Interleaving Mode 1 Window
VENx
97%
VCC
Interleaving Mode 2 Window
VENx
78%
85%
VCC
Synchronous Mode Window
VENx
54%
64%
VCC
SYNC AND INTERLEAVING MODE
Typical Threshold Hysteresis
-5%
Minimum SYNC Pulse
VCC
40
Maximum Synchronization Delay
50
ns
ns
Interleaving Mode Phase Shift
SYNC = 5V, PWM = 300kHz, 10% Width
180
°
Synchronization Mode Phase Shift
SYNC = 0V, PWM = 300kHz, 10% Width
0
°
PWM INPUT (PWMIN)
Sinking Impedance
RPWM_SNK
5.5
kΩ
Source Impedance
RPWM_SRC
10
kΩ
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ISL6617A
Electrical Specifications These specifications apply for recommended ambient temperature, unless otherwise noted. Boldface limits
apply over the operating temperature range. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
Tri-State to PWM High Rising Threshold
VVCC = 5V
Tri-State to PWM High Falling Threshold
VVCC = 5V
Tri-State to PWM Low Rising Threshold
VVCC = 5V
Tri-State to PWM Low Falling Threshold
VVCC = 5V
MIN
(Note 6)
TYP
2.50
2.00
MAX
(Note 6) UNITS
2.70
2.25
0.95
V
V
1.15
V
0.50
0.75
V
CSENA = CSENB = 0µA
-6
0
6
µA
CSENA = CSENB = 20µA
14
20
26
µA
CSENA = CSENB = 50µA
43
50
57
µA
CSENA = CSENB = 100µA
90
100
110
µA
ENx = LOW TO HIGH, PWM = LOW
40
60
90
µA
CURRENT SENSE (CSENA, CSENB, IOUT) AND PROTECTION (IOUT)
Sensed Current Tolerance
IOUT
Un-Tri State Trip for OVP
IOUT
PWM OUTPUT (PWMA AND PWMB)
Sourcing Impedance
RPWM_SRC
VCC = 5V, PWMIN = HIGH
30
100
200
Ω
Sink Impedance
RPWM_SNK
VCC = 5V, PWMIN = LOW
30
100
150
Ω
VPWMA/B
VCC = 5V, PWMIN = HIGH, 2.5mA Load
4.5
PWM Output Low Level
VPWMA/B
VCC = 5V, PWMIN = LOW, 2.5mA Load
PWM Tri-State Level
VPWMA/B
VCC = 5V, EN_PH = LOW, 0.5mA Load
PWM Output High Level
1.65
V
2.00
0.4
V
2.6
V
SWITCHING TIME (See Figure 1 on page 8)
PWMA/B Low to High Rise Time
tR1
Unloaded, 10% to 90%
4.5
ns
PWMA/B Tri-State to High Rise Time
tR2
Unloaded, 10% to 90%
4.5
ns
PWMA/B High to Low Fall Time
tF1
Unloaded, 90% to 10%
4.0
ns
PWMA/B High to Tri-state Fall Time
tF2
100% to 60% (3V), Assume Equivalent Loading of
RC = 50kΩ*10pF = 500ns
255
ns
PWMA/B Turn-on Propagation Delay
tPDH
Outputs Unloaded
35
ns
PWMA/B Turn-off Propagation Delay
tPDL
Outputs Unloaded, excluding extension
35
ns
PWMA/B Extension
tEXT
ENx = VCC, IPWMA > IPWMB
70
ns
ENx = VCC, IPWMA < IPWMB
70
ns
ENx = 80%*VCC, IPWMA > IPWMB
190
ns
Tri-State to High or Low Propagation Delay
Tri-State Shutdown Hold-off Time
tPTS
tTSSHD
ENx = 80%*VCC, IPWMA < IPWMB
190
ns
Outputs Unloaded, excluding extension
10
ns
Including Propagation Delay
65
ns
NOTE:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
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ISL6617A
Timing Diagram
3.3V
1.7V
PWMIN
tPDL
tPDH
15ns
tTSSHD
tTSSHD
tR1
PWMA/B
10%
5V
tPTS
tF2
90%
90%
tR2
10%
60%
90%
tPTS
10%
tF1
FIGURE 1. TIMING DIAGRAM
Operation
Designed for high phase count and phase shedding applications,
the ISL6617A driverless phase doubler is meant to double or
quadruple (cascaded with two ISL6617s) the number of phases
that 3.3V multiphase controllers can support.
A rising transition on PWMIN initiates the turn-on of the PWMA/B
(see Figure 1). After a short propagation delay [tPDH], the
PWMA/B begins to rise. Typical rise times [tR1] are provided in
the “Electrical Specifications” table on page 7.
A falling transition on PWMIN indicates the turn-off of the
PWMA/B. The PWMA/B begins to fall [tF1] after a propagation
delay [tPDL], which is modulated by the current balance circuits.
When the PWMIN stays in the tri-state window for longer than
[tTSSHD], both PWMA/B will pull to 40% of VCC so that the
cascaded 5V PWM input MOSFET driver or integrated power
stage can recognize tri-state.
maximum IOUT current. This provides additional protection to the
load if the upper MOSFET experiences a short while the doubler
is enabled.
The EN_SYNC pin should remain high if driving the PWM line high
is prohibited for the associated controller. For proper system
interface, please refer to the respective device datasheet.
SYNCHRONOUS OPERATION
The ISL6617A can be set in interleaving mode or synchronous
mode by pulling the EN_SYNC pin to the respective level, as
shown in Table 1. A synchronous pulse can be sent to the phase
doubler during the load application to improve the voltage droop
and current balance while still maintaining interleaving operation
at DC load conditions. However, excessive ringback can occur;
hence, the synchronous mode operation should be carefully
investigated. Figure 3 shows how to generate a synchronous
pulse when a transient load is applied. The comparator should be
a fast comparator with a minimum delay.
VCC
EN_SYNC Operation
49.9kΩ
ENABLE OPERATION
1kΩ
20kΩ
The EN_SYNC pin features multiple functions. It is the enable
input of the device and the input to select various operational
modes.
+
-
2kΩ
COMP
0Ω
SYNC
DNP
1.0nF
FIGURE 3. TYPICAL SYNC PULSE GENERATOR
EN_SYNC
VARIOUS OPERATIONAL MODES
PWMIN
PWMA/B
FIGURE 2. TYPICAL ENABLE OPERATION TIMING DIAGRAM
As shown in Figure 2, the ISL6617A disables the doubler
operation when the EN_SYNC pin is pulled to ground. When the
EN_SYNC returns high, the phase doubler will pull the PWM line
into the tri-state window, and then will be enabled only at the
leading edge of the PWM input. Prior to the first PWMIN rising
edge, both the PWMA and PWMB output will remain in tri-state
unless an overvoltage fault is detected. This fault is defined as
when a phase is detected to have more than 60% of the
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The ISL6617A has three distinct operating modes depending
upon the voltage level of the EN_SYNC pin. To ensure that the
ISL6617A is in operation, the pin must be above 2V. When the
EN_SYNC pin is set to above 97% of VCC, the ISL6617A will
operate in interleaving mode with a maximum extension of 70ns.
When VCC is between 78% and 85% of VCC, the ISL6617A
operates in interleaving mode with a fixed extension of 120ns
and a variable extension of up to 70ns. This results in a minimum
extension of 120ns and a max of 190ns. To enter this 2nd
interleaving mode, the pin must remain in the 78% to 85% range
for at least 4 cycles. Between 54% and 64% of VCC, the device
operates in synchronous mode. Figures 4 and 5 show simplified
synchronous and interleaving modes’ operational waveforms,
respectively.
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ISL6617A
TABLE 1. ISL6617A OPERATIONAL MODES
MODE
MIN
TYP
Enable Low
Enable High
Interleaving#1
MAX
PWM
EXTENSION
0.8V
PWMA
2V
97%*VCC
VCC
0ns to 70ns
PWMB
Interleaving#2 78%*VCC 81%*VCC 85%*VCC 120ns + (0ns to 70ns)
Synchronous
Not Used
54%*VCC 60%*VCC 64%*VCC
FIGURE 4. INTERLEAVING MODE’S OPERATIONAL WAVEFORMS
(ENx = VCC, OR 81%*VCC)
0ns to 70ns
From 0.8V to 2V or 54% of VCC is not recommended Region
To transition between two different modes, the EN_SYNC pin
voltage level needs to be set accordingly. Figures 6 and 7 show
an example of external circuits for mode transition between
synchronous mode and interleaving #1 or #2 mode, respectively.
The R should be less than 50kΩ to improve transition time.
PWM
PWMA
PWMB
FIGURE 5. SYNCHRONOUS MODE’S OPERATIONAL WAVEFORMS
(EN_SYNC = 60%*VCC)
VCC
ISL6617A
INTERLEAVING
0ns TO 70ns
40%*R
EN_SYNC
+
60%*R
4 CYCLES
BLANKING
-
INTERLEAVING
+120+(0ns TO 70ns)
+
SYNC
SYNC
0ns TO 70ns
+
+
TTL
EN
-
FIGURE 6. CONFIGURATION FOR TRANSITION BETWEEN SYNCHRONOUS AND INTERLEAVING #1 MODES
ISL6617A
VCC
INTERLEAVING
0ns TO 70ns
19%*R
EN_SYNC
+
4 CYCLES
BLANKING
-
28.5%*R
INTERLEAVING
+120+(0ns TO 70ns)
+
52.5%*R
SYNC
-
SYNC
0ns TO 70ns
+
+
TTL
-
EN
FIGURE 7. CONFIGURATION FOR TRANSITION BETWEEN SYNCHRONOUS AND INTERLEAVING #2 MODES
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ISL6617A
PWMA PWM1A
VCC
EN_X
ISENA
PWMIN
PWM1B
IOUT
PWMB
ISENB
CSENA
PHASE1B
POWER
STAGE
PWMA
PWMIN
IOUT
VOUT
PWMB
PWMB
PWMA
CSENB
PWM1C
POWER
STAGE
TO CONTROLLER
PHASE1A
PWMA
ISL6617A
PWM1
POWER
STAGE
ISL6617/ISL6611A
PHASE1C
ISENA
PWMIN
VCC
EN_X
PWMB
PWM1D
POWER
STAGE
IOUT
ISENB
PHASE1D
ISL6617/ISL6611A
FIGURE 8. CASCADED PHASE DOUBLER SIMPLIFIED DIAGRAM
TABLE 2. CONTROLLER FREQUENCY AND MAXIMUM DUTY CYCLE
OPERATIONAL MODES FCONTROLLER
PWM1A
PWM1B
PWMB
PWM1C
2 x fSW
50%
Synchronous
fSW
100%
Cascaded Interleaving
4 x fSW
25%
When the doubler operates in interleaving mode, the PWM
controller frequency should be set at two times the desired
phase frequency (fSW). Since the input PWM pulse is divided into
half to feed into each phase of the doubler, the operational duty
cycle of each phase should be less than 50%. In synchronous
mode, the PWM controller should be operated at the same
frequency as the desired phase frequency. In this mode, the
allowable duty cycle is up to 100%. For cascaded interleaving,
the controller switching frequency needs to be set at four times
the phase frequency. During cascaded operation, the maximum
10
PWMA
ISL6617A MAXIMUM DUTY CYCLE
PER PHASE
Interleaving
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PWM1
PWM1D
DOUBLER #1
To operate each phase at the switching frequency of fSW, the
operational frequency of the controller needs to be scaled
accordingly for different modes, as shown in Table 2.
allowable duty cycle will be less than 25%. All of the maximum
allowable duty cycle numbers referenced assume that the PWM
controller can send out a 100% duty cycle pulse. In many cases,
this is not achievable because the controller needs time to reset
its internal sawtooth ramp or internal max duty limit. However,
the fixed 120ns extension of interleaving mode 2 helps recover
the typical 1% duty cycle loss associated with the ramp reset
time.
DOUBLER #2
The ISL6617A can further be cascaded with ISL6617 or
ISL6611A (phase doubler with integrated 5V drivers), as shown in
Figure 8. This can quadruple the number of phases each PWM
line can support. Figure 9 shows the operational waveforms of
the cascaded doublers. The PWMIN pin of ISL6617 or ISL6611A
will be pulled to VCC when it is disabled (EN_x = Low). To avoid
driving the PWM outputs of the 1st stage ISL6617A by the 2nd
stage’s PWMIN, the 2nd stage doubler’s enable input should
remain high, i.e, tied to VCC, as shown in Figure 8. Note that
ISL6617A cannot cascade with itself and its PWMIN will not be
pulled to VCC when EN_x is disabled (Low).
FIGURE 9. CASCADED DOUBLER OPERATIONAL WAVEFORMS
To properly compensate the system that uses phase doublers,
the effective system sawtooth to calculate the modulator gain
should factor in the duty cycle limitation (DMAX) as Equation 1.
For instance, when using ISL6617A and ISL6617 in cascaded
interleaving mode, the effective sawtooth amplitude should be
scaled as 3V/22.5% = 13.33V.
V RAMP
V RAMP_EFFECTIVE = -----------------D MAX
(EQ. 1)
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ISL6617A
Current Sensing
The ISL6617A senses current continuously for fast response. The
ISL6617A supports inductor DCR sensing, or resistive sensing
techniques. The associated channel current sense amplifier uses
the ISEN inputs to reproduce a signal proportional to the inductor
current, IL. The sensed current, ISEN, is proportional to the
inductor current. The sensed current is used for current balance
and load-line regulation.
The internal circuitry (shown in Figures 10 and 11) represents
one channel. This circuitry is repeated for each channel in the
doubler. The input bias current of the current sensing amplifier is
typically 60nA; less than 5kΩ input impedance is preferred to
minimize the offset error. In addition, the common mode input
voltage to the amplifier should be less than VCC-3V.
INDUCTOR DCR SENSING
An inductor’s winding is characteristic of a distributed resistance,
as measured by the DCR (Direct Current Resistance) parameter.
Consider the inductor DCR as a separate lumped quantity, as
shown in Figure 10.
VIN
POWER
STAGE
DCR
VOUT
+
R
-
VC(s)
PWMA/B
COUT
-
+
INDUCTOR
VL
L
 s  ----------- + 1   DCR  I L 
 DCR

V C  s  = ---------------------------------------------------------------- s  RC + 1 
(EQ. 3)
If the R-C network components are selected such that the RC
time constant matches the inductor time constant (RC = L/DCR),
the voltage across the capacitor VC is equal to the voltage drop
across the DCR, i.e., proportional to the channel current.
With the internal low-offset current amplifier, the capacitor
voltage VC is replicated across the sense resistor RISEN.
Therefore, the current out of ISEN+ pin, ISEN, is proportional to
the inductor current.
Because of the internal filter at ISEN- pin, one capacitor, CT, is
needed to match the time delay between the ISEN- and ISEN+
signals. Select the proper CT to keep the time constant of RISEN
and CT (RISEN x CT) close to 27ns.
Equation 4 shows that the ratio of the channel current to the
sensed current, ISEN, is driven by the value of the sense resistor
and the DCR of the inductor.
DCR
I SEN = I L  --------------R ISEN
IL  s 
L
The voltage on the capacitor VC, can be shown to be proportional
to the channel current IL. See Equation 3.
C
(EQ. 4)
RESISTIVE SENSING
For more accurate current sensing, a dedicated resistor RSENSE in
series with each output inductor can serve as the current sense
element (see Figure 11). This technique reduces overall converter
efficiency due to the additional power loss on the current sense
element RSENSE.
L
IL
RSENSE VOUT
ISL6617A
COUT
RISEN(A/B)
ISL6617A
IA/B
RISEN(A/B)
IA/B
CURRENT
SENSE
CURRENT
+
CSEN(A/B)
SENSE
-
CSRTN(A/B)
+
CT
CSEN(A/B)
-
CSRT(A/B)
DCR
I SEN = I --------------LR
ISEN
FIGURE 10. DCR SENSING CONFIGURATION
The channel current IL, flowing through the inductor, will also
pass through the DCR. Equation 2 shows the s-domain
equivalent voltage across the inductor VL.
(EQ. 2)
V L  s  = I L   s  L + DCR 
CT
R SENSE
I SEN = I ------------------------L R
ISEN
A simple R-C network across the inductor extracts the DCR
voltage, as shown in Figure 10.
FIGURE 11. SENSE RESISTOR IN SERIES WITH INDUCTORS
The same capacitor CT is needed to match the time delay between
ISEN- and ISEN+ signals. Select the proper CT to keep the time
constant of RISEN and CT (RISEN x CT) close to 27ns.
Equation 5 shows the ratio of the channel current to the sensed
current ISEN.
R SENSE
I SEN = I L  -------------------R
(EQ. 5)
ISEN
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ISL6617A
Current Balance and Current Monitoring
The sensed currents IA and IB from each respective channel are
summed together and divided by 2. The resulting average current
IAVG provides a measure of the total load current. Channel
current balance is achieved by comparing the sensed current of
each channel to the average current to make an appropriate
adjustment to the PWMA and PWMB duty cycle with Intersil’s
patented current-balance method.
Channel current balance is essential in achieving the thermal
advantage of multiphase operation. With good current balance,
the power loss is equally dissipated over multiple devices and a
greater area.
The resulting average current IAVG also goes out from the IOUT
pin for current monitoring and can also be fed back to the
controller’s ISEN lines for current balance, load-line regulation,
and overcurrent protection. For fast response to the current
information, the IOUT pin should have minimum decoupling; no
more than 50ns filter is recommended. The full scale of IOUT is
100µA; it typically should set resistor gain around 50µA to 80µA
at the full load to ensure that it will not hit the full scale prior to
the overcurrent trip point. At the same time, the current signal
accuracy is maximized.
Benefits of a High Phase Count System
At heavy load condition, efficiency can be improved by spreading
the load across many phases. This is primarily because the
resistive loss becomes the dominant component of total loss
budget at high current levels.
Since the load is carried by more phases, each power device
handles less current. In addition, the devices are likely to be
spread over a larger area on the Printed Circuit Board (PCB). Both
these factors result in improved heat dissipation for higher phase
count systems. By reducing the system’s operating temperature,
the reliability of the components is improved.
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Furthermore, increasing the phase count also reduces the size of
ripple on both the input and output currents. It reduces EMI and
improves the efficiency. Figures 12 and 13 show the ripple
values for a 24-phase voltage regulator with the following
parameters:
• Input voltage: 12V
• Output voltage: 1.6V
• Duty cycle: 13.3%
• Load current: 200A
• Output Phase Inductor: 500nH
• Phase switching frequency: 200kHz
In this example, the 24-phase voltage regulator (VR) can run in
6-phase, 8-phase, 12-phase or 24-phase interleaving mode. In
6-phase interleaving mode, every 4 phases runs synchronously,
which yields 18.73A and 12.93A input and output ripple
currents, respectively. The 24-phase interleaving regulator
significantly drops these values to 4.05A and 0.78A, respectively.
As shown in Table 3, both input and output ripple currents are
reduced when more phases are running in interleaving mode.
Note that the 8-phase VR has lower output ripple current than the
12-phase VR since the 8-phase VR has better output ripple
cancellation factor close to the duty cycle of 1/8.
TABLE 3. RIPPLE CURRENT (UNIT: A)
INTERLEAVED PHASES
6
8
12
24
Input Ripple Current
18.73
11.64
8.79
4.05
Output Ripple Current
12.93
2.70
4.83
0.78
Figure 14 shows the efficiency of a 12-phase VR design, which
runs the doubler in interleaving and synchronous modes. For
comparison, a 6-phase VR with the same number of MOSFETs
and inductors is also plotted, clearly demonstrating the efficiency
improvement of a high-phase count system and interleaving
mode over synchronous mode resulting from the better ripple
cancellation.
FN7844.0
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ISL6617A
80
24 CHANNELS, 6 INTERLEAVING
15
15
OUTPUT CURRENT RIPPLE (A)
INPUT RIPPLE CURRENT (A)
20
20
24 CHANNELS, 8 INTERLEAVING
10
10
24 CHANNELS, 12 INTERLEAVING
24 INTERLEAVING PHASES
55
00 0
24 CHANNELS, 6 INTERLEAVING
60
24 CHANNELS, 8 INTERLEAVING
24 CHANNELS, 12 INTERLEAVING
40
24 INTERLEAVING PHASES
20
0
10
20
30
40
50
0
10
DUTY CYCLE (%)
20
30
40
50
DUTY CYCLE (%)
FIGURE 12. INPUT CURRENT RIPPLE vs DUTY CYCLE, PHASE COUNT
FIGURE 13. OUTPUT CURRENT RIPPLE vs DUTY CYCLE, PHASE
COUNT
93
92
EFFICIENCY (%)
91
90
PHASE DOUBLER IN
INTERLEAVING MODE
89
PHASE DOUBLER IN
SYNCHRONOUS MODE
88
6-PHASE, SAME AMOUNT
OF MOSFETS AND INDUCTORS
87
86
85
0
20
40
60
80 100
LOAD (A)
120
140
160
180
FIGURE 14. EFFICIENCY COMPARISON IN 12-PHASE DESIGN
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ISL6617A
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
DATE
REVISION
December 19, 2014
FN7844.0
CHANGE
Initial Release
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
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ISL6617A
Package Outline Drawing
L10.3x3
10 LEAD DUAL FLAT PACKAGE (DFN)
Rev 10, 7/14
3.00
5
PIN #1 INDEX AREA
A
B
1
5
PIN 1
INDEX AREA
(4X)
3.00
2.00
8x 0.50
2
10 x 0.23
0.10
1.60
TOP VIEW
10x 0.35
BOTTOM VIEW
(4X)
0.10 M C A B
0.415
0.200
0.23
0.35
(10 x 0.55)
SEE DETAIL "X"
(10x 0.23)
1.00
MAX
0.10 C
0.20
2.00
(8x 0.50)
BASE PLANE
C
SEATING PLANE
0.08 C
SIDE VIEW
0.415
C
1.60
0.20 REF
4
0.05
2.85 TYP
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Tiebar shown (if present) is a non-functional feature.
5.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
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