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ACEMENT
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DATASHEET
2.5MHz Integrated Power Management IC with I2C
Compatible Interface
ISL80083
Features
ISL80083 is an integrated mini Power Management IC
(mini-PMIC) for powering low-voltage microprocessor, or
applications using a single Li-Ion or Li-Polymer cell battery to
power multiple voltage rails. ISL80083 integrates a
high-efficiency 2.5MHz synchronous step-down converter, a
low-input low-dropout linear regulator, 33MHz oscillator, level
shift, and input supply select.
• 800mA synchronous step-down converter and 300mA,
general-purpose LDO
The 2.5MHz PWM switching frequency allows for the use of
very small external inductors and capacitors. The step-down
converter can enter skip mode under light load conditions to
further improve the efficiency and maximize the battery life.
For noise sensitive applications, it can also be programmed
through I2C interface to operate in forced PWM mode,
regardless of the load current condition. The I2C interface
supports on-the-fly control of the output voltage from 0.625V
to 2.225V at 25mV/step size for dynamic power saving. The
step-down converter can supply up to 800mA load current.
ISL80083 also provides a 300mA low dropout (LDO) regulator.
The input voltage range is from 2.6V to 5.5V allowing it to be
powered from one of the on-chip step-down converters or directly
from the battery. The default LDO output comes with factory
pre-set fixed output voltage options between 0.9V to 3.6V.
• LDO output voltage I2C programmability
- At 50mV/step. . . . . . . . . . . . . . . . . . . . . . . . . . . 0.9V to 3.6V
• 400kb/s I2C-bus series interface transfers the control data
between the host controller and the ISL80083
• Fixed SMPS output voltage I2C programmability
- At 25mV/step. . . . . . . . . . . . . . . . . . . . . . 0.625V to 2.225V
• 33MHz oscillator
• Level shift from 1.8V to 3V with enable
• Input select
• Switcher I2C programmable skip mode under light load or
forced fixed switching frequency PWM mode
Applications
• Power cable
ISL80083 is available in a 2.11mm x 2.13mm 25 Ball CSP
package.
100
EFFICIENCY (%)
90
1V - PFM
80
70
60
50
40
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
OUTPUT LOAD (A)
FIGURE 1. EFFICIENCY vs LOAD (3.3VIN, TA = +25°C)
May 15, 2013
FN7886.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL80083
Pin Configuration
ISL80083
(25 BALL CSP 2.11 x 2.13mm)
TOP VIEW
1
2
3
4
5
A
-OSCOUT
+OSCOUT
OSCGND
CLK2P3IN
CLK2P3OUT
CFG2
LSRX
UART_EN
RESET
V3CLAMP
CFG2_CR
LSRX_CR
VOLDO
GNDLDO
GND
VIN_REMOTE
OSC_EN
SCLK
SDAT
1VAUX
VIN_HOST
VSELECT
PHASE
PGND
FB
B
C
D
E
Pin Descriptions
PIN NUMBER
PIN NAME
A1
-OSCOUT
Negative terminal of the precision 33MHz oscillator differential output.
A2
+OSCOUT
Positive terminal of the precision 33MHz oscillator differential output.
A3
OSCGND
Isolated ground for the internal 33MHz oscillator.
A4
CLK2P3IN
A5
CLK2P3OUT
B1
CFG2
This is the output of the level shifter from the CFG2_CR rail control signal shifting from 1.8V to 3V.
B2
LSRX
This is the output of the level shifter from the LSRX_CR rail control signal shifting from 1.8V to 3V.
B3
UART_EN
B4
RESET
B5
V3CLAMP
This rail is a 3V LDO sourcing from VSELECT.
C1
CFG2_CR
This is the input to the level shifter for the CONFIG2 rail control signal shifting from 3V to 1.8V.
C2
LSRX_CR
This is the input to the level shifter from the LSRX rail control signal.
C3
VOLDO
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DESCRIPTION
2.3V input for the 33MHz oscillator. Connect a 220nF capacitor from CLK2P3OUT to OSCGND.
2.3V internal LDO output for the 33MHz oscillator. Connect CLK2P3IN to CLK2P3OUT along with a 220nF capacitor
for low noise performance.
Level shift of LSRX logic enable control. The output LSRX is in high Z state when UART_EN is pulled low. There is a
125k pull-down resistor from this pin to GND.
This is a totem pole output to indicate a fault mode. The output is low if any of the fault is detected. The output is high
during normal operation.
Output of the LDO.
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ISL80083
Pin Descriptions (Continued)
PIN NUMBER
PIN NAME
DESCRIPTION
C4
GNDLDO
C5
GND
D1
VIN_REMOTE
Input voltage secondary for cases where VIN_HOST is valid, VIN_REMOTE is held off IC. If there is 2.6V present and VIN host
is not valid, then the pass MOSFET turns on. If this voltage is greater than 4.5V, then its pass MOSFET turn off.
D2
OSC_EN
Oscillator control pin. Connect to logic high will allow all outputs to operate normally and SMPS in PWM. Connecting
to logic low will disable the 33MHz oscillator, 1VAUX, and allow the SMPS to operate in high light load efficiency PFM.
There is a 125k pull-up resistor from this pin to 1.8V.
D3
SCLK
I2C interface clock pin.
D4
SDAT
I2C interface data pin.
D5
1VAUX
E1
VIN_HOST
Input voltage primary for the IC. If there is 2.6V present, then the pass MOSFET turns on. If this voltage is greater than 4.5V,
then its pass MOSFET turn off.
E2
VSELECT
Input voltage for buck converter switcher, V3CLAMP, LDO, and it also serves as the power supply pin for the whole internal
digital/analog circuits.
E3
PHASE
Switching node for DC to DC converter; connect to one terminal of the inductor.
E4
PGND
Power ground for switcher.
E5
FB
Power ground for LDO.
System ground for analog and digital circuitry.
This rail is a low impedance pass PFET switch sourcing from switcher’s output thru the VFB pin.
Feedback pin for switcher; connect external voltage divider resistors between switcher output, this pin and ground. For
fixed output versions, connect this pin directly to the switcher output.
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
FB
(V)
SLV
LDO
(V)
TEMP. RANGE
(°C)
PACKAGE
Tape & Reel
(Pb-free)
PKG.
DWG. #
ISL80083IIZ-T
80083
Adj
3.3
-40 to +85
25 Ball WLCSP
W5x5.25B
ISL80083IIZ-TK
80083
Adj
3.3
-40 to +85
25 Ball WLCSP
W5x5.25B
ISL80083IIZ-TS
80083
Adj
3.3
-40 to +85
25 Ball WLCSP
W5x5.25B
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free WLCSP and BGA packaged products employ special Pb-free material sets; molding compounds/die attach materials and
SnAgCu - e1 solder ball terminals, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free
WLCSP and BGA packaged products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL80083. For more information on MSL please see Tech Brief TB363.
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May 15, 2013
ISL80083
VIN HOST
VIN REMOTE
Block Diagram
HOST
REMOTE
SELECTOR
LOGIC
2.5V TO 4.5V
PASS RANGE
PREFER “HOST”
INPUT
Q1
Q2
VSELECT
C1
10µF
V3CLAMP
5k
5k
SDAT
C2
1µF
Q4
I2C
SSTIME
BUCK
VOUT
LDO VOUT
PWM/PFM
SCLK
V3CLAMP
15mA
Q3
3V
CLAMP
OUT
FAULT
VIN UV
OVP/
UVP
OCP
OTP
LDO OV
LDO UV
LDO
BUCK
CONTROL
Q5
LDOGND
LDO
GND
CFG2
PGND
LSRX_CR
LSRX
UART_EN
C4
10µF
FB
Q7
1V AUX
125k
LEVEL
SHIFT
3V TO 1.8V
(LSRX
HI-Z OUT
DISABLE)
1.0V
L1
1µH
Q6
1V AUX
CFG2_CR
C3
1µF
PHASE
1.8V
RESET
1.8V
VOLDO
500mA
OSC_EN
CONTROL
C5
10µF
CLK2P3IN
OSC
33MHz
AGND
OSC
LDO
OSCGND
CLK2P3OUT
OSCGND
-OSCOUT
+OSCOUT
AGND
125k 
C6
220nF
TABLE 1. TYPICAL APPLICATION PART LIST
PARTS
L1
DESCRIPTION
MANUFACTURER
PART NUMBER
SPECIFICATIONS
SIZE
Inductor
TDK
VSF302512T-1R0
1.0µH/1.8A/33mΩ
3.0mmx2.5mmx1.2mm
C1, C4,
C5
Input and output
capacitor
Murata
GRM21BR60J106KE19L
10µF/6.3V
0402
C2, C3
Output capacitor
Murata
GRM185R60J105KE26D
1µF/6.3V
0201
Bias Capacitor
Various
GRM185R60J224KE26D
220nF/6.3V
0201
C6
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FN7886.1
May 15, 2013
ISL80083
Absolute Maximum Ratings (Refer to ground)
Thermal Information
VIN_HOST, VIN_REMOTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3V (DC) to 22V (DC)
VSELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3V (DC) to 6.5V (DC) or 7V (20ms)
PHASE. . . . . . . . . . . . . . . . . . . . .-1.5V (100ns)/-0.3V (DC) to 6.5V (DC) or 7V (20ms)
V3PCLAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
AGND, OSCGND, PGND, GNDLDO . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
1VAUX, CFG2, CFG2_CR, LSRX, LSRX_CR . . . . . . . . . . . . . . . -0.3V to 3.6V
RESET, SDAT, SCLK, UART_EN, VOLDO . . . . . . . . . . . . . . . . . . -0.3V to 3.6V
All other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.9V
ESD Ratings
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 2kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 200V
Charged Device Model (Tested per JESD22-C101D) . . . . . . . . . . . . . 1kV
Latch Up (Tested per JESD78B, Class II, Level A) . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
CSP Package (Notes 4, 5) . . . . . . . . . . . . . .
70
0.9
Maximum Junction Temperature Range . . . . . . . . . . . . . .-40°C to +150°C
Recommended Junction Temperature Range . . . . . . . . . . 0°C to +125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-40°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
VIN_HOST, VIN_REMOTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 20V
SMPS Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 800mA
LDO Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0mA to 300mA
Operating Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . 0°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. For JC, the “case temp” location is taken at the package top center.
Electrical Specifications
Unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and
the typical specifications are measured at the following conditions: TA = +25°C, VIN_HOST or VIN_REMOTE = 3.3V. For LDO, VSELECT = VOLDO + 0.5V to
5.5V, L1 = 1.0µH, C1 = C4 = C5 = 10µF, C2 = C3 = C6 = 1µF, IOUT = 0A for SMPS and LDO (see Figure 1 for more details). Boldface limits apply across
the operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
TEST CONDITIONS
VIN_HOST or VIN_REMOTE Voltage
Range
VSELECT Undervoltage Lockout
Threshold
TYP
2.7
VUVLO
Quiescent Supply Current on VSELECT
MIN
(Note 6)
IVSELECT
MAX
(Note 6)
UNIT
20
V
Rising, IOUT = 0A for both SMPS and LDO
2.40
2.56
2.62
V
Falling
2.30
2.46
2.57
V
150
500
µA
All outputs no loading
Thermal Shutdown
155
°C
Thermal Shutdown Hysteresis
30
°C
INPUT SELECTOR
VIN_HOST P-Channel MOSFET
ON-resistance
Q1
VSELECT = 3.3V, IO = 200mA
0.20
Ω
VIN_REMOTE P-Channel MOSFET ONresistance
Q2
VSELECT = 3.3V, IO = 200mA
0.20
Ω
Minimum Pass Range Voltage
VIN_MIN
2.2
2.7
V
Maximum Pass Range Voltage
VIN_Max
4.5
5.52
V
1.000
1.050
V
SMPS
Output Start Up Voltage
VSELECT = 3.3V, PWM
0.950
Line Regulation
VSELECT = VO + 0.5V to 5.5V (minimal 2.5V)
0.1
%/V
P-Channel MOSFET ON-resistance
Q5
VSELECT = 3.3V, IO = 200mA
0.14
0.18
Ω
N-Channel MOSFET ON-resistance
Q6
VSELECT = 3.3V, IO = 200mA
0.05
0.08
Ω
P-Channel MOSFET Peak Current Limit
IPK
1.4
1.7
A
PWM Switching Frequency
fS
SW Minimum ON-time
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5
1
fOSC/13
2.5
MHz
VFB = 2V
70
ns
FN7886.1
May 15, 2013
ISL80083
Electrical Specifications
Unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and
the typical specifications are measured at the following conditions: TA = +25°C, VIN_HOST or VIN_REMOTE = 3.3V. For LDO, VSELECT = VOLDO + 0.5V to
5.5V, L1 = 1.0µH, C1 = C4 = C5 = 10µF, C2 = C3 = C6 = 1µF, IOUT = 0A for SMPS and LDO (see Figure 1 for more details). Boldface limits apply across
the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
SS Time
VOUT Rise Time
Soft-Discharge Resistor
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
1
ms
Resistor from PHASE to PGND
115
Ω
IO = 200mA
0.07
Ω
Sleep Mode From OSC_EN < 0.45V
1.5
ms
1VAUX
P-Channel MOSFET ON-resistance
Q7
Shutdown Delay Time
LDOs
Internal Peak Current Limit
200
425
540
mA
VOLDO Output Start-Up Voltage
VSELECT = 3.3V
1.71
1.80
1.89
V
V3CLAMP Output Voltage
I3P3V = 15mA, VSELECT = 3.3V
2.7
3.0
3.3
V
VOLDO Power Supply Rejection Ratio
IO = 300mA @ 1kHz, VSELECT = 3.3V, VO = 2.6V,
TA = +25°C
55
dB
VOLDO Output Voltage Noise
VSELECT = 3.3V, IO = 10mA, TA = +25°C, BW = 10Hz to
100kHz
45
µVRMS
LEVEL SHFT
CFG2_CR Logic High Input
1.4
V
CFG2_CR Logic Low Input
0.4
LSRX_CR Logic High Input
UART_EN > 1.2V
LSRX_CR Logic Low Input
UART_EN > 1.2V
CFG2 Logic High Output
CFG2_CR > 1.2V, 3.3k Pull-down
CFG2 Logic Low Output
CFG2_CR < 0.4V, 3.3k Pull-down
LSRX Logic High Output
UART_EN > 1.2V, LSRX_CR > 1.2V, 1M Pull-down
LSRX Logic Low Output
UART_EN > 1.2V, LSRX_CR < 0.4V, 1Mk Pull-down
CFG2 Low-to-High Prop Delay
CFG2_CR > 1.2V
50
ns
CFG2 High-to-Low Prop Delay
CFG2_CR < 0.4V
50
ns
LSRX Low-to-High Prop Delay
UART_EN > 1.2V, LSRX_CR > 1.2V
50
ns
LSRX High-to-Low Prop Delay
UART_EN > 1.2V, LSRX_CR < 0.4V
50
ns
UART_EN < 0.6V
10
MΩ
LSRX Output Impedance
High Z
1.4
V
V
2.8
2.4
0.4
V
3.3
V
0.4
V
3.2
V
0.4
V
OSCILLATOR
CLK2P3OUT Voltage
I2P2V = 15mA, VSELECT = 2.8V to 5.5V
2.25
700
Output Voltage
VOH
Single-ended (+OSCOUT or -OSCOUT)
Output Voltage
VOL
Single-ended (+OSCOUT or -OSCOUT)
2.30
2.35
V
mV
100
mV
Frequency
Measured from +OSCOUT to -OSCOUT, VSELECT = 3.3V
33.00
MHz
Jitter
Measured from +OSCOUT to -OSCOUT, VSELECT = 3.3V
6
ps
RMS/
Cycle
CLK_OSC Disable Time - Sleep Mode
Delay from OSC_EN < 0.45V
1
ms
CLK_OSC Start Time From Sleep
From CLK_EN > 1.2V
100
µs
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ISL80083
I2C Interface Timing Specifications
SYMBOL
For SCL and SDA pins, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6) UNITS
Cpin
Pin Capacitance
15
pF
fSCL
SCL Frequency
400
kHz
tsp
Pulse Width Suppression Time at SDA
and SCL Inputs
Any pulse narrower than the max spec is
suppressed
50
ns
tAA
SCL Falling Edge to SDA Output Data
Valid
SCL falling edge crossing VIL, until SDA exits the
VIL to VIH window
900
ns
tBUF
Time the Bus Must be Free Before the
Start of a New Transmission
SDA crossing VIH during a STOP condition, to SDA
crossing VIH during the following START
condition
1300
ns
tLOW
Clock LOW Time
Measured at the VIL crossings
1300
ns
tHIGH
Clock HIGH Time
Measured at the VIH crossings
600
ns
tSU:STA
START Condition Set-up Time
SCL rising edge to SDA falling edge; both
crossing VIH
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge crossing VIL to SCL falling
edge crossing VIH
600
ns
tSU:DAT
Input Data Set-up Time
From SDA exiting the VIL to VIH window, to SCL
rising edge crossing VIL
100
ns
tHD:DAT
Input Data Hold Time
From SCL rising edge crossing VIH to SDA
entering the VIL to VIH window
0
ns
tSU:STO
STOP Condition Set-up Time
From SCL rising edge crossing VIH, to SDA rising
edge crossing VIL
600
ns
tHD:STO
STOP Condition Hold Time for Read, or
Volatile Only Write
From SDA rising edge to SCL falling edge; both
crossing VIH
1300
ns
tDH
Output Data Hold Time
From SCL falling edge crossing VIL, until SDA
enters the VIL to VIH window
0
ns
tR
SDA and SCL Rise Time
From VIL to VIH
20 + 0.1 x Cb
250
ns
tF
SDA and SCL Fall Time
From VIH to VIL
20 + 0.1 x Cb
250
ns
Cb
Capacitive Loading of SDA or SCL
Total on-chip and off-chip
10
400
pF
Rpu
SDA and SCL Bus Pull-up Resistor
Off-Chip
Maximum is determined by tR and tF
For Cb = 400pF, max is about 2k~2.5k
For Cb = 40pF, max is about 15k~20k
1
k
NOTE:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
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May 15, 2013
ISL80083
Typical
Performance Curves and Waveforms
.
300
100
EFFICIENCY (%)
90
POWER DISSIPATION (mW)
1V - PFM
80
70
1V - PWM
60
50
40
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
250
200
1V - PWM
150
100
50
1V - PFM
0
0.0
1.0
0.1
0.2
0.3
1.030
1.815
1.020
1.810
1V - PWM
1.000
0.990
1V - PFM
0.980
0.970
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.5
0.6
0.7
0.8
0.9
1.0
FIGURE 3. POWER DISSIPATION vs LOAD (3.3V IN , TA = +25°C)
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
FIGURE 2. EFFICIENCY vs LOAD (3.3VIN , TA = +25°C)
1.010
0.4
OUTPUT LOAD (A)
OUTPUT LOAD (A)
0.7
0.8
0.9
1.0
1.805
1.8V LDO
1.800
1.795
1.790
1.785
0
30
60
90
120
150
180
210
240
270
300
OUTPUT LOAD (A)
OUTPUT LOAD (A)
FIGURE 4. VOUT REGULATION vs LOAD (3.3V IN , TA = +25°C)
FIGURE 5. VOUT REGULATION vs LOAD (3.3V IN , TA = +25°C)
VIN HOST 5V/DIV
SMPS 1V/DIV
VIN HOST 5V/DIV
SMPS 1V/DIV
VIN REMOTE 1V/DIV
VIN REMOTE 1V/DIV
VLDO 2V/DIV
VLDO 2V/DIV
RESET B 2V/DIV
RESET B 2V/DIV
1ms/DIV
FIGURE 6. START-UP WITH VIN HOST = 3.3V AT NO LOAD (PFM)
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8
1ms/DIV
FIGURE 7. START-UP WITH VIN HOST = 3.3V AT NO LOAD (PWM)
FN7886.1
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ISL80083
Typical Performance Curves and Waveforms (Continued)
VIN HOST 5V/DIV
VIN HOST 5V/DIV
SMPS 1V/DIV
SMPS 1V/DIV
VIN REMOTE 1V/DIV
VIN REMOTE 1V/DIV
VLDO 2V/DIV
RESET B 2V/DIV
RESET B 2V/DIV
10ms/DIV
VLDO 2V/DIV
10ms/DIV
FIGURE 8. SHUT DOWN VIN HOST = 3.3V AT NO LOAD (PFM)
VIN HOST 5V/DIV
FIGURE 9. SHUT DOWN VIN HOST = 3.3V AT NO LOAD (PWM)
VIN HOST 5V/DIV
SMPS 1V/DIV
SMPS 1V/DIV
VIN REMOTE 1V/DIV
VIN REMOTE 1V/DIV
VLDO 2V/DIV
VLDO 2V/DIV
RESET B 2V/DIV
RESET B 2V/DIV
1ms/DIV
10ms/DIV
FIGURE 10. START-UP VIN HOST = 3.3V AT 0.8A LOAD (PWM)
VIN HOST 5V/DIV
SMPS 1V/DIV
FIGURE 11. SHUTDOWN VIN HOST = 3.3V AT 0.8A LOAD (PWM)
VIN HOST 5V/DIV
SMPS 1V/DIV
VIN REMOTE 1V/DIV
VIN REMOTE 1V/DIV
VLDO 2V/DIV
VLDO 2V/DIV
RESET B 2V/DIV
RESET B 2V/DIV
1ms/DIV
FIGURE 12. START-UP VIN HOST = 3.3V AT 0.8A LOAD (PFM)
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10ms/DIV
FIGURE 13. SHUTDOWN VIN HOST = 3.3V AT 0.8A LOAD (PFM)
FN7886.1
May 15, 2013
ISL80083
Typical Performance Curves and Waveforms (Continued)
VIN HOST 1V/DIV
SMPS 1V/DIV
VIN HOST 1V/DIV
SMPS 1V/DIV
VIN REMOTE 5V/DIV
VIN REMOTE 5V/DIV
VLDO 2V/DIV
VLDO 2V/DIV
RESET B 2V/DIV
RESET B 2V/DIV
1ms/DIV
10ms/DIV
FIGURE 14. START-UP VIN REMOTE = 3.3V AT NO LOAD (PWM)
VIN HOST 1V/DIV
SMPS 1V/DIV
FIGURE 15. SHUTDOWN VIN REMOTE = 3.3V AT NO LOAD (PWM)
VIN HOST 1V/DIV
SMPS 1V/DIV
VIN REMOTE 5V/DIV
VIN REMOTE 5V/DIV
VLDO 2V/DIV
VLDO 2V/DIV
RESET B 2V/DIV
RESET B 2V/DIV
1ms/DIV
10ms/DIV
FIGURE 16. START-UP VIN REMOTE = 3.3V AT NO LOAD (PFM)
VIN HOST 1V/DIV
SMPS 1V/DIV
FIGURE 17. SHUTDOWN VIN REMOTE = 3.3V AT NO LOAD (PFM)
VIN HOST 1V/DIV
SMPS 1V/DIV
VIN REMOTE 5V/DIV
VIN REMOTE 5V/DIV
VLDO 2V/DIV
VLDO 2V/DIV
M4 RESET
B 2V/DIV
RESET
B 2V/DIV
RESET B 2V/DIV
1ms/DIV
FIGURE 18. START-UP VIN REMOTE = 3.3V AT 0.8A LOAD (PFM)
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10ms/DIV
FIGURE 19. SHUTDOWN VIN REMOTE = 3.3V AT 0.8A LOAD (PFM)
FN7886.1
May 15, 2013
ISL80083
Typical Performance Curves and Waveforms (Continued)
VIN HOST 1V/DIV
VIN HOST 1V/DIV
SMPS 1V/DIV
SMPS 1V/DIV
VIN REMOTE 5V/DIV
VIN REMOTE 5V/DIV
VLDO 2V/DIV
VLDO 2V/DIV
RESET B 2V/DIV
RESET B 2V/DIV
10ms/DIV
1ms/DIV
FIGURE 20. START-UP VIN REMOTE = 3.3V AT 0.8A LOAD (PWM)
FIGURE 21. SHUTDOWN VIN REMOTE = 3.3V AT 0.8A LOAD (PWM)
LX 1V/DIV
LX 1V/DIV
5ns/DIV
5ns/DIV
FIGURE 22. JITTER AT NO LOAD (PWM), VIN = 3.3V
FIGURE 23. JITTER AT FULL LOAD (PWM), VIN = 3.3V
LX 2V/DIV
LX 2V/DIV
SMPS 10mV/DIV
SMPS 20mV/DIV
IL 0.5A/DIV
IL 0.5A/DIV
200ns/DIV
FIGURE 24. STEADY STATE AT NO LOAD (PWM), VIN = 3.3V
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50ms/DIV
FIGURE 25. STEADY STATE AT NO LOAD (PFM), VIN = 3.3V
FN7886.1
May 15, 2013
ISL80083
Typical Performance Curves and Waveforms (Continued)
LX 5V/DIV
LX 2V/DIV
SMPS 10mV/DIV
SMPS 10mV/DIV
IL 0.5A/DIV
IL 0.5A/DIV
200ns/DIV
200ns/DIV
FIGURE 26. STEADY STATE AT 0.8A LOAD (PWM), VIN = 3.3V
FIGURE 27. STEADY STATE AT 0.8A LOAD (PFM), VIN = 3.3V
SMPS RIPPLE 50mV/DIV
SMPS RIPPLE 100mV/DIV
IOUT 0.5A/DIV
IL 0.5A/DIV
50µs/DIV
50µs/DIV
FIGURE 28. LOAD TRANSIENT (PWM), VIN = 3.3V
LX 2V/DIV
FIGURE 29. LOAD TRANSIENT (PFM), VIN = 3.3V
SMPS 0.5V/DIV
SMPS 1V/DIV
IL 1A/DIV
IL 2A/DIV
RESET B 2V/DIV
RESET B 2V/DIV
5µs/DIV
10ms/DIV
FIGURE 30. OUTPUT SHORT CIRCUIT, VIN = 3.3V
FIGURE 31. OVERCURRENT PROTECTION, VIN = 3.3V
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ISL80083
Typical Performance Curves and Waveforms (Continued)
LX 2V/DIV
LX 2V/DIV
SMPS RIPPLE 20mV/DIV
SMPS RIPPLE 20mV/DIV
IL 0.5A/DIV
IL 0.5A/DIV
200mA MODE TRANSITION, COMPLETELY
ENTER TO PWM AT 206mA
BACK TO PFM AT 110mA
5µs/DIV
5µs/DIV
FIGURE 32. PFM TO PWM TRANSITION, VIN = 3.3V
FIGURE 33. PWM TO PFM TRANSITION, VIN = 3.3V
LX 2V/DIV
TA = +150°C
SMPS 0.5V/DIV
SMPS 2V/DIV
IL 1A/DIV
RESET B 1V/DIV
RESET B 2V/DIV
200µs/DIV
1ms/DIV
FIGURE 34. OVERVOLTAGE PROTECTION, VIN = 3.3V
FIGURE 35. OVER-TEMPERATURE PROTECTION, VIN = 3.3V
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ISL80083
Input Selector Operation
Overcurrent Protection
Input power for the ISL80083 is automatically selected from one
of two source pins; VIN_HOST or VIN_REMOTE. The rising slew
rate of VIN_HOST or VIN_REMOTE is assumed to be 120V/ms or
less. The selector output is VSELECT and should be de-coupled
with a 10µF or greater MLCC. In addition to choosing which input
will provide power, the selector provides de-bounce, a soft-start to
limit inrush current and it protects other circuit blocks of the
ISL80083 against overvoltage.
The overcurrent protection is realized by monitoring the current
through the PFET, Q5 in the block diagram. Upon detection of
overcurrent condition, the upper MOSFET will be immediately
turned off and will not be turned on again until the next switching
cycle. Upon detection of the initial overcurrent condition, the
overcurrent fault counter is set to 1. If, on the subsequent cycle,
another overcurrent condition is detected, the OC fault counter
will be incremented. If there are 17 sequential OC fault
detections, the regulator will be shut down under an overcurrent
fault condition. An overcurrent fault condition will result in the
switcher and LDO attempting to restart in a hiccup mode within
the delay of 600µs. At the end of the wait period, the fault
counters are reset and soft-start is attempted again.
Typically, when either input pin exceeds 2.2V, it is considered “in
range” and its switch is activated over approximately 300µs,
which limits the surge to the VSELECT capacitor. Once complete,
the selector provides typically a 200m path between the
selected input and VSELECT. The un-selected input is isolated
from VSELECT and <5µA will flow in or out of the input.
In the case that both inputs enter the selectable range at the
same moment, the VIN_HOST will be selected. Otherwise, the
selector will simply choose the first input that comes in range.
Typically, overvoltage is considered to be greater than 4.5V. If this
condition occurs, the selector will disconnect this input within
5µs. In the case that neither input is considered in range, the
selector will isolate both inputs from VSELECT and the ISL80083
will remain in an un-powered state until an input comes in range.
SMPS Introduction
The SMPS converter on ISL80083 uses the peak-current-mode
pulse-width modulation (PWM) control scheme for fast transient
response and pulse-by-pulse current limiting. The converter is
able to supply up to 800mA load current. The default output
voltage is 1V upon start-up and can be programmed via the I2C
interface in the range of 0.625V to 2.225V at 25mV/step with a
programmable slew rate using the register SMPS_OUT. When
OSC_EN is pulled low, the I2C register 03H switches over. The
default output is still 1V and will operate in PFM. Optionally, the
SMPS can be programmed to be actively discharged via an
on-chip bleeding resistor (typical 115Ω) when the converter is
disabled.
Soft-Start
Upon VSELECT engaged, the output is defaulted to 1V with a rise
time of about 1ms to reduce the in-rush. Then 1ms of delay later,
the LDO will rise to 1.8V in 20ms. See Figure 36, start-up
sequence for more details.
RESET
RESET is the totem pole window comparator output that
continuously monitors the buck regulator output voltage via the
FB pin. RESET is actively held low when disabled and during the
buck regulator soft-start period. RESET goes high after 1ms or
8.4ms delay as long as the output voltages of the switcher and
LDO are above 95% of the nominal regulation voltage. The delay
time is controlled via the I2C interface. The default delay time is
1ms. When VOUT drops 10% below the nominal regulation
voltage, the ISL80083 pulls RESET low. Any fault condition forces
RESET low until the fault condition is cleared by attempts to softstart.
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Likewise, an overcurrent on the LDO output still results in the
switcher and LDO attempting to restart in a hiccup mode within
the delay of 600µs. The 1V SMPS and 1VAUX will soft-start first,
then the LDO will attempt to start 1ms later. The LDO output may
not reach regulation unless an overcurrent condition is removed.
Once an overcurrent fault is removed, RESET will transition high
after the delay time when the LDO voltage reaches regulation.
Negative Current Protection
Similar to the overcurrent, the negative current protection is
realized by monitoring the current across the lowside N-FET, as
shown in the “Block Diagram” on page 4. When the valley point of
the inductor current reaches -1A for 2 consecutive cycles, both
P-FET and N-FET are off. The 115 parallel to the N-FET will
activate discharging the output into regulation. The control will
begin to switch when output is within regulation. The regulator will
be in PFM for 20µs before switching to PWM if necessary.
Undervoltage Lockout (UVLO)
An undervoltage lockout (UVLO) circuit is provided on the
ISL80083. The UVLO circuit block can prevent abnormal
operation in the event that the supply voltage is too low to
guarantee proper operation. The UVLO on VSELECT is set for a
typical 2.49V with 100mV hysteresis. When the input voltage is
sensed to be lower than the UVLO threshold, all the related
channels are disabled.
Low Dropout Operation
The SMPS converter features low dropout operation, which
maximizes the battery life. When the input voltage drops to a
level that the converter can no longer operate under switching
regulation to maintain the output voltage, the P-Channel MOSFET
is completely turned on (100% duty cycle). The dropout voltage
under such conditions is the product of the load current and the
ON-resistance of the P-Channel MOSFET. Minimum required
input voltage VSELECT under such conditions is the sum of the
output voltage plus the voltage drop across the inductor and the
P-Channel MOSFET switch.
Active Output Voltage Discharge For SMPS
The ISL80083 offers a feature to actively discharge the output
voltage of SMPS via an internal bleeding resistor (typically 115Ω)
when the channel is disabled. This feature is enabled by default,
but the output can be disabled through programming the control
bit in SMPS_PARAMETER register.
FN7886.1
May 15, 2013
ISL80083
3.0V Clamp Output
The V3CLAMP is a 3V LDO sourced from VSELECT capable of
providing up to 15mA. There is an internal clamp to prevent this
output from exceeding 3.3V.
1V Auxiliary Output
The 1V AUX is an auxiliary output sourced from the 1V switcher.
The 50m PFET is controlled by using I2C. There is
approximately 5ms delay time from the enable to the output
start-up. Soft-start rise time is approximately 20µs to prevent a
VIN_HOST
or
VIN_REMOTE
switcher glitch. Pulling OSC_EN low can also disable the 1VAUX
output.
Thermal Shutdown
When the die temperature of ISL80083 reaches +150°C, the
regulator is completely shut down and as the temperature drops
to +120°C (typical), the device resumes normal operation after
initiate its soft-start cycle.
3.3V
3V
VSELECT
2.3V
V3CLAMP
1ms
CLK2P3OUT
1ms
1.8V
1.8V LDO
1V
1V SMPS
1VAUX
1ms
1.5ms
1ms
RESET
OSC
1ms
OSC_EN
FIGURE 36. START-UP AND SHUTDOWN SEQUENCE
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ISL80083
I2C Compatible Interface
specifications, here the value of Bit 0 determines the direction of
the message (“0” means “write” and “1” means “read”).
The ISL80083 offers an I2C compatible interface, using two pins:
SCLK for the serial clock and SDAT for serial data respectively.
According to the I2C specifications, there are internal 5kΩ pull-up
resistors for the clock and data signals connected to V3PCLAMP.
MSB
Signal timing specifications should satisfy the standard I2C bus
specification. The maximum bit rate is 400kb/s and more details
regarding the I2C specifications can be found from Philips.
LSB
1
1
0
1
1
0
0
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
I2C Slave Address
FIGURE 37. I2C SLAVE ADDRESS
The ISL80083 serves as a slave device and the 7-bit default chip
address is 1101100, as shown in Figure 37. According to the I2C
S
SLAVE ADDRESS
0 A
REGISTER ADDRESS
I2C Protocol
Figure 38 shows typical I2C-bus transaction protocols.
A
DATA BYTE 1
A
P
SYSTEM HOST
ISL80083H
R/W
A – ACKNOWLEDGE
N – NOT ACKNOWLEDGE
S – START
P – STOP
FIGURE 38A. I2C WRITE
S
SLAVE ADDRESS
0 A
REGISTER ADDRESS
A
P
S
SLAVE ADDRESS
R/W
R/W
1 A
DATA BYTE N
N P
SYSTEM HOST
ISL80083H
A – ACKNOWLEDGE
N – NOT ACKNOWLEDGE
S – START
P – STOP
FIGURE 38B. I2C READ
FIGURE 38.
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ISL80083
I2C Control Registers
LDO OUTPUT VOLTAGE CONTROL REGISTER
All the registers are reset at initial start-up.
LDO_OUT, address 0x01h.
TABLE 3. LDO OUTPUT VOLTAGE CONTROL REGISTERS
CONTROL REGISTER
PARAMETERS, address 0x00h
BIT
TABLE 2. REAL TIME OSC ADJUSTMENT REGISTER
BIT
NAME
ACCESS RESET
NAME
ACCESS
RESET
B7
1VAUX_EN
R/W
1
DESCRIPTION
B7 OSC_TRIM
R/W
0
Reg00h Value
Adjustment
B6
RESERVED
R/W
1
B6 OSC_TRIM
R/W
0
LDO_OUT-5
R/W
0
R/W
0
+127
+126
B5
B5 OSC_TRIM
B4
LDO_OUT-4
R/W
1
B4 OSC_TRIM
R/W
0
B3
LDO_OUT-3
R/W
0
B3 OSC_TRIM
R/W
0
B2
LDO_OUT-2
R/W
0
B2 OSC_TRIM
R/W
0
B1
LDO_OUT-1
R/W
1
B1 OSC_TRIM
R/W
0
0111 1111
0111 1110
|
|
0000 0001
0000 0000
1111 1111
|
|
1000 0001
1000 0000
B0
LDO_OUT-0
R/W
0
B0 OSC_TRIM
R/W
0
+1
0
-1
-2
-127
-128
DESCRIPTION
1VAUX enable
selection. 0-enable,
1-disable
Refer to Table 4 for
LDO output voltage
settings
TABLE 4. LDO OUTPUT VOLTAGE SETTINGS
LDOOUT
<5:0>
LDO OUTPUT
VOLTAGE (V)
LDOOUT
<5:0>
LDO OUTPUT
VOLTAGE (V)
LDOOUT
<5:0>
LDO OUTPUT
VOLTAGE (V)
LDOOUT
<5:0>
LDO OUTPUT
VOLTAGE (V)
00H
0.9
10H
1.70
20H
2.50
30H
3.30
01H
0.95
11H
1.75
21H
2.55
31H
3.35
02H
1.00
12H
1.80
22H
2.60
32H
3.40
03H
1.05
13H
1.85
23H
2.65
33H
3.45
04H
1.1
14H
1.90
24H
2.70
34H
3.50
05H
1.15
15H
1.95
25H
2.75
35H
3.55
06H
1.20
16H
2.00
26H
2.80
36H
3.60
07H
1.25
17H
2.05
27H
2.85
08H
1.30
18H
2.10
28H
2.90
09H
1.35
19H
2.15
29H
2.95
0AH
1.40
1AH
2.20
2AH
3.00
0BH
1.45
1BH
2.25
2BH
3.05
0CH
1.50
1CH
2.30
2CH
3.10
0DH
1.55
1DH
2.35
2DH
3.15
0EH
1.60
1EH
2.40
2EH
3.20
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ISL80083
SMPS OUTPUT VOLTAGE CONTROL REGISTER
TABLE 5. BUCK CONVERTER OUTPUT VOLTAGE CONTROL REGISTER
SMPS_OUT, address 0x02h
BIT
NAME
ACCESS
RESET
Caution: Disable SMPS prior to changing from fixed output
voltage to adjustable output voltage or from adjustable output
voltage to fixed output voltage using I2C.
B7
OSC_CONTROL
R/W
1
33MHz oscillator control
selection. 0-off, 1-on
B6
SMPS_EN
R/W
1
SMPS enable selection.
0-disable, 1-enable
B5
SMPS_pwm-5
R/W
0
B4
SMPS_pwm-4
R/W
0
Refer to Table 6 for SMPS
output voltage setting
B3
SMPS_pwm-3
R/W
1
B2
SMPS_pwm-2
R/W
1
B1
SMPS_pwm-1
R/W
1
B0
SMPS_pwm-0
R/W
1
DESCRIPTION
TABLE 6. SMPS OUTPUT VOLTAGE SETTING
SMPS OUTPUT
VOLTAGE
(V)
SMPSOUT
<5:0>
SMPS OUTPUT
VOLTAGE
(V)
1DH
1.375
3BH
2.125
1EH
1.400
3CH
2.150
0.675
1FH
1.425
3DH
2.175
0.700
20H
1.450
3EH
2.200
21H
1.475
3FH
2.225
22H
1.500
SMPSOUT
<5:0>
SMPS OUTPUT
VOLTAGE
(V)
SMPSOUT
<5:0>
00H
0.625
01H
0.650
02H
03H
04H
0.725
05H
0.750
06H
0.775
23H
1.525
07H
0.800
24H
1.550
08H
0.825
25H
1.575
09H
0.850
26H
1.600
0AH
0.875
27H
1.625
0BH
0.900
28H
1.650
0CH
0.925
29H
1.675
0DH
0.950
2AH
1.700
0EH
0.975
2BH
1.725
0FH
1.000
2CH
1.750
10H
1.025
2DH
1.775
11H
1.050
2EH
1.800
12H
1.075
2FH
1.825
13H
1.100
30H
1.850
14H
1.125
31H
1.875
15H
1.150
32H
1.900
16H
1.175
33H
1.925
17H
1.200
34H
1.950
18H
1.225
35H
1.975
19H
1.250
36H
2.000
19H
1.275
37H
2.025
1AH
1.300
38H
2.050
1BH
1.325
39H
2.075
1CH
1.350
3AH
2.100
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ISL80083
SMPS OUTPUT VOLTAGE CONTROL REGISTER
TABLE 7. BUCK CONVERTER OUTPUT VOLTAGE CONTROL REGISTER
SMPS_SLEEP, address 0x03h
BIT
Caution: Disable SMPS prior to changing from fixed output
voltage to adjustable output voltage or from adjustable output
voltage to fixed output voltage using I2C.
B7
NAME
ACCESS
RESET
DESCRIPTION
RESET_DY
R/W
0
RESET Delay Time,
00 to 1.07ms
01 to 8.4ms
B6
SMPSSR
R/W
0
SMPS Slew Rate Setting,
0 to 0.19mV/µs
1 to 0.38mV/µs
B5
SMPS_pfm-5
R/W
0
B4
SMPS_pfm-4
R/W
0
Refer to Table 8 for SMPS
output voltage setting.
B3
SMPS_pfm-3
R/W
1
B2
SMPS_pfm-2
R/W
1
B1
SMPS_pfm-1
R/W
1
B0
SMPS_pfm-0
R/W
1
TABLE 8. SMPS OUTPUT VOLTAGE SETTING
SMPSOUT
<5:0>
SMPS OUTPUT
VOLTAGE
(V)
0.625
1CH
1.350
39H
2.075
0.650
1DH
1.375
3AH
2.100
02H
0.675
1EH
1.400
3BH
2.125
03H
0.700
1FH
1.425
3CH
2.150
04H
0.725
20H
1.450
3DH
2.175
05H
0.750
21H
1.475
3EH
2.200
3FH
2.225
SMPSOUT
<5:0>
SMPS OUTPUT
VOLTAGE
(V)
00H
01H
06H
0.775
22H
1.500
07H
0.800
23H
1.525
08H
0.825
24H
1.550
09H
0.850
25H
1.575
0AH
0.875
26H
1.600
0BH
0.900
27H
1.625
0CH
0.925
28H
1.650
0DH
0.950
29H
1.675
0EH
0.975
2AH
1.700
0FH
1.000
2BH
1.725
10H
1.025
2CH
1.750
11H
1.050
2DH
1.775
12H
1.075
2EH
1.800
13H
1.100
2FH
1.825
14H
1.125
30H
1.850
15H
1.150
31H
1.875
16H
1.175
32H
1.900
17H
1.200
33H
1.925
18H
1.225
34H
1.950
19H
1.250
35H
1.975
19H
1.275
36H
2.000
1AH
1.300
37H
2.025
1BH
1.325
38H
2.050
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SMPSOUT
<5:0>
SMPS OUTPUT
VOLTAGE
(V)
FN7886.1
May 15, 2013
ISL80083
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
May 15, 2013
FN7886.1
CHANGE
Initial Release
About Intersil
Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management
semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal
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For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
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in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
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FN7886.1
May 15, 2013
ISL80083
Package Outline Drawing
W5x5.25B
5X5 ARRAY 25 BALL WITH 0.40 PITCH WAFER LEVEL CHIP SCALE PACKAGE (WLCSP)
Rev 2, 12/11
X
Y
1.60
2.11±0.03
25x 0.225±0.03
E
D
0.40
2.13±0.03
1.60
C
B
0.265
A
0.10
PIN 1 (A1 CORNER)
(4X)
TOP VIEW
1
2
3
4
0.254
5
0.40
BOTTOM VIEW
0.25
PACKAGE
OUTLINE
0.305±0.025
0.225
0.55 MAX
0.40
Z SEATING PLANE
0.19±0.03
3
0.25±0.03
NSMD
TYPICAL RECOMMENDED LAND PATTERN
0.10
0.05
ZXY
Z
0.05 Z
SIDE VIEW
NOTES:
1. All dimensions are in millimeters.
2. Dimension and tolerance per ASMEY 14.5M-1994,
and JESD 95-1 SPP-010.
3. NSMD refers to Non-Solder Mask Defined pad design per
Intersil Tech Brief TB451 located at:
http://www.intersil.com/data/tb/tb451.pdf.
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