DATASHEET

ISL6424
®
Data Sheet
September 13, 2005
Dual Output LNB Supply and Control
Voltage Regulator with I2C Interface for
Advanced Satellite Set-Top Box Designs
The ISL6424 is a highly integrated voltage regulator and
interface IC, specifically designed for supplying power and
control signals from advanced satellite set-top box (STB)
modules to the low noise blocks (LNBs) of two antenna
ports. The device is comprised of two independent currentmode boost PWMs and two low-noise linear regulators along
with the circuitry required for 22kHz tone generation,
modulation and I2C device interface. The device makes the
total LNB supply design simple, efficient and compact with
low external component count.
FN9175.3
Features
• Single Chip Power Solution
- True Dual Operation for 2-Tuner/2-Dish Applications
- Both Outputs May be Enabled Simultaneously at
Maximum Power
- Integrated DC-DC Converter and I2C Interface
• Switch-Mode Power Converter for Lowest Dissipation
- Boost PWMs with > 92% Efficiency
- Selectable 13V or 18V Outputs
- Digital Cable Length Compensation (1V)
• I2C Compatible Interface for Remote Device Control
- Registered Slave Address 0001 00XX
- Full 3.3V/5V Operation up to 400kHz
Two independent current-mode boost converters provide the
linear regulators with input voltages that are set to the final
output voltages, plus typically 1.2V to insure minimum power
dissipation across each linear regulator. This maintains
constant voltage drops across each linear pass element
while permitting adequate voltage range for tone injection.
• External Pins to Select 13V/18V Option
• DSQIN1&2 and SEL18V1&2 pins 2.5V Logic Compatible
The final regulated output voltages are available at two
output terminals to support simultaneous operation of two
antenna ports for dual tuners. The outputs for each PWM are
set to 13V or 18V by independent voltage select commands
(VSEL1, VSEL2) through the I2C bus. Additionally, to
compensate for the voltage drop in the coaxial cable, the
selected voltage may be increased by 1V with the line length
compensation (LLC) feature. All the functions on this IC are
controlled via the I2C bus by writing 8 bits on System
Register (SR, 8 bits). The same register can be read back,
and two bits will report the diagnostic status. Separate enable
commands sent on the I2C bus provide independent standby
mode control for each PWM and linear combination, disabling
the output into shutdown mode.
• LNB Short-Circuit Protection and Diagnostics
Each output channel is capable of providing 750mA of
continuous current. The overcurrent limit can be digitally
programmed. The SEL18V pin allows the 13V to 18V
transition with an external pin, overriding the I2C input.
The ISL6424 is offered in a 32 Ld 5x5 QFN.
• Built-In Tone Oscillator Factory Trimmed to 22kHz
- Facilitates DiSEqC (EUTELSAT) Encoding
• Internal Over-Temperature Protection and Diagnostics
• Internal Overload and Overtemp Flags (Visible on I2C)
• QFN Package
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Product Outline
- Near Chip-Scale Package Footprint
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• LNB Power Supply and Control for Satellite Set-Top Box
References
• Tech Brief 389 (TB389) - “PCB Land Pattern Design and
Surface Mount Guidelines for QFN Packages”; Available
on the Intersil website, www.intersil.com
Ordering Information
PART # *
ISL6424ER
PART
MARKING
ISL6424ER
TEMP.
(°C)
PACKAGE
PKG.
DWG. #
-20 to 85 32 Ld 5x5 QFN L32.5x5
ISL6424ERZ (Note) ISL6424ERZ -20 to 85 32 Ld 5x5 QFN L32.5x5
(Pb-free)
*Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004-2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL6424
Pinout
GATE2
FB2
COMP2
VSW2
NC
VCC
CPVOUT
CPSWIN
ISL6424 (QFN)
TOP VIEW
32
31
30
29
28
27
26
25
PGND2
1
24
CPSWOUT
CS2
2
23
TCAP2
SGND
3
22
DSQIN2
SEL18V1
4
21
VO2
SEL18V2
5
20
AGND
BYP
6
19
VO1
PGND1
7
18
DSQIN1
GATE1
8
17
TCAP1
2
FB1
COMP1
VSW1
13
14
15
16
SCL
12
ADDR
11
SDA
10
NC
9
CS1
ISL6424ER
FN9175.3
September 13, 2005
Block Diagram
14
4
S
3
ADDR
ISEL1
PGND1
-
CS1
+
BAND GAP
REF VOLTAGE
COMP1
+
-
REF
VOLTAGE
ADJ2
SEL18V2
TONE
INJ
CKT 2
VSW2
+
-
30
31
5
29
21
ENT2
ON CHIP
LINEAR
UVLO
POR
SOFT-START
FN9175.3
September 13, 2005
6
CPVOUT
INT 5V
SOFT-START
EN1/EN2
20
17
18
22
TCAP2
ENT1
DSQIN2
SGND
FB2
VREF2
VO2
BYPASS
3
COMP2
22kHz
TONE
+
-
2
SLOPE
COMPENSATION
CLK2
VO1
VCC
CS2
∑
DCL
÷ 10 &
WAVE SHAPING
DSQIN1
27
VSW1
CS
AMP
BGV
TONE
INJ
CKT 1
TCAP1
19
VREF1
ENT2
LLC2
ILIM2
23
OTF
THERMAL
SHUTDOWN
CHARGE PUMP
CPSWIN
CPSWOUT
24
26
25
ISL6424
12
BGV
REF
VOLTAGE
ADJ1
FB1
EN2
VSEL2
OSC.
220kHz
1
+
10
VSEL1
CLK1
SLOPE
COMPENSATION
11
LLC1
∑
AGND
9
OTF
PGND2
ISEL2
I2 C
INTERFACE
ENT1
ILIM1
CS
AMP
32
S
SCL
OLF2
OLF1
EN1
GATE2
Q
CLK2
CLK1
COUNTER
PWM
LOGIC
OC2
SDA
7
SCL
ADDR
SDA
OC1
+
Q
OVERCURRENT
PROTECTION
LOGIC SCHEME 2
DCL
-
8
OLF2
SEL18V1
DCL
PWM
LOGIC
GATE1
16
-
OLF1
OVERCURRENT
PROTECTION
LOGIC SCHEME 1
COUNTER
15
Typical Application Schematic
P1
VIN
P2
C3
5.1
1500pF
L3
D1
100nH
C4
1µF
C27A
10µF
+
C27B
10µF
STPS2L40U
C5
56µF
E
8
7
6
5
Q1
E
C5
33pF
0.10
1500pF
C30
0.01µF
E
VOUT1
E
C15
1µF
1µF
U1
ISL6424
E
C12
D
1
2
3
4
8
7
6
5
GATE2
CS2
PGND2
COMP2
FB2
VSW2
VO2
DSQIN2
2
8V
L1
SE
32
2
1
30
31
29
21
22
C24
R10
100
5.1
D2
STPS2L40U +
C17
56µF
100pF
C13
R5
1500pF
68K
C14
33pF
C31
0.01µF
P5
R12
10K
C19
0.1µF
R16
100K
R17
100K
E
R15
100K
P9
P8
100
R8
D
R14
100K
VL
R7
J1
SCL 1 1
GND 2 2
GND 3 3
SDA 4 4
1x4
D4
STPS2L40U
P6
IN VL
R11
10K
100
FN9175.3
September 13, 2005
1
2
3
4
5
6
D
SW1
12
11
10
9
8
7
DISQ1
DISQ2
SEL18V1
SEL18V2
ADDR
DIP_SW5_SPST
VOUT2
SP2
E
E
C26
1µF
E
E
R13
100K
C29
0.1µF
100nH
C18
1µF
E
E
OUT
C28B
10µF
0.10
C21
0.1µF
P7
L4
C28A
10µF
R4
E
P4
R6
D
SP1
+5V/+3.3V
Q2
FDS6612A
P3
D3
STPS2L40U
GND
L2
33µH
SEL18V1
SEL18V2
GND
ISL6424
R3
C15
10µF
E
4.7µF
GATE1
CS1
PGND
COMP1
FB1
VSW1
VO1
DSQIN1
33 EP
+
C21
1µF
C8
8
9
7
11
10
12
19
18
100pF
68K
1000pF
D
R9
100
C7
0.047µF
C2
E
FDS6612A
R2
C24
E
1
2
3
4
C10
17
37
38
36
35
34
6
23
4
R1
E
C9
TCAP1
VCC
NC
CPVOUT
CPSWIN
CPSWOUT
BYP
TCAP2
L1
33µH
C15A
56µF
C1A
56µF
SCL
SDA
ADDR
SGND
NC
AGND
SEL18V1
E
C25
1µF
+
C1B
10µF
16
14
15
3
13
20
4
5
GND
ISL6424
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0V to 18.0V
Logic Input Voltage Range
(SDA, SCL, ENT, DSQIN 1&2, SEL18V 1&2) . . . . . . -0.5V to 7V
Thermal Resistance (Typical, Notes 1, 2)
θJA (°C/W)
θJC (°C/W)
QFN Package. . . . . . . . . . . . . . . . . . . .
32
4
Maximum Junction Temperature (Note 3) . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -40°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
Operating Temperature Range . . . . . . . . . . . . . . . . . . -20°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
3. The device junction temperature should be kept below 150°C. Thermal shut-down circuitry turns off the device if junction temperature exceeds
+150°C typically.
Electrical Specifications
VCC = 12V, TA = -20°C to +85°C, unless otherwise noted. Typical values are at TA = 25°C. EN1 = EN2 = H,
LLC1 = LLC2 = L, ENT1 = ENT2 = L, DCL = L, DSQIN1 = DSQIN2 = L, Iout = 12mA, unless otherwise noted.
See software description section for I2C access to the system.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
8
12
14
V
EN1 = EN2 = L
-
1.5
3.0
mA
EN1 = EN2 = LLC1 = LLC2 = VSEL1 =
VSEL2 = ENT1 = ENT2 = H, No Load
-
4.0
8.0
mA
Start Threshold
7.5
-
7.95
V
Stop Threshold
7.0
-
7.55
V
Start to Stop Hysteresis
350
400
500
mV
-
512
-
Cycles
Operating Supply Voltage Range
Standby Supply Current
Supply Current
IIN
UNDERVOLTAGE LOCKOUT
SOFT-START
COMP Rise Time (Note 4)
(Note 5)
Output Voltage (Note 5)
Line Regulation
Load Regulation
Dynamic Output Current Limiting
VO1
VSEL1 = L, LLC1 = L
12.74
13.0
13.26
V
VO1
VSEL1 = L, LLC1 = H
13.72
14.0
14.28
V
VO1
VSEL1 = H, LLC1 = L
17.64
18.0
18.36
V
VO1
VSEL1 = H, LLC1 = H
18.62
19.0
19.38
V
VO2
VSEL2 = L, LLC2 = L
12.74
13.0
13.26
V
VO2
VSEL2 = L, LLC2 = H
13.72
14.0
14.28
V
VO2
VSEL2 = H, LLC2 = L
17.64
18.0
18.36
V
VO2
VSEL2 = H, LLC2 = H
18.62
19.0
19.38
V
DVO1,
DVO2
VIN = 8V to 14V; VO1, VO2 = 13V
-
4.0
40.0
mV
VIN = 8V to 14V; VO1, VO2 = 18V
-
4.0
60.0
mV
DVO1,
DVO2
IO = 12mA to 350mA
-
50
80
mV
IO = 12mA to 750mA (Note 6)
-
100
200
mV
IMAX
DCL = L, ISEL1/2 = L
425
-
550
mA
DCL = L, ISEL1/2 = H (Note 6)
775
850
950
mA
-
900
-
ms
-
20
-
ms
Dynamic Overload Protection Off Time
TOFF
Dynamic Overload Protection On Time
TON
5
DCL = L, Output Shorted (Note 6)
FN9175.3
September 13, 2005
ISL6424
Electrical Specifications
VCC = 12V, TA = -20°C to +85°C, unless otherwise noted. Typical values are at TA = 25°C. EN1 = EN2 = H,
LLC1 = LLC2 = L, ENT1 = ENT2 = L, DCL = L, DSQIN1 = DSQIN2 = L, Iout = 12mA, unless otherwise noted.
See software description section for I2C access to the system. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
22kHz TONE SECTION
Tone Frequency
ftone
ENT1/2 = H
20.0
22.0
24.0
kHz
Tone Amplitude
Vtone
ENT1/2 = H
500
680
800
mV
Tone Duty Cycle
dctone
ENT1/2 = H
40
50
60
%
Tone Rise or Fall Time
Tr, Tf
ENT1/2 = H
5
8
14
µs
Iout = 750mA (Note 6)
-
1.2
-
V
Asserted LOW
-
-
0.8
V
Asserted HIGH
1.7
-
-
V
-
1
-
µA
-
700
-
nA
Static current mode, DCL = H
325
400
500
mV
LINEAR REGULATOR
Drop-out Voltage
DSQIN PIN 1&2, SEL18V 1&2 INPUT PINs (Note 11)
Input Current
CURRENT SENSE
Input Bias Current
IBIAS
Over Current Threshold
ERROR AMPLIFIER
Open Loop Voltage Gain
AOL
(Note 6)
70
88
-
dB
Gain Bandwidth Product
GBP
(Note 6)
10
-
-
MHz
90
93
-
%
-
20
-
ns
200
220
240
kHz
PWM
Maximum Duty Cycle
Minimum Pulse Width
(Note 6)
OSCILLATOR
Oscillator Frequency
fo
Fixed at (10)(ftone)
THERMAL SHUTDOWN
Temperature Shutdown Threshold
(Note 6)
-
150
-
Temperature Shutdown Hysteresis
(Note 6)
-
20
-
NOTES:
4. Internal digital soft-start.
5. VO1 for LNB1, VO2 for LNB2. Voltage programming signals VSEL1, VSEL2, LLC1, and LLC2 are implemented via the I2C bus.
IO1 = IO2 = 350mA/750mA.
6. Guaranteed by design.
7. Unused DSQIN 1&2 pins should be connected to GND. SEL18V1&2 pins have 200K internal pulldown resistors.
6
FN9175.3
September 13, 2005
ISL6424
Typical Performance Curves
0.80
0.70
IOUT (A)
0.60
IOUT_max
0.50
0.40
0.30
0.20
0.10
0.00
0
20
40
60
80
TEMPERATURE (°C)
FIGURE 1. OUTPUT CURRENT DERATING
NOTE: With both channels in simultaneous operation at rated output
Functional Pin Description
SYMBOL
FUNCTION
SDA
Bidirectional data from/to I2C bus.
SCL
Clock from I2C bus.
VSW1, 2
Input of the linear post-regulator.
PGND1, 2 Dedicated ground for the output gate driver of
respective PWM.
CS1, 2
Current sense input; connect Rsc at this pin for
desired over current value for respective PWM.
SGND
Small signal ground for the IC.
AGND
Analog ground for the IC.
TCAP1, 2
BYPASS
Capacitor for setting rise and fall time of the output of
LNB A and LNB B respectively. Use this capacitor
value 1µF or higher.
Bypass capacitor for internal 5V.
DSQIN1, 2 When HIGH enables internal 22kHz modulation for
LNB A and LNA B respectively, Use this pin for tone
enable function for LNB A and LNB B.
VCC
GATE1, 2
Main power supply to the chip.
These are the device outputs of PWM A and PWM B
respectively. These high current driver outputs are
capable of driving the gate of a power FET. These
outputs are actively held low when Vcc is below the
UVLO threshold.
VO1, 2
Output voltage of LNB A and LNB B respectively.
ADDR
Address pin to select two different addresses per
voltage level at this pin.
COMP1, 2 Error amp outputs used for compensation.
FB1, 2
Feedback pins for respective PWMs
CPVOUT, Charge pump connections.
CPSWIN,
CPSWOUT
SEL18V1, 2 When connected HIGH, this pin will change the output
of the respective PWM to 18V.
7
Functional Description
The ISL6424 dual output voltage regulator makes an ideal
choice for advanced satellite set-top box and personal video
recorder applications. Both supply and control voltage
outputs for two low-noise blocks (LNBs) are available
simultaneously in any output configuration. The device
utilizes built-in DC/DC step-converters that, from a single
supply source ranging from 8V to 14V, generate the voltages
that enable the linear post-regulators to work with a
minimum of dissipated power. An undervoltage lockout
circuit disables the circuit when VCC drops below a fixed
threshold (7.5V typ).
DiSEqC Encoding
The internal oscillator is factory-trimmed to provide a tone of
22kHz in accordance with DiSEqC (EUTELSAT) standards.
No further adjustment is required. The 22kHz oscillator can be
controlled either by the I2C interface (ENT1/2 bit) or by a
dedicated pin (DSQIN1/2) that allows immediate DiSEqC data
encoding separately for each LNB. (Please see Note 1 at the
end of this section.) All the functions of this IC are controlled
via the I2C bus by writing to the system registers (SR1, SR2).
The same registers can be read back, and two bits will report
the diagnostic status. The internal oscillator operates the
converters at ten times the tone frequency. The device offers
full I2C compatible functionality, 3.3V or 5V, and up to 400kHz
operation.
If the Tone Enable (ENT1/2) bit is set LOW through I2C, then
the DSQIN1/2 terminal activates the internal tone signal,
modulating the dc output with a 0.3V, 22kHz, symmetrical
waveform. The presence of this signal usually gives the LNB
information about the band to be received.
Burst coding of the 22kHz tone can be accomplished due to
the fast response of the DSQIN1/2 input and rapid tone
response. This allows implementation of the DiSEqC
(EUTELSAT) protocols.
FN9175.3
September 13, 2005
ISL6424
When the ENT1/2 bit is set HIGH, a continuous 22kHz tone
is generated regardless of the DSQIN1/2 pin logic status for
the corresponding regulator channel (LNB-A or LNB-B). The
ENT1/2 bit must be set LOW when the DSQIN1 and/or
DSQIN2 pin is used for DiSEqC encoding.
Linear Regulator
The output linear regulator will sink and source current. This
feature allows full modulation capability into capacitive loads
as high as 0.25µF. In order to minimize the power
dissipation, the output voltage of the internal step-up
converter is adjusted to allow the linear regulator to work at
minimum dropout.
When the device is put in the shutdown mode (EN1,
EN2 = LOW), both PWM power blocks are disabled. (i.e.
when EN1 = 0, PWM1 is disabled, and when EN2 = 0,
PWM2 is disabled).
When the regulator blocks are active (EN1, EN2 = HIGH),
the output can be logic controlled to be 13V or 18V (typical)
by means of the VSEL bit (Voltage Select) for remote
controlling of non-DiSEqC LNBs. Additionally, it is possible
to increment by 1V (typical) the selected voltage value to
compensate for the excess voltage drop along the coaxial
cable (LLC1/2 bit HIGH).
Output Timing
The programmed output voltage rise and fall times can be
set by an external capacitor. The output rise and fall times
will be approximately 3400 times the TCAP value. For the
recommended range of 0.47µF to 2.2µF, the rise and fall
time would be 1.6ms to 7.6ms. Using a 0.47µF capacitor
insures the PWM stays below its overcurrent threshold when
charging a 120µF VSW filter cap during the worst case 13V
to 19V transition. A typical value of 1.0µF is recommended.
This feature only affects the turn-on and programmed
voltage rise and fall times.
Current Limiting
The current limiting block has two thresholds that can be
selected by the ISEL bit of the SR and can work either
statically (simple current clamp) or dynamically. The lower
threshold is between 425mA and 550mA (ISEL = L), while
the higher threshold is between 775mA and 950mA
(ISEL = H). When the DCL (Dynamic Current Limiting) bit is
set to LOW, the overcurrent protection circuit works
dynamically: as soon as an overload is detected, the output
is shutdown for a time tOFF, typically 900ms. Simultaneously
the OLF bit of the System Register is set to HIGH. After this
time has elapsed, the output is resumed for a time tON =
20ms. During tON, the device output will be current limited to
425mA min. or 775mA min., depending on the ISEL bits. At
the end of tON, if the overload is still detected, the protection
circuit will cycle again through tOFF and tON. At the end of a
full tON in which no overload is detected, normal operation is
resumed and the OLF bit is reset to LOW. Typical tON + tOFF
time is 920ms as determined by an internal timer. This
8
dynamic operation can greatly reduce the power dissipation
in a short circuit condition, still ensuring excellent power-on
start-up in most conditions.
However, there could be some cases in which a highly
capacitive load on the output may cause a difficult start-up
when the dynamic protection is chosen. This can be solved
by initiating any power start-up in static mode (DCL = HIGH)
and then switching to the dynamic mode (DCL = LOW) after
a chosen amount of time. When in static mode, the OLF1/2
bit goes HIGH when the current limit threshold at the CS pin
reaches 0.45V typ and returns LOW when the overload
condition is cleared. The OLF1/2 bit will be LOW at the end of
initial power-on soft-start.
Thermal Protection
This IC is protected against overheating. When the junction
temperature exceeds 150°C (typical), the step-up converter
and the linear regulator are shut off and the OTF bit of the
SR is set HIGH. Normal operation is resumed and the OTF
bit is reset LOW when the junction is cooled down to 135°C
(typical).
In over temperature conditions, the OTF Flag goes HIGH
and the I2C data will be cleared. The user may need to
monitor the I2C enable bits and OTF flag continuously and
enable the chip, if I2C data is cleared. OTF conditions may
also make the OLF flags go HIGH, when high capacitive
loads are present or self-heating conditions occur at higher
loads.
External Output Voltage Selection
The output voltage can be selected by the I2C bus.
Additionally, the package offers two pins (SEL18V1,
SEL18V2) for independent 13V/18V output voltage
selection. When using these pins, the I2C bits should be
initialized to 13V status.
TABLE 1.
I2C BITS
SEL18V (1, 2)
O/P VOLTAGE
13V
Low
13V
14V
Low
14V
13V
High
18V
14V
High
18V
I2C Bus Interface for ISL6424
(Refer to Philips I2C Specification, Rev. 2.1)
Data transmission from main microprocessor to the ISL6424
and vice versa takes place through the two wire I2C bus
interface, consisting of the two lines SDA and SCL. Both SDA
and SCL are bidirectional lines, connected to a positive supply
voltage via a pull up resistor. (Pull up resistors to positive supply
voltage must be externally connected). When the bus is free,
both lines are HIGH. The output stages of ISL6424 will have an
open drain/open collector in order to perform the wired-AND
function. Data on the I2C bus can be transferred up to 100Kbps
FN9175.3
September 13, 2005
ISL6424
in the standard-mode or up to 400Kbps in the fast-mode. The
level of logic “0” and logic “1” is dependent of associated value
of VDD as per electrical specification table. One clock pulse is
generated for each data bit transferred.
Data Validity
The data on the SDA line must be stable during the HIGH
period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is
LOW. Refer to Figure 2.
The peripheral which has been addressed has to generate
an acknowledge after the reception of each byte, otherwise
the SDA line remains at the HIGH level during the ninth
clock pulse time. In this case, the master transmitter can
generate the STOP information in order to abort the transfer.
The ISL6424 will not generate the acknowledge if the
POWER OK signal from the UVLO is LOW.
SCL
2
1
8
9
SDA
SDA
MSB
START
ACKNOWLEDGE
FROM SLAVE
SCL
FIGURE 4. ACKNOWLEDGE ON THE I2C BUS
DATA LINE CHANGE
STABLE
OF DATA
DATA VALID ALLOWED
Transmission Without Acknowledge
FIGURE 2. DATA VALIDITY
START and STOP Conditions
As shown in Figure 3, START condition is a HIGH to LOW
transition of the SDA line while SCL is HIGH.
The STOP condition is a LOW to HIGH transition on the SDA
line while SCL is HIGH. A STOP condition must be sent
before each START condition.
Avoiding detection of the acknowledgement, the
microprocessor can use a simpler transmission; it waits one
clock without checking the slave acknowledging, and sends
the new data.
This approach, though, is less protected from error and
decreases the noise immunity.
ISL6424 Software Description
Interface Protocol
SDA
The interface protocol is comprised of the following, as
shown below in Table 2:
SCL
• A start condition (S)
S
P
START
CONDITION
STOP
CONDITION
FIGURE 3. START AND STOP WAVEFORMS
• A chip address byte (MSB on left; the LSB bit determines
read (1) or write (0) transmission) (the assigned I2C slave
address for the ISL6424 is 0001 00XX)
Byte Format
• A sequence of data (1 byte + Acknowledge)
Every byte put on the SDA line must be eight bits long. The
number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an
acknowledge bit. Data is transferred with the most significant
bit first (MSB).
• A stop condition (P)
TABLE 2. INTERFACE PROTOCOL
S 0
0
0
1
0
0
0 R/W ACK
Data (8 bits)
ACK P
Acknowledge
The master (microprocessor) puts a resistive HIGH level on
the SDA line during the acknowledge clock pulse (Figure 4).
The peripheral that acknowledges has to pull down (LOW)
the SDA line during the acknowledge clock pulse, so that the
SDA line is stable LOW during this clock pulse. (Of course,
set-up and hold times must also be taken into account.)
9
FN9175.3
September 13, 2005
ISL6424
System Register Format
• R, W = Read and Write bit
• R = Read-only bit
• All bits reset to 0 at Power-On
TABLE 3. SYSTEM REGISTER 1 (SR1)
R, W
R, W
R, W
R, W
R, W
R, W
R, W
R
SR1
DCL
ISEL1
ENT1
LLC1
VSEL1
EN1
OLF1
TABLE 4. SYSTEM REGISTER 2 (SR2)
R, W
R, W
R, W
R, W
R, W
R, W
R
R
SR2
ISEL2
ENT2
LLC2
VSEL2
EN2
OTF
OLF2
Transmitted Data (I2C bus WRITE mode)
microprocessor as shown below. The spare bits of SR1/SR2
can be used for other functions.
When the R/W bit in the chip is set to 0, the main
microprocessor can write on the system registers (SR1/SR2)
of the ISL6424 via I2C bus. These will be written by the
TABLE 5. SYSTEM REGISTER (SR1 AND SR2) CONFIGURATION
SR
DCL
ISEL1
ENT1
LLC1
VSEL1
EN1
OLF1
FUNCTION
0
X
X
X
0
0
X
X
SR1 is selected
0
X
X
X
0
0
1
X
Vout1 = 13V, Vboost1 = 13V + Vdrop
0
X
X
X
0
1
1
X
Vout1 = 18V, Vboost1 = 18V + Vdrop
0
X
X
X
1
0
1
X
Vout1 = 14V, Vboost1 = 14V + Vdrop
0
X
X
X
1
1
1
X
Vout1 = 19V, Vboost1 = 19V + Vdrop
0
X
X
0
X
X
1
X
22kHz tone is controlled by DSQIN1 pin
0
X
X
1
X
X
1
X
22kHz tone is ON, DSQIN1 is disabled
0
X
0
X
X
X
1
X
Iout1 = 425mA max.
0
X
1
X
X
X
1
X
Iout1 = 775mA max.
0
1
X
X
X
X
1
X
Dynamic current limit NOT selected
0
0
X
X
X
X
1
X
Dynamic current limit selected
0
X
X
X
X
X
0
X
PWM and Linear for channel 1 disabled
SR
ISEL2
ENT2
LLC2
VSEL2
EN2
OTF
OLF2
1
X
X
X
X
X
X
X
SR2 is selected
1
X
X
0
0
1
X
X
Vout2 = 13V, Vboost2 = 13V + Vdrop
1
X
X
0
1
1
X
X
Vout2 = 18V, Vboost2 = 18V + Vdrop
1
X
X
1
0
1
X
X
Vout2 = 14V, Vboost2 = 14V + Vdrop
1
X
X
1
1
1
X
X
Vout2 = 19V, Vboost2 = 19V + Vdrop
1
X
0
X
X
1
X
X
22kHz tone is controlled by DSQIN2 pin
1
X
1
X
X
1
X
X
22kHz tone is ON, DSQIN2 is disabled
1
0
X
X
X
1
X
X
Iout2 = 425mA max.
1
1
X
X
X
1
X
X
Iout2 = 775mA max.
1
X
X
X
X
0
X
X
PWM and Linear for channel 2 disabled
FUNCTION
NOTE: OTF and OLF1&2 are “Read Only” bits and X is a “Don’t Care” for the function specified.
10
FN9175.3
September 13, 2005
ISL6424
interface will not respond to any I2C commands and the
system register SR1 and SR2 are initialized to all zeros, thus
keeping the power blocks disabled. Once the Vcc rises
above UVLO, the POWER OK signal given to the I2C
interface block will be HIGH, the I2C interface becomes
operative and the SRs can be configured by the main
microprocessor. About 400mV of hysteresis is provided in
the UVLO threshold to avoid false triggering of the PowerOn reset circuit. (I2C comes up with EN = 0; EN goes HIGH
at the same time as (or later than) all other I2C data for that
PWM becomes valid).
Received Data (I2C bus READ MODE)
The ISL6424 can provide to the master a copy of the system
register information via the I2C bus in read mode. The read
mode is Master activated by sending the chip address with
R/W bit set to 1. At the following Master generated clock bits,
the ISL6424 issues a byte on the SDA data bus line (MSB
transmitted first).
At the ninth clock bit the MCU master can:
• Acknowledge the reception, starting in this way the
transmission of another byte from the ISL6424.
ADDRESS Pin
• Not acknowledge, stopping the read mode
communication.
While the whole register is read back by the microprocessor,
the read-only bits OLF1, OLF2, and OTF convey diagnostic
information about the ISL6424.
Connecting this pin to GND the chip I2C interface address is
0001000, but, it is possible to choose between two different
addresses simply by setting this pin at one of the two fixed
voltage levels as shown in Table 8.
TABLE 6. ADDRESS PIN CHARACTERISTICS
Power-On I2C Interface Reset
The I2C interface built into the ISL6424 is automatically reset
at power-on. The I2C interface block will receive a Power OK
logic signal from the UVLO circuit. This signal will go HIGH
when chip power is OK. As long as this signal is LOW, the
VADDR
MINIMUM
TYPICAL
MAXIMUM
VADDR-1
“0001000”
0V
-
2V
VADDR-2
“0001001”
2.7V
-
5V
TABLE 7. READING SYSTEM REGISTERS
DCL
ISEL1/2
ENT1/2
LLC1/2
VSEL1/1
EN1/2
These bits are read as they were after the last write operation.
OTF2
OLF1/2
FUNCTION
0
TJ ≤ 130°C, normal operation
1
TJ > 150°C, power blocks disabled
0
IOUT < IMAX, normal operation
1
IOUT > IMAX, overload protection triggered
I2C Electrical Characteristics
TABLE 8. I2C SPECIFICATIONS
PARAMETER
TEST CONDITION
MINIMUM
TYPICAL
Input Logic High, VIH
SDA, SCL
0.7 x VDD
Input Logic Low, VIL
SDA, SCL
0.3 x VDD
Input Logic Current, IIL
SDA, SCL;
0.4V < VIN < 4.5V
SCL Clock Frequency
10µA
0
11
MAXIMUM
100kHz
400kHz
FN9175.3
September 13, 2005
ISL6424
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L32.5x5
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VHHD-2 ISSUE C
MILLIMETERS
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
0.80
0.90
1.00
-
A1
-
-
0.05
-
A2
-
-
1.00
A3
b
0.18
D
0.23
9
0.30
5,8
5.00 BSC
D1
D2
9
0.20 REF
-
4.75 BSC
2.95
3.10
9
3.25
7,8
E
5.00 BSC
-
E1
4.75 BSC
9
E2
2.95
e
3.10
3.25
7,8
0.50 BSC
-
k
0.25
-
-
-
L
0.30
0.40
0.50
8
L1
-
-
0.15
10
N
32
Nd
2
8
3
Ne
8
8
3
P
-
-
0.60
9
θ
-
-
12
9
Rev. 1 10/02
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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12
FN9175.3
September 13, 2005
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