DATASHEET

HIP6602
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6014
(ISL6
®
Dual Channel Synchronous-Rectified
Buck MOSFET Driver
The HIP6602 is a high frequency, two power channel
MOSFET driver specifically designed to drive four power
N-Channel MOSFETs in a synchronous-rectified buck
converter topology. These drivers combined with a HIP63xx
series of Multi-Phase Buck PWM controller and Intersil’s
UltraFETs® form a complete core voltage regulator solution
for advanced microprocessors.
The HIP6602 drives both upper and lower gates over a
range of 5V to 12V. This drive-voltage flexibility provides the
advantage of optimizing applications involving trade-offs
between switching losses and conduction losses.
The output drivers in the HIP6602 have the capacity to
efficiently switch power MOSFETs at high frequencies. Each
driver is capable of driving a 3000pF load with a 30ns
propagation delay and 50ns transition time. This device
implements bootstrapping on the upper gates with only a
single external capacitor required for each power channel.
This reduces implementation complexity and allows the use
of higher performance, cost effective, N-Channel MOSFETs.
Adaptive shoot-through protection is integrated to prevent
both MOSFETs from conducting simultaneously.
August 2000
Features
• Drives Four N-channel MOSFETs
• Adaptive Shoot-Through Protection
• Internal Bootstrap Devices
• Supports High Switching Frequency
- Fast Output Rise Time
- Propagation Delay 30ns
• Small 14-Lead SOIC Package
• 5V to 12V Gate-Drive Voltages for Optimal Efficiency
• Three-State Input for Bridge Shutdown
• Supply Under-Voltage Protection
Applications
• Core Voltage Supplies for Intel Pentium® III and AMD®
AthlonTM Microprocessors.
• High Frequency Low Profile DC/DC Converters
• High Current Low Voltage DC/DC Converters
Pinout
HIP6602CB
(SOIC)
TOP VIEW
Ordering Information
PART NUMBER
HIP6602CB
HIP6602CB-T
TEMP. RANGE
(°C)
0 to 85
PACKAGE
14 Ld SOIC
14 Ld SOIC Tape and Reel
1
PKG. NO.
M14.15
FN4838.1
PWM1
1
14 VCC
PWM2
2
13 PHASE1
GND
3
12 UGATE1
LGATE1 4
11 BOOT1
PVCC
5
10 BOOT2
PGND
6
9 UGATE2
LGATE2
7
8 PHASE2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright © Intersil Corporation 2000, 2005
Pentium® is a registered trademark of Intel Corporation.; AMD® is a registered trademark of Advanced Micro Devices, Inc.
UltraFET® is a registered trademark of Intersil Corporation. Athlon™ is a trademark of Advanced Micro Devices, Inc.
HIP6602
Block Diagram
PVCC
BOOT1
UGATE1
VCC
+5V
SHOOTTHROUGH
PROTECTION
10K
PWM1
PHASE1
PVCC
LGATE1
10K
PGND
CONTROL
LOGIC
+5V
PGND
PVCC
BOOT2
10K
UGATE2
PWM2
SHOOTTHROUGH
PROTECTION
10K
GND
PHASE2
PVCC
LGATE2
HIP6602
PGND
Typical Application - 2 Channel Converter Using a HIP6302 and a HIP6602 Gate Driver
+5V
BOOT1
+12V
+12V
FB
UGATE1
COMP
VCC
VCC
VSEN
PHASE1
ISEN1
PGOOD
PWM1
VID
DUAL
DRIVER
HIP6602
MAIN
CONTROL
HIP6302
PWM2
FS/DIS
LGATE1
PWM1
PVCC
BOOT2
PWM2
UGATE2
PHASE2
ISEN2
LGATE2
GND
GND
2
PGND
+VCORE
+5V/12V
+12V
HIP6602
Typical Application - 4 Channel Converter Using a HIP6303 and HIP6602 Gate Driver
+12V
BOOT1
+12V
UGATE1
VCC
PHASE1
LGATE1
+5V
DUAL
DRIVER
HIP6602
FB
PVCC
+5V/12V
BOOT2
COMP
+12V
VCC
VSEN
UGATE2
ISEN1
PGOOD
PWM1
EN
PWM2
PHASE2
PWM1
PWM2
LGATE2
ISEN2
VID
MAIN
CONTROL
HIP6303
GND
PGND
+VCORE
ISEN3
FS/DIS
PWM3
PWM4
GND
BOOT3
+12V
+12V
ISEN4
UGATE3
VCC
PHASE3
LGATE3
DUAL
DRIVER
HIP6602
PVCC
+5V/12V
BOOT4
UGATE4
PWM3
PHASE4
PWM4
LGATE4
GND
3
PGND
+12V
HIP6602
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V
Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3V
BOOT Voltage (VBOOT - VPHASE) . . . . . . . . . . . . . . . . . . . . . . .15V
Input Voltage (VPWM) . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 7V
UGATE. . . . . . . . . . . . . . . . . . . . . . VPHASE - 0.3V to VBOOT + 0.3V
LGATE . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to VPVCC + 0.3V
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . .3kV
Machine Model (Per EIAJ ED-4701 Method C-111) . . . . . . .200V
Thermal Resistance (Note 1)
θJA (°C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
68
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
Operating Conditions
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . 0°C to 85°C
Maximum Operating Junction Temperature. . . . . . . . . . . . . . . 125°C
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V ±10%
Supply Voltage Range PVCC . . . . . . . . . . . . . . . . . . . . . 5V to 12V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VCC SUPPLY CURRENT
Bias Supply Current
IVCC
fPWM = 500kHz, VPVCC = 12V
-
3.7
5.0
mA
Power Supply Current
IPVCC
fPWM = 500kHz, VPVCC = 12V
-
2.0
4.0
mA
VCC Rising Threshold
9.7
9.95
10.4
V
VCC Falling Threshold
9.0
9.2
9.5
V
-
500
-
µA
POWER-ON RESET
PWM INPUT
Input Current
IPWM
VPWM = 0 or 5V (See Block Diagram)
PWM Rising Threshold
VPVCC = 12V
3.45
3.6
-
V
PWM Falling Threshold
VPVCC = 12V
-
1.45
1.55
V
TRUGATE
VPVCC = VVCC = 12V, 3nF Load
-
20
-
ns
LGATE Rise Time
TRLGATE
VPVCC = VVCC = 12V, 3nF Load
-
50
-
ns
UGATE Fall Time
TFUGATE
VPVCC = VVCC = 12V, 3nF Load
-
20
-
ns
LGATE Fall Time
TFLGATE
VPVCC = VVCC = 12V, 3nF Load
-
20
-
ns
UGATE Turn-Off Propagation Delay
TPDLUGATE VPVCC = VVCC = 12V, 3nF Load
-
30
-
ns
LGATE Turn-Off Propagation Delay
TPDLLGATE VPVCC = VVCC = 12V, 3nF Load
-
20
-
ns
1.4
-
3.6
V
-
230
-
ns
UGATE Rise Time
Shutdown Window
Shutdown Holdoff Time
OUTPUT
Upper Drive Source Impedance
RUGATE
VVCC = 12V, VPVCC = 5V
-
1.7
3.0
Ω
VVCC = VPVCC = 12V
-
3.0
5.0
Ω
VVCC = 12V, VPVCC = 5V
-
2.3
4.0
Ω
Upper Drive Sink Impedance
RUGATE
-
1.1
2.0
Ω
Lower Drive Source Current
ILGATE
VVCC = 12V, VPVCC = 5V
400
580
-
mA
VVCC = VPVCC = 12V
500
730
-
mA
Lower Drive Sink Impedance
RLGATE
VVCC = 12V, VPVCC = 5V or 12V
-
1.6
4.0
Ω
VVCC = VPVCC = 12V
4
HIP6602
Functional Pin Descriptions
PWM1 (Pin 1) and PWM2 (Pin 2)
The PWM signal is the control input for the driver. The PWM
signal can enter three distinct states during operation, see the
three-state PWM Input section under DESCRIPTION for further
details. Connect this pin to the PWM output of the controller.
GND (Pin 3)
Bias and reference ground. All signals are referenced to this
node.
PHASE pin. The bootstrap capacitor provides the charge to
turn on the upper MOSFETs. See the Internal Bootstrap
Device section under DESCRIPTION for guidance in
choosing the appropriate capacitor value.
VCC (Pin 14)
Connect this pin to a +12V bias supply. Place a high quality
bypass capacitor from this pin to GND. To prevent forward
biasing an internal diode, this pin should be more positive
then PVCC during converter start-up.
Description
LGATE1 (Pin 4) and LGATE2 (Pin 7)
Lower gate drive outputs. Connect to gates of the low-side
power N-Channel MOSFETs.
PVCC (Pin 5)
This pin supplies the upper and lower gate drivers bias.
Connect this pin from +12V down to +5V.
PGND (Pin 6)
This pin is the power ground return for the lower gate
drivers.
PHASE2 (Pin 8) and PHASE1 (Pin 13)
Connect these pins to the source of the upper MOSFETs
and the drain of the lower MOSFETs. The PHASE voltage is
monitored for adaptive shoot-through protection. These pins
also provide a return path for the upper gate drive.
UGATE2 (Pin 9) and UGATE1 (Pin 12)
Upper gate drive outputs. Connect to gate of high-side
power N-Channel MOSFETs.
Operation
Designed for versatility and speed, the HIP6602 two channel,
dual MOSFET driver controls both high-side and low-side
N-Channel FETs from two externally provided PWM signals.
The upper and lower gates are held low until the driver is
initialized. Once the VCC voltage surpasses the VCC Rising
Threshold (See Electrical Specifications), the PWM signal
takes control of gate transitions. A rising edge on PWM
initiates the turn-off of the lower MOSFET (see Timing
Diagram). After a short propagation delay [TPDLLGATE], the
lower gate begins to fall. Typical fall times [TFLGATE] are
provided in the Electrical Specifications section. Adaptive
shoot-through circuitry monitors the LGATE voltage and
determines the upper gate delay time [TPDHUGATE] based
on how quickly the LGATE voltage drops below 1.0V. This
prevents both the lower and upper MOSFETs from
conducting simultaneously or shoot-through. Once this delay
period is complete the upper gate drive begins to rise
[TRUGATE] and the upper MOSFET turns on.
BOOT 2 (Pin 10) and BOOT 1 (Pin 11)
Floating bootstrap supply pins for the upper gate drivers.
Connect the bootstrap capacitor between these pins and the
Timing Diagram
PWM
TPDHUGATE
TPDLUGATE
TRUGATE
TFUGATE
UGATE
LGATE
TRLGATE
TFLGATE
TPDLLGATE
TPDHLGATE
5
HIP6602
A falling transition on PWM indicates the turn-off of the
upper MOSFET and the turn-on of the lower MOSFET. A
short propagation delay [TPDLUGATE] is encountered
before the upper gate begins to fall [TFUGATE]. Again, the
adaptive shoot-through circuitry determines the lower gate
delay time, TPDHLGATE. The PHASE voltage is monitored
and the lower gate is allowed to rise after PHASE drops
below 0.5V. The lower gate then rises [TRLGATE], turning
on the lower MOSFET.
Three-State PWM Input
A unique feature of the HIP6602 drivers is the addition of a
shutdown window to the PWM input. If the PWM signal
enters and remains within the shutdown window for a set
holdoff time, the output drivers are disabled and both
MOSFET gates are pulled and held low. The shutdown state
is removed when the PWM signal moves outside the
shutdown window. Otherwise, the PWM rising and falling
thresholds outlined in the ELECTRICAL SPECIFICATIONS
determine when the lower and upper gates are enabled.
Adaptive Shoot-Through Protection
The drivers incorporate adaptive shoot-through protection to
prevent upper and lower MOSFETs from conducting
simultaneously and shorting the input supply. This is
accomplished by ensuring the falling gate has turned off one
MOSFET before the other is allowed to rise.
During turn-off of the lower MOSFET, the LGATE voltage is
monitored until it reaches a 1.0V threshold, at which time the
UGATE is released to rise. Adaptive shoot-through circuitry
monitors the PHASE voltage during UGATE turn-off. Once
PHASE has dropped below a threshold of 0.5V, the LGATE
is allowed to rise. If the PHASE does not drop below 0.5V
within 250ns, LGATE is allowed to rise. This is done to
generate the bootstrap refresh signal. PHASE continues to
be monitored during the lower gate rise time. If the PHASE
voltage exceeds the 0.5V threshold during this period and
remains high for longer than 2µs, the LGATE transitions low.
This is done to make the lower MOSFET emulate a diode.
Both upper and lower gates are then held low until the next
rising edge of the PWM signal.
Power-On Reset (POR) Function
During initial start-up, the VCC voltage rise is monitored and
gate drives are held low until a typical VCC rising threshold
of 9.95V is reached. Once the rising VCC threshold is
exceeded, the PWM input signal takes control of the gate
drives. If VCC drops below a typical VCC falling threshold of
9.2V during operation, then both gate drives are again held
low. This condition persists until the VCC voltage exceeds
the VCC rising threshold.
Internal Bootstrap Device
Both drivers feature an internal bootstrap device. Simply
adding an external capacitor across the BOOT and PHASE
pins completes the bootstrap circuit.
6
The bootstrap capacitor must have a maximum voltage
rating above PVCC + 5V. The bootstrap capacitor can be
chosen from the following equation:
Q GATE
C BOOT ≥ -----------------------∆V BOOT
Where QGATE is the amount of gate charge required to fully
charge the gate of the upper MOSFET. The ∆VBOOT term is
defined as the allowable droop in the rail of the upper drive.
As an example, suppose a HUF76139 is chosen as the
upper MOSFET. The gate charge, QGATE , from the data
sheet is 65nC for a 10V upper gate drive. We will assume a
200mV droop in drive voltage over the PWM cycle. We find
that a bootstrap capacitance of at least 0.325µF is required.
The next larger standard value capacitance is 0.33µF.
Gate Drive Voltage Versatility
The HIP6602 provides the user flexibility in choosing the
gate drive voltage. Simply applying a voltage from 5V up to
12V on PVCC will set both driver rail voltages.
Power Dissipation
Package power dissipation is mainly a function of the switching
frequency and total gate charge of the selected MOSFETs.
Calculating the power dissipation in the driver for a desired
application is critical to ensuring safe operation. Exceeding the
maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
temperature of 125°C. The maximum allowable IC power
dissipation for the 14 lead SOIC package is approximately
1000mW. Improvements in thermal transfer may be gained by
increasing the PC board copper area around the HIP6602.
Adding a ground pad under the IC to help transfer heat to the
outer peripheral of the board will help. Also keeping the leads to
the IC as wide as possible and widening this these leads as
soon as possible to further enhance heat transfer will also help.
When designing the driver into an application, it is
recommended that the following calculation be performed to
ensure safe operation at the desired frequency for the
selected MOSFETs. The total chip power dissipation is
approximated as:
3 (Q + Q ) + (Q + Q )] + I
P = 1.05 x fSW x VPVCC [_
U2
L1
L2
DDQ x VCC
2 U1
where fsw is the switching frequency of the PWM signal. QU
and QL is the upper and lower gate charge determined by
MOSFET selection and any external capacitance added to
the gate pins. The IDDQ VCC product is the quiescent power
of the driver and is typically 40mW.
The 1.05 term is a correction factor derived from the
following characterization. The base circuit for characterizing
the drivers for different loading profiles and frequencies is
provided. CU and CL are the upper and lower gate load
capacitors. Decoupling capacitors [0.15µF] are added to the
HIP6602
PVCC and VCC pins. The bootstrap capacitor value in the
test circuit is 0.01µF.
The power dissipation approximation is a result of power
transferred to and from the upper and lower gates. But, the
internal bootstrap device also dissipates power on-chip
during the refresh cycle. Expressing this power in terms of
the upper MOSFET total gate charge is explained below.
tied together and to a +12V supply. Figures 5 through 7
show the same characterization for PVCC tied to +5V
instead of +12V. The gate supply voltage, PVCC, within the
HIP6602 sets both upper and lower gate driver supplies at
the same 5V level for the last three curves.
Test Circuit
+5V OR +12V
The bootstrap device conducts when the lower MOSFET or
its body diode conducts and pulls the PHASE node toward
GND. While the bootstrap device conducts, a current path is
formed that refreshes the bootstrap capacitor. Since the
upper gate is driving a MOSFET, the charge removed from
the bootstrap capacitor is equivalent to the total gate charge
of the MOSFET. Therefore, the refresh power required by
the bootstrap capacitor is equivalent to the power used to
charge the gate capacitance of the upper MOSFETs.
+12V
+5V OR +12V
0.01µF
BOOT1
PVCC
2N7002
0.15µF
UGATE1
CU
PHASE1
VCC
0.15µF
LGATE1
PWM1
HIP6602
PGND
where QLOSS is the total charge removed from the bootstrap
capacitors and provided to the upper gate loads.
100kΩ
2N7002
CL
P REFRESH = f SW Q
V
= f SW Q V
LOSS PVCC
U PVCC
0.01µF
BOOT2
GND
2N7002
In Figure 1, CU and CL values are the same and frequency
is varied from 10kHz to 2MHz. PVCC and VCC are tied
together to a +12V supply.
UGATE2
CU
PHASE2
PWM2
Figure 2 shows the dissipation in the driver with 1nF loading
on both gates and each individually. Figure 3 is the same as
Figure 2 except the capacitance is increased to 3nF.
LGATE2
100kΩ
2N7002
CL
The impact of loading on power dissipation is shown in
Figure 4. Frequency is held constant while the gate
capacitors are varied from 1nF to 5nF. VCC and PVCC are
Typical Performance Curves
1200
1200
CU = C L
= 5nF
PVCC = VCC = 12V
1000
CU = C L
= 4nF
800
CU = C L
= 3nF
600
CU = CL = 2nF
400
CU = CL = 1nF
PVCC = 12V
VCC = 12V
POWER (mW)
POWER (mW)
1000
800
CL = 1nF, CU = 0nF
600
400
CU = 1nF, CL = 0nF
CU = CL = 1nF
200
200
0
0
0
500
1000
FREQUENCY (kHz)
FIGURE 1. POWER DISSIPATION vs FREQUENCY
7
1500
0
500
1000
1500
FREQUENCY (kHz)
FIGURE 2. 1nF LOADING PROFILE
2000
HIP6602
Typical Performance Curves
(Continued)
1200
1200
PVCC = VCC = 12V
PVCC = VCC = 12V
1000
1000
500kHz
POWER (mW)
POWER (mW)
CU = CL = 3nF
800
600
CU = 3nF, CL = 0nF
CL = 3nF, CU = 0nF
400
800
600
200kHz
400
100kHz
10kHz
200
200
30kHz
0
0
0
500
1
1500
1000
2
FIGURE 3. 3nF LOADING PROFILE
4
5
FIGURE 4. POWER DISSIPATION vs LOADING
350
800
PVCC = 5V, VCC = 12V
PVCC = 5V, VCC = 12V
CU = CL = 5nF
700
300
CU = CL = 4nF
600
CU = CL = 1nF
CU = CL = 3nF
250
500
POWER (mW)
POWER (mW)
3
GATE CAPACITANCE (CU = CL ), (nF)
FREQUENCY (kHz)
400
300
150
CU = 1nF, CL = 0nF
100
CU = CL = 2nF
200
CL = 1nF, CU = 0nF
200
CU = CL =1nF
50
100
0
0
500
1000
FREQUENCY (kHz)
1500
2000
FIGURE 5. POWER DISSIPATION vs FREQUENCY, PVCC = 5V
0
0
500
1000
FREQUENCY (kHz)
PVCC = 5V,
VCC = 12V
500
1.5MHz
POWER (mW)
1MHz
400
300
500kHz
200
100kHz
200kHz
100
0
30kHz
1
2
3
4
GATE CAPACITANCE (CU = CL), (nF)
FIGURE 7. POWER DISSIPATION vs LOADING, PVCC = 5V
8
2000
FIGURE 6. POWER DISSIPATION vs FREQUENCY, PVCC = 5V
600
2MHz
1500
5
HIP6602
Small Outline Plastic Packages (SOIC)
M14.15 (JEDEC MS-012-AB ISSUE C)
N
INDEX
AREA
H
0.25(0.010) M
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
B M
E
INCHES
-B-
1
2
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
e
α
A1
B
0.25(0.010) M
C A M
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.3367
0.3444
8.55
8.75
3
E
0.1497
0.1574
3.80
4.00
4
e
C
0.10(0.004)
B S
0.050 BSC
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
N
NOTES:
MILLIMETERS
α
14
0o
14
8o
0o
7
8o
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
9
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