DATASHEET

NS
W DESIG
E
N
R
O
NDED F
S:
C OMM E R E C O MME N D
E
,
R
T
O
N
IL
L6613A
S
IS
R
,
INTE
Data
Sheet
6613
L
A
IS
5
,
2
A
6
2
6
, ISL661
622, ISL
ISL6612
4A, ISL6
1
6
6
L
IS
,
ISL6614
Dual Channel Synchronous Rectified
Buck MOSFET Driver
The output drivers in the HIP6602B have the capacity to
efficiently switch power MOSFETs at high frequencies. Each
driver is capable of driving a 3000pF load with a 30ns
propagation delay and 50ns transition time. This device
implements bootstrapping on the upper gates with a single
external capacitor and resistor required for each power
channel. This reduces implementation complexity and allows
the use of higher performance, cost effective, N-Channel
MOSFETs. Adaptive shoot-through protection is integrated
to prevent both MOSFETs from conducting simultaneously.
Ordering Information
HIP6602BCB
HIP6602BCB-T
HIP6602BCBZ (Note 1)
HIP6602BCBZ-T (Note 1)
HIP6602BCR
HIP6602BCR-T
HIP6602BCRZ (Note 1)
HIP6602BCRZ-T (Note 1)
HIP6602BCRZA (Note 1)
0 to 85
PACKAGE
14 Ld SOIC
FN9076.6
• Drives Four N-Channel MOSFETs
The HIP6602B drives both upper and lower gates over a
range of 5V to 12V. This drive-voltage flexibility provides the
advantage of optimizing applications involving trade-offs
between switching losses and conduction losses.
TEMP.
RANGE (°C)
December 3, 2015
Features
The HIP6602B is a high frequency, two power channel
MOSFET driver specifically designed to drive four power
N-Channel MOSFETs in a synchronous rectified buck
converter topology. This device is available in either a
14-lead SOIC or a 16-lead QFN package with a PAD to
thermally enhance the package. These drivers combined
with a HIP63xx or ISL65xx series of Multi-Phase Buck PWM
controllers and MOSFETs form a complete core voltage
regulator solution for advanced microprocessors.
PART NUMBER
HIP6602B
PKG.
DWG. #
M14.15
• Adaptive Shoot-Through Protection
• Internal Bootstrap Devices
• Supports High Switching Frequency
- Fast Output Rise Time
- Propagation Delay 30ns
• Small 14-Lead SOIC Package
• Smaller 16-Lead QFN Thermally Enhanced Package
• 5V to 12V Gate-Drive Voltages for Optimal Efficiency
• Three-State Input for Bridge Shutdown
• Supply Undervoltage Protection
• Pb-Free Plus Anneal Available (RoHS Compliant)
• QFN Package:
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
Applications
• Core Voltage Supplies for Intel Pentium® III and AMD®
AthlonTM Microprocessors.
• High-Frequency, Low-Profile DC/DC Converters
• High-Current, Low-Voltage DC/DC Converters
14 Ld SOIC Tape and Reel
0 to 85
14 Ld SOIC
(Pb-Free)
M14.15
14 Ld SOIC Tape and Reel (Pb-Free)
0 to 85
16 Ld 5x5 QFN
L16.5x5
16 Ld 5x5 QFN Tape and Reel
0 to 85
16 Ld 5x5 QFN
(Pb-Free)
L16.5x5
16 Ld 5x5 QFN Tape and Reel (Pb-Free)
0 to 85
16 Ld 5x5 QFN
(Pb-Free)
L16.5x5
HIP6602BCRZA-T (Note 1) 16 Ld 5x5 QFN Tape and Reel (Pb-Free)
NOTE:
1. Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2002-2005, 2015. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HIP6602B
Pinouts
14 VCC
PWM2
2
13 PHASE1
GND
3
12 UGATE1
LGATE1
4
11 BOOT1
PVCC
5
10 BOOT2
PGND
6
LGATE2
7
PHASE1
1
VCC
PWM1
PWM1
HIP6602 (16 LD QFN)
TOP VIEW
PWM2
HIP6602B (SOIC)
TOP VIEW
16
15
14
13
11 BOOT1
9 UGATE2
PVCC 3
10 BOOT2
8 PHASE2
PGND 4
9
NC
5
6
7
8
NC
LG1 2
PHASE2
12 UG1
LG2
GND 1
UG2
Block Diagram
PVCC
BOOT1
UGATE1
VCC
+5V
SHOOTTHROUGH
PROTECTION
10K
PWM1
PHASE1
PVCC
LGATE1
10K
PGND
CONTROL
LOGIC
+5V
PGND
PVCC
BOOT2
10K
UGATE2
PWM2
SHOOTTHROUGH
PROTECTION
10K
GND
PHASE2
PVCC
LGATE2
HIP6602B
PGND
PAD
2
For HIP6602BCR, the PAD on the bottom side of the
package MUST be soldered to the PC board
FN9076.6
December 3, 2015
HIP6602B
Typical Application - 2 Channel Converter Using a HIP6302 and a HIP6602B Gate Driver
+5V
BOOT1
+12V
FB
+12V
UGATE1
COMP
VCC
VCC
VSEN
PHASE1
ISEN1
PGOOD
VID
PWM1
DUAL
DRIVER
HIP6602B
MAIN
CONTROL
HIP6302
PVCC
+VCORE
+5V/12V
BOOT2
PWM2
PWM2
+12V
UGATE2
PHASE2
ISEN2
FS/DIS
LGATE1
PWM1
LGATE2
GND
GND
3
PGND
FN9076.6
December 3, 2015
HIP6602B
Typical Application - 4 Channel Converter Using a HIP6303 and HIP6602B Gate Driver
+12V
BOOT1
+12V
UGATE1
VCC
PHASE1
LGATE1
+5V
DUAL
DRIVER
HIP6602B
+5V/12V
BOOT2
COMP
FB
PVCC
+12V
VCC
VSEN
UGATE2
ISEN1
PGOOD
PWM1
EN
PWM2
VID
MAIN ISEN2
CONTROL
HIP6303
PHASE2
PWM1
PWM2
LGATE2
GND
PGND
+VCORE
ISEN3
FS/DIS
PWM3
PWM4
GND
BOOT3
+12V
+12V
ISEN4
UGATE3
VCC
PHASE3
LGATE3
DUAL
DRIVER
HIP6602B
PVCC
BOOT4
+5V/12V
+12V
UGATE4
PWM3
PHASE4
PWM4
LGATE4
GND
4
PGND
FN9076.6
December 3, 2015
HIP6602B
Absolute Maximum Ratings
Operating Conditions
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V
Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3V
BOOT Voltage (VBOOT - VPHASE) . . . . . . . . . . . . . . . . . . . . . . .15V
Input Voltage (VPWM) . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 7V
UGATE. . . . . . .VPHASE - 5V(<400ns pulse width) to VBOOT + 0.3V
VPHASE -0.3V(>400ns pulse width) to VBOOT + 0.3V
LGATE . . . . . . . . . GND - 5V(<400ns pulse width) to VPVCC + 0.3V
GND -0.3V(>400ns pulse width) to VPVCC + 0.3V
PHASE. . . . . . . . . . . . . . . . . . GND -5V(<400ns pulse width) to 15V
GND -0.3V(>400ns pulse width) to 15V
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . .3kV
Machine Model (Per EIAJ ED-4701 Method C-111) . . . . . . . .200V
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . 0°C to 85°C
Maximum Operating Junction Temperature. . . . . . . . . . . . . . . 125°C
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V 10%
Supply Voltage Range PVCC . . . . . . . . . . . . . . . . . . . . . 5V to 12V
Thermal Information
JA (°C/W) JC (°C/W)
Thermal Resistance
SOIC Package (Note 2) . . . . . . . . . . . .
68
N/A
QFN Package (Note 3). . . . . . . . . . . . .
36
6
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
For Recommended soldering conditions see Tech Brief TB389.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
2. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. JC, the
“case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Electrical Specifications
Recommended Operating Conditions, unless otherwise specified.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VCC SUPPLY CURRENT
Bias Supply Current
IVCC
fPWM = 500kHz, VPVCC = 12V
-
3.7
5.0
mA
Power Supply Current
IPVCC
fPWM = 500kHz, VPVCC = 12V
-
2.0
4.0
mA
VCC Rising Threshold
9.7
9.95
10.4
V
VCC Falling Threshold
7.3
7.6
8.0
V
VPWM = 0 or 5V (See Block Diagram)
-
500
-
µA
VPVCC = 12V
-
3.6
-
V
POWER-ON RESET
PWM INPUT
Input Current
IPWM
PWM Rising Threshold
PWM Falling Threshold
VPVCC = 12V
-
1.45
-
V
UGATE Rise Time
TRUGATE
VPVCC = VVCC = 12V, 3nF Load
-
20
-
ns
LGATE Rise Time
TRLGATE
VPVCC = VVCC = 12V, 3nF Load
-
50
-
ns
UGATE Fall Time
TFUGATE
VPVCC = VVCC = 12V, 3nF Load
-
20
-
ns
LGATE Fall Time
TFLGATE
VPVCC = VVCC = 12V, 3nF Load
-
20
-
ns
UGATE Turn-Off Propagation Delay
TPDLUGATE VPVCC = VVCC = 12V, 3nF Load
-
30
-
ns
LGATE Turn-Off Propagation Delay
TPDLLGATE VPVCC = VVCC = 12V, 3nF Load
-
20
-
ns
1.4
-
3.6
V
-
230
-
ns
Shutdown Window
Shutdown Holdoff Time
OUTPUT
Upper Drive Source Impedance
RUGATE
Upper Drive Sink Impedance
RUGATE
Lower Drive Source Current
ILGATE
VVCC = 12V, VPVCC = 5V
-
1.7
3.0

VVCC = VPVCC = 12V
-
3.0
5.0

VVCC = 12V, VPVCC = 5V
-
2.3
4.0

-
1.1
2.0

VVCC = 12V, VPVCC = 5V
400
580
-
mA
VVCC = VPVCC = 12V
500
730
-
mA
-
1.6
4.0

VVCC = VPVCC = 12V
Lower Drive Sink Impedance
RLGATE
5
VVCC = 12V, VPVCC = 5V or 12V
FN9076.6
December 3, 2015
HIP6602B
Functional Pin Descriptions
PWM1 (Pin 1) and PWM2 (Pin 2), (Pins 15 and 16
QFN)
The PWM signal is the control input for the driver. The PWM
signal can enter three distinct states during operation, see the
three-state PWM Input section under DESCRIPTION for further
details. Connect this pin to the PWM output of the controller.
GND (Pin 3), (Pin 1 QFN)
Bias and reference ground. All signals are referenced to
this node.
LGATE1 (Pin 4) and LGATE2 (Pin 7), (Pins 2 and
6 QFN)
Lower gate drive outputs. Connect to gates of the low-side
power N-Channel MOSFETs.
BOOT 2 (Pin 10) and BOOT 1 (Pin 11), (Pins 10 and
11 QFN)
Floating bootstrap supply pins for the upper gate drivers.
Connect a bootstrap capacitor between these pins and the
corresponding PHASE pin. The bootstrap capacitor provides
the charge to turn on the upper MOSFETs. A resistor in
series with boot capacitor is required in certain applications
to reduce ringing on the BOOT pin. See the Internal
Bootstrap Device section under DESCRIPTION for guidance
in choosing the appropriate resistor and capacitor value.
VCC (Pin 14), (Pin 14 QFN)
Connect this pin to a +12V bias supply. Place a high quality
bypass capacitor from this pin to GND. To prevent forward
biasing an internal diode, this pin should be more positive
then PVCC during converter start-up
PVCC (Pin 5), (Pin 3 QFN)
Description
This pin supplies the upper and lower gate drivers bias.
Connect this pin from +12V down to +5V.
Operation
PGND (Pin 6), (Pin 4 QFN)
This pin is the power ground return for the lower gate
drivers.
PHASE2 (Pin 8) and PHASE1 (Pin 13), (Pins 7 and
13 QFN)
Connect these pins to the source of the upper MOSFETs
and the drain of the lower MOSFETs. The PHASE voltage is
monitored for adaptive shoot-through protection. These pins
also provide a return path for the upper gate drive.
UGATE2 (Pin 9) and UGATE1 (Pin 12), (Pins 9 and
12 QFN)
Upper gate drive outputs. Connect to gate of high-side
power N-Channel MOSFETs.
Designed for versatility and speed, the HIP6602B two channel,
dual MOSFET driver controls both high-side and low-side
N-Channel FETs from two externally provided PWM signals.
The upper and lower gates are held low until the driver is
initialized. Once the VCC voltage surpasses the VCC Rising
Threshold (See Electrical Specifications), the PWM signal
takes control of gate transitions. A rising edge on PWM
initiates the turn-off of the lower MOSFET (see Timing
Diagram). After a short propagation delay [TPDLLGATE], the
lower gate begins to fall. Typical fall times [TFLGATE] are
provided in the Electrical Specifications section. Adaptive
shoot-through circuitry monitors the LGATE voltage and
determines the upper gate delay time [TPDHUGATE] based
on how quickly the LGATE voltage drops below 2.2V. This
prevents both the lower and upper MOSFETs from
conducting simultaneously or shoot-through. Once this delay
period is complete the upper gate drive begins to rise
[TRUGATE] and the upper MOSFET turns on.
Timing Diagram.
PWM
TPDHUGATE
TPDLUGATE
TRUGATE
TFUGATE
UGATE
LGATE
TRLGATE
TFLGATE
TPDLLGATE
TPDHLGATE
6
FN9076.6
December 3, 2015
HIP6602B
A falling transition on PWM indicates the turn-off of the
upper MOSFET and the turn-on of the lower MOSFET. A
short propagation delay [TPDLUGATE] is encountered
before the upper gate begins to fall [TFUGATE]. Again, the
adaptive shoot-through circuitry determines the lower gate
delay time, TPDHLGATE. The PHASE voltage is monitored
and the lower gate is allowed to rise after PHASE drops
below 0.5V. The lower gate then rises [TRLGATE], turning
on the lower MOSFET.
Three-State PWM Input
A unique feature of the HIP6602B drivers is the addition of a
shutdown window to the PWM input. If the PWM signal
enters and remains within the shutdown window for a set
holdoff time, the output drivers are disabled and both
MOSFET gates are pulled and held low. The shutdown state
is removed when the PWM signal moves outside the
shutdown window. Otherwise, the PWM rising and falling
thresholds outlined in the Electrical Specifications determine
when the lower and upper gates are enabled.
Adaptive Shoot-Through Protection
The drivers incorporate adaptive shoot-through protection to
prevent upper and lower MOSFETs from conducting
simultaneously and shorting the input supply. This is
accomplished by ensuring the falling gate has turned off one
MOSFET before the other is allowed to rise.
During turn-off of the lower MOSFET, the LGATE voltage is
monitored until it reaches a 2.2V threshold, at which time the
UGATE is released to rise. Adaptive shoot-through circuitry
monitors the PHASE voltage during UGATE turn-off. Once
PHASE has dropped below a threshold of 0.5V, the LGATE
is allowed to rise. If the PHASE does not drop below 0.5V
within 250ns, LGATE is allowed to rise. This is done to
generate the bootstrap refresh signal. PHASE continues to
be monitored during the lower gate rise time. If the PHASE
voltage exceeds the 0.5V threshold during this period and
remains high for longer than 2µs, the LGATE transitions low.
This is done to make the lower MOSFET emulate a diode.
Both upper and lower gates are then held low until the next
rising edge of the PWM signal.
Power-On Reset (POR) Function
During initial start-up, the VCC voltage rise is monitored and
gate drives are held low until a typical VCC rising threshold
of 9.95V is reached. Once the rising VCC threshold is
exceeded, the PWM input signal takes control of the gate
drives. If VCC drops below a typical VCC falling threshold of
7.6V during operation, then both gate drives are again held
low. This condition persists until the VCC voltage exceeds
the VCC rising threshold.
Internal Bootstrap Device
The HIP6602B features an internal bootstrap device. Simply
adding an external capacitor across the BOOT and PHASE
pins completes the bootstrap circuit.
7
The bootstrap capacitor must have a maximum voltage
rating above PVCC + 5V. The bootstrap capacitor can be
chosen from the following equation:
Q GATE
C BOOT  -----------------------V BOOT
Where QGATE is the amount of gate charge required to fully
charge the gate of the upper MOSFET. The VBOOT term is
defined as the allowable droop in the rail of the upper drive.
As an example, suppose a HUF76139 is chosen as the
upper MOSFET. The gate charge, QGATE , from the data
sheet is 65nC for a 10V upper gate drive. We will assume a
200mV droop in drive voltage over the PWM cycle. We find
that a bootstrap capacitance of at least 0.325µF is required.
The next larger standard value capacitance is 0.33µF.
In applications which require down conversion from +12V or
higher and PVCC is connected to a +12V source, a boot
resistor in series with the boot capacitor is required. The
increased power density of these designs tend to lead to
increased ringing on the BOOT and PHASE nodes, due to
faster switching of larger currents across given circuit
parasitic elements. The addition of the boot resistor allows
for tuning of the circuit until the peak ringing on BOOT is
below 29V from BOOT to GND and 17V from BOOT to VCC.
A boot resistor value of 5 typically meets this criteria.
In some applications, a well tuned boot resistor reduces the
ringing on the BOOT pin, but the PHASE to GND peak
ringing exceeds 17V. A gate resistor placed in the UGATE
trace between the controller and upper MOSFET gate is
recommended to reduce the ringing on the PHASE node by
slowing down the upper MOSFET turn-on. A gate resistor
value between 2 to 10 typically reduces the PHASE to
GND peak ringing below 17V.
Gate Drive Voltage Versatility
The HIP6602B provides the user flexibility in choosing the
gate drive voltage. Simply applying a voltage from 5V up to
12V on PVCC will set both driver rail voltages.
Power Dissipation
Package power dissipation is mainly a function of the switching
frequency and total gate charge of the selected MOSFETs.
Calculating the power dissipation in the driver for a desired
application is critical to ensuring safe operation. Exceeding the
maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
temperature of 125°C. The maximum allowable IC power
dissipation for the 14 lead SOIC package is approximately
1000mW. Improvements in thermal transfer may be gained by
increasing the PC board copper area around the HIP6602B.
Adding a ground pad under the IC to help transfer heat to the
outer peripheral of the board will help. Also keeping the leads to
the IC as wide as possible and widening this these leads as
soon as possible to further enhance heat transfer will also help.
FN9076.6
December 3, 2015
HIP6602B
When designing the driver into an application, it is
recommended that the following calculation be performed to
ensure safe operation at the desired frequency for the
selected MOSFETs. The total chip power dissipation is
approximated as:
3 (Q + Q ) + (Q + Q )] + I
P = 1.05 x fSW x VPVCC [_
U2
L1
L2
DDQ x VCC
2 U1
where fsw is the switching frequency of the PWM signal. QU
and QL is the upper and lower gate charge determined by
MOSFET selection and any external capacitance added to
the gate pins. The IDDQ VCC product is the quiescent power
of the driver and is typically 40mW.
The 1.05 term is a correction factor derived from the
following characterization. The base circuit for characterizing
the drivers for different loading profiles and frequencies is
provided. CU and CL are the upper and lower gate load
capacitors. Decoupling capacitors [0.15µF] are added to the
PVCC and VCC pins. The bootstrap capacitor value in the
test circuit is 0.01µF.
In Figure 2, CU and CL values are the same and frequency
is varied from 10kHz to 1.5MHz. PVCC and VCC are tied
together to a +12V supply.
Figure 3 shows the dissipation in the driver with 1nF loading
on both gates and each individually. Figure 4 is the same as
Figure 3 except the capacitance is increased to 3nF.
The impact of loading on power dissipation is shown in
Figure 5. Frequency is held constant while the gate
capacitors are varied from 1nF to 5nF. VCC and PVCC are
tied together and to a +12V supply. Figures 6, 7 and 8 show
the same characterization for PVCC tied to +5V instead of
+12V. The gate supply voltage, PVCC, within the HIP6602B
sets both upper and lower gate driver supplies at the same
5V level for the last three curves.
The power dissipation approximation is a result of power
transferred to and from the upper and lower gates. But, the
internal bootstrap device also dissipates power on-chip
during the refresh cycle. Expressing this power in terms of
the upper MOSFET total gate charge is explained below.
The bootstrap device conducts when the lower MOSFET or
its body diode conducts and pulls the PHASE node toward
GND. While the bootstrap device conducts, a current path is
formed that refreshes the bootstrap capacitor. Since the
upper gate is driving a MOSFET, the charge removed from
the bootstrap capacitor is equivalent to the total gate charge
of the MOSFET. Therefore, the refresh power required by
the bootstrap capacitor is equivalent to the power used to
charge the gate capacitance of the upper MOSFETs.
P REFRESH = f SW Q
V
= f SW Q V
LOSS PVCC
U PVCC
where QLOSS is the total charge removed from the bootstrap
capacitors and provided to the upper gate loads.
8
FN9076.6
December 3, 2015
HIP6602B
Test Circuit
+5V OR +12V
+12V
+5V OR +12V
0.01µF
PVCC
BOOT1
2N7002
0.15µF
UGATE1
CU
PHASE1
VCC
0.15µF
LGATE1
PWM1
GND
HIP6602B
PGND
100k
2N7002
CL
0.01µF
BOOT2
2N7002
UGATE2
CU
PHASE2
PWM2
LGATE2
2N7002
CL
100k
FIGURE 1. HIP6602B TEST CIRCUIT
Typical Performance Curves
1200
1200
CU = CL
= 5nF
PVCC = VCC = 12V
1000
CU = C L
= 4nF
800
CU = CL
= 3nF
PVCC = 12V
VCC = 12V
POWER (mW)
POWER (mW)
1000
600
CU = CL = 2nF
400
0
0
500
CL = 1nF, CU = 0nF
600
400
200
1000
FREQUENCY (kHz)
FIGURE 2. POWER DISSIPATION vs FREQUENCY
9
800
CU = 1nF, CL = 0nF
CU = CL = 1nF
200
CU = CL = 1nF
1500
0
0
500
1000
1500
2000
FREQUENCY (kHz)
FIGURE 3. 1nF LOADING PROFILE
FN9076.6
December 3, 2015
HIP6602B
Typical Performance Curves
(Continued)
1200
1200
PVCC = VCC = 12V
PVCC = VCC = 12V
1000
1000
500kHz
800
600
POWER (mW)
POWER (mW)
CU = CL = 3nF
CU = 3nF, CL = 0nF
CL = 3nF, CU = 0nF
400
800
600
200kHz
400
100kHz
200
200
0
0
500
0
1500
1000
FIGURE 4. 3nF LOADING PROFILE
2
3
4
5
FIGURE 5. POWER DISSIPATION vs LOADING
350
800
PVCC = 5V, VCC = 12V
700
PVCC = 5V, VCC = 12V
CU = CL = 5nF
300
CU = CL = 4nF
600
CU = CL = 1nF
CU = CL = 3nF
250
500
POWER (mW)
POWER (mW)
1
GATE CAPACITANCE (CU = CL ), (nF)
FREQUENCY (kHz)
400
300
CU = CL =1nF
500
1000
FREQUENCY (kHz)
1500
2000
FIGURE 6. POWER DISSIPATION vs FREQUENCY, PVCC = 5V
10
150
CU = 1nF, CL = 0nF
50
100
0
CL = 1nF, CU = 0nF
200
100
CU = CL = 2nF
200
0
10kHz
30kHz
0
0
500
1000
FREQUENCY (kHz)
1500
2000
FIGURE 7. POWER DISSIPATION vs FREQUENCY, PVCC = 5V
FN9076.6
December 3, 2015
HIP6602B
Typical Performance Curves
(Continued)
600
PVCC = 5V,
VCC = 12V
500
POWER (mW)
2MHz
1.5MHz
1MHz
400
300
500kHz
200
100kHz
200kHz
100
0
30kHz
1
2
3
4
GATE CAPACITANCE (CU = CL), (nF)
5
FIGURE 8. POWER DISSIPATION vs LOADING, PVCC = 5V
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE
REVISION
December 3, 2015
FN9076.6
CHANGE
Added recommended replacement parts ISL6622 and ISL6625A.
Added Rev History and About Intersil Verbiage.
Updated POD M14.15 to most current version. Rev change as follows:
Added land pattern and moved dimensions from table onto drawing.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
11
FN9076.6
December 3, 2015
HIP6602B
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L16.5x5
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VHHB ISSUE C)
MILLIMETERS
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
0.80
0.90
1.00
-
A1
-
-
0.05
-
A2
-
-
1.00
9
A3
b
0.20 REF
0.28
D
0.40
5, 8
5.00 BSC
D1
D2
0.33
9
-
4.75 BSC
2.55
2.70
9
2.85
7, 8
E
5.00 BSC
-
E1
4.75 BSC
9
E2
2.55
e
2.70
2.85
7, 8
0.80 BSC
-
k
0.25
-
-
-
L
0.35
0.60
0.75
8
L1
-
-
0.15
10
N
16
Nd
2
4
3
Ne
4
4
3
P
-
-
0.60
9

-
-
12
9
Rev. 2 10/02
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P &  are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
12
FN9076.6
December 3, 2015
HIP6602B
Package Outline Drawing
M14.15
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 1, 10/09
8.65
A 3
4
0.10 C A-B 2X
6
14
DETAIL"A"
8
0.22±0.03
D
6.0
3.9
4
0.10 C D 2X
0.20 C 2X
7
PIN NO.1
ID MARK
5
0.31-0.51
B 3
(0.35) x 45°
4° ± 4°
6
0.25 M C A-B D
TOP VIEW
0.10 C
1.75 MAX
H
1.25 MIN
0.25
GAUGE PLANE C
SEATING PLANE
0.10 C
0.10-0.25
1.27
SIDE VIEW
(1.27)
DETAIL "A"
(0.6)
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSEY14.5m-1994.
3. Datums A and B to be determined at Datum H.
(5.40)
4. Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
5. The pin #1 indentifier may be either a mold or mark feature.
(1.50)
6. Does not include dambar protrusion. Allowable dambar protrusion
shall be 0.10mm total in excess of lead width at maximum condition.
7. Reference to JEDEC MS-012-AB.
TYPICAL RECOMMENDED LAND PATTERN
13
FN9076.6
December 3, 2015
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