DATASHEET

ISL6622B
®
Data Sheet
March 19, 2009
VR11.1 Compatible Synchronous
Rectified Buck MOSFET Drivers
Features
• Dual MOSFET Drives for Synchronous Rectified Bridge
The ISL6622B is a high frequency MOSFET driver designed
to drive upper and lower power N-Channel MOSFETs in a
synchronous rectified buck converter topology. The advanced
PWM protocol of ISL6622B is specifically designed to work
with Intersil VR11.1 controllers and combined with
N-Channel MOSFETs, form a complete core-voltage regulator
solution for advanced microprocessors. When ISL6622B
detects a PSI PWM protocol sent by an Intersil VR11.1
controller, it activates Diode Emulation (DE) operation;
otherwise, it operates in normal Continuous Conduction
Mode (CCM) PWM mode.
In the 8 Ld SOIC package, the ISL6622B drives the upper
gate to 12V while the lower drive voltage is fixed at 5.75V. The
10 Ld DFN part offers more flexibility: the upper gate can be
driven from 5V to 12V via the UVCC pin, while the lower gate
has a resistor-selectable drive voltage of 5.75V, 6.75V, and
7.75V (typically). This provides the flexibility necessary to
optimize applications involving trade-offs between gate
charge and conduction losses.
To further enhance light load efficiency, the ISL6622B
enables diode emulation operation during PSI mode. This
allows for Discontinuous Conduction Mode (DCM) operation
by detecting when the inductor current reaches zero and
subsequently turning off the low side MOSFET to prevent it
from sinking current.
An advanced adaptive shoot-through protection is integrated
to prevent both the upper and lower MOSFETs from
conducting simultaneously and to minimize dead time. The
ISL6622B has a 20kΩ integrated high-side MOSFET
gate-to-source resistor to prevent self turn-on due to high
input bus dV/dt. This driver also has an overvoltage
protection feature operational while VCC is below the POR
threshold: the PHASE node is connected to the gate of the
low side MOSFET (LGATE) via a 10kΩ resistor, limiting the
output voltage of the converter close to the gate threshold of
the low side MOSFET, dependent on the current being
shunted, which provides some protection to the load should
the upper MOSFET(s) be shorted prior to start-up.
1
FN6602.1
• Advanced Adaptive Zero Shoot-Through Protection
• Integrated LDO with Selectable Lower Gate Drive Voltage
for Light Load Efficiency Optimization
• 36V Internal Bootstrap Diode
• Advanced PWM Protocol (Patent Pending) to Support PSI
Operation
• Diode Emulation for Enhanced Light Load Efficiency
• Bootstrap Capacitor Overcharging Prevention
• Supports High Switching Frequency
- 3A Sinking Current Capability
- Fast Rise/Fall Times and Low Propagation Delays
• Integrated UGATE-to-PHASE Resistor for Increased
Upper MOSFET Input Bus High dV/dt Immunity
• Pre-POR Overvoltage Protection at Start-Up and
Shutdown
• Dual Flat No-Lead (DFN) Package
- Near Chip-Scale Package Footprint; Improves PCB
Efficiency and Thinner in Profile
- Bottom Copper Pad for Enhanced Heat Sinking
• Pb-Free (RoHS Compliant)
Applications
• High Light-Load Efficiency Voltage Regulators
• Core Regulators for Advanced Microprocessors
• High Current DC/DC Converters
• High Frequency and High Efficiency VRM and VRD
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Technical Brief TB417 “Designing Stable Compensation
Networks for Single Phase Voltage Mode Buck
Regulators” for Power Train Design, Layout Guidelines,
and Feedback Compensation Design
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008, 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL6622B
Ordering Information
PART NUMBER
(Note)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL6622BCBZ*
6622B CBZ
0 to +70
8 Ld SOIC
M8.15
ISL6622BCRZ*
622B
0 to +70
10 Ld 3x3 DFN
L10.3x3
ISL6622BIBZ*
6622B IBZ
-40 to +85
8 Ld SOIC
M8.15
ISL6622BIRZ*
22BI
-40 to +85
10 Ld 3x3 DFN
L10.3x3
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pinouts
ISL6622B
(10 LD 3x3 DFN)
TOP VIEW
ISL6622B
(8 LD SOIC)
TOP VIEW
UGATE
1
8
PHASE
BOOT
2
7
VCC
PWM
3
6
LVCC
GND
4
5
LGATE
UGATE 1
10 PHASE
BOOT 2
9 VCC
GD_SEL 3
PAD
8 UVCC
PWM 4
7 LVCC
GND 5
6 LGATE
Block Diagrams
ISL6622B
BOOT
UVCC
UGATE
LDO
GD_SEL
20k
VCC
PHASE
+5V
LVCC
11.2k
SHOOTTHROUGH
PROTECTION
10k
LVCC
POR/
PWM
CONTROL
9.6k
LOGIC
LGATE
GND
UVCC = VCC for SOIC
LVCC = 5.75V (TYPICALLY) at 50mA for SOIC
2
March 19, 2009
ISL6622B
Typical Application Circuit
+12V
VIN
BOOT
LVCC
+5V
VCC
UGATE
PHASE
ISL6622B
DRIVER
LGATE
FB
COMP VCC
DAC
GND
PWM
REF
VDIFF
VSEN
PWM1
RGND
VTT
EN_VTT
VIN
+12V
ISEN1-
BOOT
PVCC
ISEN1+
VR_RDY
VCC
UGATE
VID7
VID6
ISL6334
VID5
ISL6334
PHASE
ISL6612
DRIVER
LGATE
VID4
PWM2
VID3
VID2
GND
PWM
ISEN2-
VID1
ISEN2+
VID0
VIN
+12V
PSI
PVCC
PWM3
VR_FAN
BOOT
µP
LOAD
ISEN3-
VR_HOT
ISEN3+
VCC
UGATE
VIN
PHASE
ISL6612
DRIVER
EN_PWR
LGATE
GND
PWM
GND
PWM4
IMON
ISEN4ISEN4+
TCOMP
VIN
+12V
TM
OFS
FS
BOOT
SS
PVCC
+5V
+5V
VCC
UGATE
PHASE
NTC
ISL6612
DRIVER
LGATE
PWM
3
GND
March 19, 2009
ISL6622B
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VCC, UVCC) . . . . . . . . . . . . . . . . . . . . . . . . . . .15V
BOOT Voltage (VBOOT-GND). . . . . . . . . . . . . . . . . . . . . . . . . . . .36V
Input Voltage (VPWM) . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 7V
UGATE. . . . . . . . . . . . . . . . . . . VPHASE - 0.3VDC to VBOOT + 0.3V
VPHASE - 3.5V (<100ns Pulse Width, 2µJ) to VBOOT + 0.3V
LGATE . . . . . . . . . . . . . . . . . . GND - 0.3VDC to VLVCCLVCC + 0.3V
GND - 5V (<100ns Pulse Width, 2µJ) to VLVCCLVCC + 0.3V
PHASE. . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3VDC to 15VDC
GND - 8V (<400ns, 20µJ) to 30V (<200ns, VBOOT-GND<36V)
Thermal Resistance
θJA (°C/W)
θJC (°C/W)
SOIC Package (Note 1) . . . . . . . . . . . .
100
N/A
DFN Package (Notes 2, 3) . . . . . . . . . .
48
7
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range
ISL6622BIBZ, ISL6622BIRZ . . . . . . . . . . . . . . . . .-40°C to +85°C
ISL6622BCBZ, ISL6622BCRZ . . . . . . . . . . . . . . . . . 0°C to +70°C
Maximum Operating Junction Temperature. . . . . . . . . . . . . +125°C
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8V to 13.2V
Supply Voltage Range, UVCC . . . . . . . . . . . . . . . . . . 4.75V to 13.2V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
3. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
4. Limits should be considered typical and are not production tested.
Z
Electrical Specifications
Recommended Operating Conditions. Parameters with MIN and/or MAX limits are 100% tested at +25°C,
unless otherwise specified. Temperature limits established by characterization and are not production
tested.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VCC SUPPLY CURRENT
No Load Switching Supply Current
IVCC
ISL6622BCBZ and ISL6622BIBZ,
fPWM = 300kHz, VVCC = 12V
-
8.6
-
mA
IVCC
ISL6622BCRZ and ISL6622BIRZ,
fPWM = 300kHz, VVCC = 12V
-
6.6
-
mA
-
2
-
mA
-
5.1
-
mA
IUVCC
Standby Supply Current
IVCC
ISL6622BCBZ and ISL6622BIBZ, PWM
Transition from 0V to 2.5V
IVCC
ISL6622BCRZ and ISL6622BIRZ, PWM
Transition from 0V to 2.5V
-
5.0
-
mA
-
0.07
-
mA
VCC Rising Threshold
6.25
6.45
6.70
V
VCC Falling Threshold
4.8
5.0
5.25
V
LVCC Rising Threshold (Note 4)
-
4.4
-
V
LVCC Falling Threshold (Note 4)
-
3.4
-
V
IUVCC
POWER-ON RESET
PWM INPUT (See “TIMING DIAGRAM” on page 6)
Input Current
IPWM
PWM Rising Threshold
VPWM = 5V
-
500
-
µA
VPWM = 0V
-
-430
-
µA
VCC = 12V
-
3.4
-
V
PWM Falling Threshold
VCC = 12V
-
1.6
-
V
Tristate Lower Gate Falling Threshold
VCC = 12V
-
1.60
-
V
Tristate Lower Gate Rising Threshold
VCC = 12V
-
1.1
-
V
Tristate Upper Gate Rising Threshold
VCC = 12V
-
3.2
-
V
Tristate Upper Gate Falling Threshold
VCC = 12V
-
2.8
-
V
4
March 19, 2009
ISL6622B
Electrical Specifications
Recommended Operating Conditions. Parameters with MIN and/or MAX limits are 100% tested at +25°C,
unless otherwise specified. Temperature limits established by characterization and are not production
tested. (Continued)
MIN
TYP
MAX
UNITS
UGATE Rise Time
PARAMETER
SYMBOL
tRU
VVCC = 12V, 3nF Load, 10% to 90%
TEST CONDITIONS
-
26
-
ns
LGATE Rise Time
tRL
VVCC = 12V, 3nF Load, 10% to 90%
-
18
-
ns
UGATE Fall Time
tFU
VVCC = 12V, 3nF Load, 90% to 10%
-
18
-
ns
LGATE Fall Time
tFL
VVCC = 12V, 3nF Load, 90% to 10%
-
12
-
ns
UGATE Turn-On Propagation Delay (Note 4)
tPDHU
VVCC = 12V, 3nF Load, Adaptive
-
20
-
ns
LGATE Turn-On Propagation Delay (Note 4)
tPDHL
VVCC = 12V, 3nF Load, Adaptive
-
10
-
ns
UGATE Turn-Off Propagation Delay (Note 4)
tPDLU
VVCC = 12V, 3nF Load
-
10
-
ns
LGATE Turn-Off Propagation Delay (Note 4)
tPDLL
VVCC = 12V, 3nF Load
-
10
-
ns
Tristate Low Delay
tTSLD
VVCC = 12V
-
60
-
ns
tLG_ON_DM
VVCC = 12V
230
330
450
ns
Upper Drive Source Current
IU_SOURCE
VVCC = 12V, 3nF Load
-
1.25
-
A
Upper Drive Source Impedance
RU_SOURCE 20mA Source Current
Minimum LGATE ON-Time During PSI Operation
OUTPUT (Note 4)
-
2.0
-
Ω
Upper Drive Sink Current
IU_SINK
VVCC = 12V, 3nF Load
-
2
-
A
Upper Drive Sink Impedance
RU_SINK
20mA Sink Current
-
1.35
-
Ω
Lower Drive Source Current
IL_SOURCE
Lower Drive Source Impedance
RL_SOURCE 20mA Source Current
VVCC = 12V, 3nF Load
-
2
-
A
-
1.35
-
Ω
Lower Drive Sink Current
IL_SINK
VVCC = 12V, 3nF Load
-
3
-
A
Lower Drive Sink Impedance
RL_SINK
20mA Sink Current
-
0.90
-
Ω
Functional Pin Description
PACKAGE PIN #
SOIC
DFN
PIN
SYMBOL
1
1
UGATE
Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.
2
2
BOOT
Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See “Internal Bootstrap
Device” on page 7 for guidance in choosing the capacitor value.
-
3
GD_SEL
3
4
PWM
The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation,
see “Advanced PWM Protocol (Patent Pending)” on page 6 for further details. Connect this pin to the PWM output
of the controller.
4
5
GND
Bias and reference ground. All signals are referenced to this node. It is also the power ground return of the driver.
5
6
LGATE
6
7
LVCC
This pin provides power for the LGATE drive. Place a high quality low ESR ceramic capacitor from this pin to GND.
-
8
UVCC
This pin supplies power to the upper gate drive. Its operating range is +5V to +12V. Place a high quality low ESR
ceramic capacitor from this pin to GND.
7
9
VCC
Connect this pin to 12V bias supply. This pin supplies power to the upper gate in the SOIC and to the LDO for the
lower gate drive. Place a high quality low ESR ceramic capacitor from this pin to GND.
8
10
PHASE
Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides
a return path for the upper gate drive.
-
11
PAD
FUNCTION
This pin sets the LG drive voltage.
Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.
Connect this pad to the power ground plane (GND) via thermally enhanced connection.
5
March 19, 2009
ISL6622B
1.5V<PWM<3.2V
1.0V<PWM<2.6V
PWM
tPDLU
tPDHU
tTSLD
tPDTS
tPDTS
UGATE
tFU
tRU
LGATE
tFL
tRL
tTSHD
tPDLL
tPDHL
FIGURE 1. TIMING DIAGRAM
Description
Operation and Adaptive Shoot-through Protection
Designed for high speed switching, the ISL6622B MOSFET
driver controls both high-side and low-side N-Channel FETs
from one externally provided PWM signal.
A rising transition on PWM initiates the turn-off of the lower
MOSFET (see Figure 1). After a short propagation delay
[tPDLL], the lower gate begins to fall. Typical fall time [tFL] is
provided in the “Electrical Specifications” on page 5. Following
a 25ns blanking period, adaptive shoot-through circuitry
monitors the LGATE voltage and turns on the upper gate
following a short delay time [tPDHU] after the LGATE voltage
drops below ~1.75V. The upper gate drive then begins to rise
[tRU] and the upper MOSFET turns on.
A falling transition on PWM indicates the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
propagation delay [tPDLU] is encountered before the upper gate
begins to fall [tFU]. The adaptive shoot-through circuitry
monitors the UGATE-PHASE voltage and turns on the lower
MOSFET a short delay time [tPDHL] after the upper MOSFET’s
PHASE voltage drops below +0.8V or 40ns after the upper
MOSFET’s gate voltage [UGATE-PHASE] drops below ~1.75V.
The lower gate then rises [tRL], turning on the lower MOSFET.
These methods prevent both the lower and upper MOSFETs
from conducting simultaneously (shoot-through), while adapting
the dead time to the gate charge characteristics of the
MOSFETs being used.
This driver is optimized for voltage regulators with large step
down ratio. The lower MOSFET is usually sized larger
compared to the upper MOSFET because the lower MOSFET
conducts for a longer time during a switching period. The
lower gate driver is therefore sized much larger to meet this
application requirement. The 0.8Ω ON-resistance and 3A sink
current capability enable the lower gate driver to absorb the
current injected into the lower gate through the drain-to-gate
capacitor of the lower MOSFET and help prevent
6
shoot-through caused by the self turn-on of the lower
MOSFET due to high dV/dt of the switching node.
Advanced PWM Protocol (Patent Pending)
The advanced PWM protocol of ISL6622B is specifically
designed to work with Intersil VR11.1 controllers. When
ISL6622B detects a PSI protocol sent by an Intersil VR11.1
controller, it turns on diode emulation operation; otherwise, it
remains in normal CCM PWM mode.
Another unique feature of ISL6622B and other Intersil drivers
is the addition of a tristate shutdown window to the PWM
input. If the PWM signal enters and remains within the
shutdown window for a set holdoff time, the driver outputs are
disabled and both MOSFET gates are pulled and held low.
The shutdown state is removed when the PWM signal moves
outside the shutdown window. Otherwise, the PWM rising and
falling thresholds outlined in the “Electrical Specifications” on
page 4 determine when the lower and upper gates are
enabled. This feature helps prevent a negative transient on
the output voltage when the output is shut down, eliminating
the Schottky diode that is used in some systems for protecting
the load from reversed output voltage events.
Note that for a PWM low to tri-level (2.5V) transition, the
LGATE will not turn off until the diode emulation minimum
ON-time of 350ns is expired.
Diode Emulation
Diode emulation allows for higher converter efficiency under
light-load situations. With diode emulation active, the
ISL6622B detects the zero current crossing of the output
inductor and turns off LGATE. This prevents the low side
MOSFET from sinking current and ensures that
discontinuous conduction mode (DCM) is achieved. The
LGATE has a minimum ON-time of 350ns in DCM mode.
Gate Voltage Optimization Technology (GVOT)
The ISL6622B provides the user flexibility in choosing the gate
drive voltage for efficiency optimization. In applications when
the switching losses dominate system performance, dropping
March 19, 2009
ISL6622B
Figure 2 shows that the gate drive voltage optimization is
accomplished via an internal low drop out regulator (LDO)
that regulates the lower gate drive voltage. LVCC is driven to
a lower voltage depending on the GD_SEL pin impedance.
The input and output of this internal regulator are the VCC
and LVCC pins, respectively. Both VCC and LVCC should be
decoupled with a high quality, low ESR ceramic capacitor.
EXTERNAL CIRCUIT
ISL6622B INTERNAL CIRCUIT
VCC
VIN >
GVOT
LDO
1µF
+
-
RCC
9.0
8.5
+120°C
+40°C
-40°C
GD_SEL TIED TO GND
8.0
7.5
GD_SEL TIED TO 4.5kΩ TO GND
7.0
6.5
GD_SEL FLOATING
6.0
SET BY
GD_SEL
5.5
+
5.0
-
0
20
40
60
80
100
AVERAGE LOAD CURRENT (mA)
FIGURE 3. TYPICAL LVCC VARIATION WITH LOAD
LVCC
LGATE
DRIVER
1µF
RCC = OPTION FOR HIGHER LVCC
THAN PRE-SET BY GD_SEL
FIGURE 2. GATE VOLTAGE OPTIMIZATION (GVOT) DETAIL
In the 8 Ld SOIC package, the ISL6622B drives the upper
gate to 12V while the lower drive voltage is fixed at 5.75V. The
10 Ld DFN part offers more flexibility: the upper gate can be
driven from 5V to 12V via the UVCC pin, while the lower gate
has a resistor-selectable drive voltage of 5.75V, 6.75V, and
7.75V (typically). This provides the flexibility necessary to
optimize applications involving trade-offs between gate
charge and conduction losses. Table 1 shows the LDO output
(LVCC) level set by GD_SEL pin impedance.
TABLE 1. LDO OPERATION AND OPTIONS
PWM INPUT GD_SEL PIN
Don’t Care
takes control of the gate drives. If VCC drops below the POR
falling threshold, operation of the driver is disabled.
LVCC VOLTAGE (V)
down to a lower drive voltage with GVOT can improve the
switching losses seen and maximize system efficiency.
LVCC @ 50mA DC LOAD
Floating
5.75V (Typical; Fixed in SOIC Package)
4.5kΩ to GND
6.75V(Typical)
GND
7.75V(Typical)
Figure 3 illustrates the internal LDO’s variation with the
average load current plotted over a range of temperatures
spanning from -40°C to +120°C. Should finer tweaking of this
LVCC voltage be necessary, a resistor (RCC) can be used to
shunt the LDO, as shown in Figure 2. The resistor thus
delivers part of the LGATE drive current, leaving less current
going through the internal LDO, elevating the LDO’s output
voltage. Further reduction in RCC’s value can raise the
LVCC voltage further, as desired.
Power-On Reset (POR) Function
During initial start-up, the VCC voltage rise is monitored. Once
the rising VCC voltage exceeds the rising POR threshold,
operation of the driver is enabled and the PWM input signal
7
Pre-POR Overvoltage Protection
While VCC is below its POR level, the upper gate is held low
and LGATE is connected to the PHASE pin via an internal
10kΩ (typically) resistor. By connecting the PHASE node to the
gate of the low side MOSFET, the driver offers some passive
protection to the load if the upper MOSFET(s) is or becomes
shorted. If the PHASE node goes higher than the gate
threshold of the lower MOSFET, it results in the progressive
turn-on of the device and the effective clamping of the PHASE
node’s rise. The actual PHASE node clamping level depends
on the lower MOSFET’s electrical characteristics, as well as the
characteristics of the input supply and the path connecting it to
the respective PHASE node.
Internal Bootstrap Device
The ISL6622B features an internal bootstrap Schottky diode.
Simply adding an external capacitor across the BOOT and
PHASE pins completes the bootstrap circuit. The bootstrap
function is also designed to prevent the bootstrap capacitor
from overcharging due to the large negative swing at the
trailing-edge of the PHASE node. This reduces the voltage
stress on the BOOT to PHASE pins.
The bootstrap capacitor must have a maximum voltage rating
well above the maximum voltage intended for UVCC. Its
minimum capacitance value can be estimated from Equation 1:
Q GATE
C BOOT_CAP ≥ -------------------------------------ΔV BOOT_CAP
Q G1 • UVCC
Q GATE = ------------------------------------ • N Q1
V GS1
(EQ. 1)
where QG1 is the amount of gate charge per upper MOSFET
at VGS1 gate-source voltage and NQ1 is the number of
control MOSFETs. The ΔVBOOT_CAP term is defined as the
allowable droop in the rail of the upper gate drive. Select
results are exemplified in Figure 4.
March 19, 2009
ISL6622B
1.6
P DR = P DR_UP + P DR_LOW + I Q • VCC
1.4
R LO1
R HI1
⎛
⎞ P Qg_Q1
P DR_UP = ⎜ -------------------------------------- + ----------------------------------------⎟ • --------------------2
⎝ R HI1 + R EXT1 R LO1 + R EXT1⎠
CBOOT_CAP (µF)
1.2
R HI2
R LO2
⎛
⎞ P Qg_Q2
P DR_LOW = ⎜ -------------------------------------- + ----------------------------------------⎟ • --------------------R
+
R
R
+
R
2
⎝ HI2
EXT2
LO2
EXT2⎠
1.0
0.8
R GI1
R EXT1 = R G1 + ------------N
0.6
Q1
QGATE = 100nC
0.4
50nC
0.2 20nC
0.0
0.0
(EQ. 4)
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
ΔVBOOT_CAP (V)
FIGURE 4. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
Power Dissipation
P Qg_TOT = P Qg_Q1 + P Qg_Q2 + I Q • VCC
Q2
The total gate drive power losses are dissipated among the
resistive components along the transition path, as outlined in
Equation 4. The drive resistance dissipates a portion of the
total gate drive power losses, the rest will be dissipated by the
external gate resistors (RG1 and RG2) and the internal gate
resistors (RGI1 and RGI2) of MOSFETs. Figures 5 and 6 show
the typical upper and lower gate drives turn-on current paths.
BOOT
UVCC
Package power dissipation is mainly a function of the
switching frequency (FSW), the output drive impedance, the
layout resistance, and the selected MOSFET’s internal gate
resistance and total gate charge (QG). Calculating the power
dissipation in the driver for a desired application is critical to
ensure safe operation. Exceeding the maximum allowable
power dissipation level may push the IC beyond the maximum
recommended operating junction temperature. The DFN
package is more suitable for high frequency applications. See
“Layout Considerations” on page 8 for thermal impedance
improvement suggestions. The total gate drive power losses
due to the gate charge of MOSFETs and the driver’s internal
circuitry and their corresponding average driver current can
be estimated with Equations 2 and 3, respectively:
R GI2
R EXT2 = R G2 + ------------N
D
CGD
RHI1
RLO1
G
RL1
CGS
PHASE
FIGURE 5. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
LVCC
D
CGD
RHI2
RLO2
G
RL2
where the gate charge (QG1 and QG2) is defined at a
particular gate to source voltage (VGS1 and VGS2) in the
corresponding MOSFET data sheet; IQ is the driver’s total
quiescent current with no load at both drive outputs; NQ1
and NQ2 are number of upper and lower MOSFETs,
respectively; UVCC and LVCC are the drive voltages for
both upper and lower FETs, respectively. The IQ*VCC
product is the quiescent power of the driver without a load.
CDS
RG2
CGS
Q G2 • LVCC 2
P Qg_Q2 = -------------------------------------- • F SW • N Q2
V GS2
⎛ Q G1 • UVCC • NQ1 Q G2 • LVCC • N Q2⎞
I DR = ⎜ ------------------------------------------------------ + -----------------------------------------------------⎟ • F SW + I Q
V GS1
V GS2
⎝
⎠
(EQ. 3)
Q1
S
(EQ. 2)
Q G1 • UVCC 2
P Qg_Q1 = --------------------------------------- • F SW • N Q1
V GS1
CDS
RG1
Q2
S
FIGURE 6. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
Application Information
Layout Considerations
During switching of the devices, the parasitic inductances of
the PCB and the power devices’ packaging (both upper and
lower MOSFETs) leads to ringing, possibly in excess of the
absolute maximum rating of the devices. Careful layout can
help minimize such unwanted stress. The following advice is
meant to lead to an optimized layout:
• Keep decoupling loops (LVCC-GND and BOOT-PHASE)
as short as possible.
• Minimize trace inductance, especially low-impedance lines:
all power traces (UGATE, PHASE, LGATE, GND, LVCC)
should be short and wide, as much as possible.
8
March 19, 2009
ISL6622B
• Minimize the inductance of the PHASE node: ideally, the
source of the upper and the drain of the lower MOSFET
should be as close as thermally allowable.
• Minimize the input current loop: connect the source of the
lower MOSFET to ground as close to the transistor pin as
feasible; input capacitors (especially ceramic decoupling)
should be placed as close to the drain of upper and source
of lower MOSFETs as possible.
–V
DS
⎛
----------------------------------⎞
dV
⎜
------⋅
R
⋅ C iss⎟
dV
⎟
V GS_MILLER = ------- ⋅ R ⋅ C rss ⎜ 1 – e dt
⎜
⎟
dt
⎜
⎟
⎝
⎠
R = R UGPH + R GI
C rss = C GD
UVCC
Should the driver have insufficient bias voltage applied, its
outputs are floating. If the input bus is energized at a high
dV/dt rate while the driver outputs are floating, due to self
coupling via the internal CGD of the MOSFET, the gate of the
upper MOSFET could momentarily rise up to a level greater
than the threshold voltage of the device, potentially turning
on the upper switch. Therefore, if such a situation could
conceivably be encountered, it is a common practice to
place a resistor (RUGPH) across the gate and source of the
upper MOSFET to suppress the Miller coupling effect. The
value of the resistor depends mainly on the input voltage’s
rate of rise, the CGD/CGS ratio, as well as the gate-source
threshold of the upper MOSFET. A higher dV/dt, a lower
CDS/CGS ratio, and a lower gate-source threshold upper
FET will require a smaller resistor to diminish the effect of
the internal capacitive coupling. For most applications, the
integrated 20kΩ resistor is sufficient, not affecting normal
performance and efficiency.
The coupling effect can be roughly estimated with Equation 5,
which assumes a fixed linear input ramp and neglects the
clamping effect of the body diode of the upper drive and the
bootstrap capacitor. Other parasitic components, such as lead
inductances and PCB capacitances, are also not taken into
account. Figure 7 provides a visual reference for this
phenomenon and its potential solution.
VIN
BOOT
CBOOT
D
CGD
G
CDS
RG
RUGPH
UGATE
ISL6622B
Upper MOSFET Self Turn-On Effect at Start-up
C iss = C GD + C GS
>
In addition, for improved heat dissipation, place copper
underneath the IC whether it has an exposed pad or not. The
copper area can be extended beyond the bottom area of the
IC and/or connected to buried power ground plane(s) with
thermal vias. This combination of vias for vertical heat
escape, extended surface copper islands, and buried planes
combine to allow the IC and the power switches to achieve
their full thermal potential.
(EQ. 5)
CGS
20kΩ
QUPPER
S
PHASE
FIGURE 7. GATE TO SOURCE RESISTOR TO REDUCE
UPPER MOSFET MILLER COUPLING
–V
DS
⎛
----------------------------------⎞
dV
⎜
-----⋅
R
⋅C ⎟
dV
iss⎟
V GS_MILLER = ------- ⋅ R ⋅ C rss ⎜ 1 – e dt
⎜
⎟
dt
⎜
⎟
⎝
⎠
R = R UGPH + R GI
(EQ. 6)
C iss = C GD + C GS
C rss = C GD
Gate Drive Voltage Options
Intersil provides various gate drive voltage options in the
ISL6622 product family, as shown in Table 2.
The ISL6622 can drop the low-side MOSFET’s gate drive
voltage when operating in DEM, while the high-side FET’s
gate drive voltage of the DFN package can be connected to
VCC or LVCC.
The ISL6622A allows the low-side MOSFET(s) to operate
from an externally-provided rail as low as 5V, eliminating the
LDO losses, while the high-side MOSFET’s gate drive voltage
of the DFN package can be connected to VCC or LVCC.
The ISL6622B sets the low-side MOSFET’s gate drive voltage
at a fixed, programmable LDO level, while the highside FETs’
gate drive voltage of the DFN package can be connected to
VCC or LVCC.
TABLE 2. ISL6622 FAMILY OPTIONS
LVCC
POWER RAILS
ISL6622
ISL6622A
ISL6622B
PSI = LOW
PSI = HIGH
UVCC
VCC
SOIC
5.75V
11.2V
VCC
Operating Voltage Ranges from 6.8V to 13.2V
DFN
Programmable
11.2V
Separate Rail
SOIC
Separate Rail
VCC
DFN
Separate Rail
Separate Rail
SOIC
5.75V
VCC
DFN
Programmable
Separate Rail
9
March 19, 2009
ISL6622B
Dual Flat No-Lead Plastic Package (DFN)
2X
0.15 C A
D
A
L10.3x3
10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
MILLIMETERS
2X
0.15 C B
SYMBOL
MIN
6
INDEX
AREA
0.80
0.90
1.00
-
-
-
0.05
-
0.28
5,8
2.05
7,8
1.65
7,8
0.20 REF
0.18
D
1.95
E
0.10 C
0.08 C
SIDE VIEW
C
SEATING
PLANE
1
e
1.60
-
0.50 BSC
-
k
0.25
-
-
L
0.30
0.35
0.40
N
10
Nd
5
3
3. Nd refers to the number of terminals on D.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
E2/2
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
NX L
N-1
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
NX b
5
(Nd-1)Xe
REF.
8
2
2. N is the number of terminals.
E2
e
-
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
NX k
8
1.55
NOTES:
D2/2
2
N
-
Rev. 3 6/04
D2
(DATUM B)
2.00
8
7
6
INDEX
AREA
(DATUM A)
A3
-
3.00 BSC
E2
A
0.23
3.00 BSC
D2
B
NOTES
A
b
TOP VIEW
MAX
A1
A3
E
NOMINAL
0.10 M C A B
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
BOTTOM VIEW
C
L
0.415
NX (b)
(A1)
0.200
5
L
NX L
e
SECTION "C-C"
NX b
C
C C
TERMINAL TIP
FOR ODD TERMINAL/SIDE
10
March 19, 2009
ISL6622B
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
N
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
H
0.25(0.010) M
B M
INCHES
E
SYMBOL
-B-
1
2
3
L
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
MIN
MAX
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.1890
0.1968
4.80
5.00
3
E
0.1497
0.1574
3.80
4.00
4
e
α
B S
0.050 BSC
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
N
α
NOTES:
MILLIMETERS
8
0°
8
8°
0°
7
8°
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
11
March 19, 2009
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