an1625

Application Note 1625
Author: Barry Kates
ZL9101EVAL1Z Digital DC/DC 12A Module Evaluation
Board
Description
Key Features
The ZL9101M is a 12A variable output, step-down power
supply module. Included in the module is a high-performance
digital PWM controller, power MOSFETs, an inductor, and all
the passive components required for a complete DC/DC power
solution. The ZL9101M operates over a wide input voltage
range and supports an output voltage range of 0.6V to 4V,
which can be set by external resistors or via the PMBus. This
high-efficiency power module is capable of delivering 12A.
Only bulk input and output capacitors are needed to finish the
design. The output voltage can be precisely regulated to as low
as 0.6V with ±1% output voltage regulation.
• Complete Switch Mode Power Supply
The ZL9101EVAL1Z is a 6-layer board that provides a
single-phase power rail up to 12A loads. The board is designed
to efficiently transfer heat away from the module with passive
cooling.
• Convenient Power Connection
A USB to SMBus adapter is used to connect the ZL9101EVAL1Z
board to a PC. The PMBus command set is accessed by using
the PowerNavigator™ evaluation software.
• Configurable Through SMBus
• 12A DC Output Current
• Adjustable +0.6V to +4V Output Range
• Up to 90% Efficiency
• Digital Control PWM
• Fixed 615kHz Switching Frequency
• Fast Transient Response
• Enable Function Option
• Power-Good Indicator
• Multiple Power Options
• Single Supply Operation
Key Specifications
The ZL9101EVAL1Z has been designed and optimized for the
following parameters:
• VIN = 12V
• VOUT = 1.2V
• IOUT(MAX) = 15A
• FSW = 615kHz
• VOUT(RIPPLE) < 1%
• Transient Response = 3% (3A to 9A step at 2.5V/µs)
P4
P3
P2
J11
VIN
J8
Linear
Regulator
VDRV
J9
VDD
J 10
PG_0
ZL9101M
3
2
1
SW2
The rma l
Conne ction
JP1
ZL 9101
HW_EN
J4
ZL1505
VDD
VDD
EN
EN
PG
SYNC
SCL
SDA
DDC
VTRK
SA0
V1
V25
VR
PG
SYNC
SCL
SDA
DDC
VTRK
J5
PWMH
PWML
PWMH
PWML
P1
GH
SW
SW
VOUT
ISENA
ISENB
GL
FBFB+
GND
SGND
A ddress
Pinstra p
Voltage
Pinstrap
SG
PGND
J2
FBFB+
FIGURE 1. ZL9101EVAL1Z EVALUATION BOARD BLOCK DIAGRAM
February 4, 2011
AN1625.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Copyright Intersil Americas Inc. 2011. All Rights Reserved.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design), PowerNavigator, and CompZL are trademarks owned by
Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners.
Application Note 1625
Functional Description
The ZL9101EVAL1Z evaluation board provides all the circuitry
required to evaluate the features of the ZL9101M module. The
ZL9101EVAL1Z has a performance-optimized, single-phase
ZL9101M circuit layout that allows operation up to the maximum
rated output current. Power options and load connections are
provided through plug-in sockets and shorting jumpers.
Figure 1 shows a functional block diagram of the ZL9101EVAL1Z
board. The SMBus address is selectable through J4 located on
the top side of the board. All power to the board (VIN and I2C bus)
must be removed before changing the jumpers.
The hardware enable function is controlled by a toggle switch on
the ZL9101EVAL1Z board. The power-good (PG) LED indicates
the state of PG when external power is applied to the
ZL9101EVAL1Z board. The right-angle headers at opposite ends
of the board are for connecting a USB to an SMBus adapter board
or for daisy-chaining of multiple evaluation boards.
Figure 2 shows the ZL9101EVAL1Z operational circuit. The circuit
consists of the ZL9101M module and supporting components.
Figure 3 shows the ZL9101EVAL1Z interface schematic.
Figures 4 through 9 show the layers of the ZL9101EVAL1Z
evaluation board.
Basic Operation
The ZL9101EVAL1Z evaluation board is easy to set up and
operate. It is optimally configured, out of the box, to provide 1.2V
at 12A from a 12V source. All input and output connections
should be made before applying power.
The ZL9101M module requires a configuration file in order to
operate. The ZL9101M supports pinstrap configuration for output
voltage and SMBus address. All other parameters must be
configured with a text-based configuration file. See application
note AN2031 for more information on writing configuration files.
An example configuration file is listed at the end of this
document.
Pinstraps
The ZL9101M requires a configuration file for normal operation;
however, there are two pinstrap functions to be configured:
Voltage and SMBus address. Ensure that input power is removed,
and then set the address and voltage pinstraps using J4 and J6.
Apply VDD power, and the new settings will be in effect.
PMBus Operation
The ZL9101M utilizes the PMBus protocol. The PMBus
functionality can be controlled via USB from a PC running the
PowerNavigator™ evaluation software in a Windows XP or
Windows 2000/NT operating system.
Install the PowerNavigator™ software using the CD included in
the ZL9101EVAL1Z kit. For PMBus operation, connect the USB-toSMBus dongle board to J7 of the ZL9101EVAL1Z board. Connect
the desired load and an appropriate power supply to the input.
Place the ENABLE switch in “DISABLE” and turn on the power.
The PowerNavigator™ evaluation software allows modification of
all ZL9101M PMBus parameters. See Application Note AN2033
for PMBus command details. Use the mouse-over pop-ups for
PowerNavigator™ help. Manually configure the ZL9101M through
2
PowerNavigator™ or load a predefined scenario from a
configuration file.
The ENABLE switch can then be moved to “ENABLE” and the
ZL9101M can be tested. Alternately, the PMBus ONOFF, CONFIG,
and OPERATION commands can be used.
Single-Supply Operation
The ZL9101EVAL1Z board was designed to facilitate operation
from a single power supply input. The single input power mode
reduces the number of connections but results in a minor
reduction of efficiency.
The driver bias is supplied by an onboard linear regulator.
Figure 3 shows the onboard regulator circuit for powering the
ZL9101M driver. Jumpers J8 and J9 connect the supply power to
the linear regulator that is used to power the driver, and J6
connects input power to the ZL9101M digital module. If
single-supply operation is desired, J6, J8, and J9 must be
installed.
Multi-Supply Operation (External Driver
Supply)
To operate the ZL9101EVAL1Z driver from an external power
supply, remove J8 and J9, and connect an external power supply
to the driver connector, P3, between 4.5V to 6.5V.
To operate the ZL9101EVAL1Z board using different power
supplies for the controller and FETs, remove J6 and apply an
external power supply to power the FETs to P4 to between 3.0V
and 14V.
Apply a power supply voltage to the ZL9101M module through
the P2 connector.
If the VDD voltage is 4.5V ≤ VDD ≤ 5.5V, then apply 4.5V to 5.5V to
P2, and connect VR to VDD. Do not exceed 5.5V while VR is
connected to VDD or permanent damage will result.
If the VDD voltage is 5.5V ≤ VDD ≤ 14V, then apply 5.5V to 14V to
P2, and do not connect to VR.
The ZL9101EVAL1Z comes configured to use hardware Enable.
Toggle the power switch to the Enable position to power on. Use
the GUI to change the configuration, if desired.
Power Good
The ZL9101M provides a Power-Good (PG) signal, which indicates
that the output voltage is within a specified tolerance of its target
level and that no fault condition exists. By default, the PG pin
asserts if the output is within 10% of the target voltage. These
limits and the polarity of the pin may be changed via the
I2C/SMBus interface. See Application Note AN2033 for details.
A PG delay period is defined as the time from when all conditions
within the ZL9101M for asserting PG are met to when the PG pin
is actually asserted. This feature is commonly used instead of
using an external reset controller to control external digital logic.
By default, the ZL9101M PG delay is set equal to the soft-start
ramp time setting of 10ms. The PG delay may be set
independently of the soft-start ramp by using the I2C/SMBus as
described in Application Note AN2033.
AN1625.0
February 4, 2011
Application Note 1625
Switching Frequency and PLL
The ZL9101M incorporates an internal phase-locked loop (PLL) to
clock the internal circuitry. The PLL can be driven by an external
clock source connected to the SYNC pin via J7 or J14. When
using the internal oscillator, the SYNC pin can be configured as a
clock source.
The internal switching frequency of the ZL9101M is 615kHz.
Operation below 615kHz will increase the inductor ripple current
and cause permanent damage.
Loop Compensation
The ZL9101M operates as a voltage-mode synchronous buck
controller with a fixed frequency PWM scheme. The module is
internally compensated via the I2C/SMBus interface. The PID
settings are included in the configuration file stored on the
ZL9101M; the settings are shown in “Default Configuration File”
on page 6 for reference. The compensation tool, CompZL™ can
be used to generate appropriate PID settings for other circuit
configurations.
going negative, thus reducing energy losses and increasing
overall efficiency. Diode emulation is available to single-phase
devices only.
NOTE: The overall bandwidth of the device may be reduced when
in diode emulation mode. It is recommended that diode
emulation be disabled prior to applying significant load steps.
Input Undervoltage Lockout
The input undervoltage lockout (UVLO) prevents the ZL9101M
from operating when the input falls below a preset threshold,
indicating the input supply is out of its specified range. The UVLO
threshold (VUVLO) can be set between 2.85V and 16V using the
I2C/SMBus interface.
Once an input undervoltage fault condition occurs, the device
can respond in a number of ways as follows:
1. Continue operating without interruption.
2. Continue operating for a given delay period, followed by
shutdown if the fault still exists. The device remains in
shutdown until instructed to restart.
Adaptive Diode Emulation
Connectors and Jumpers
Adaptive diode emulation mode turns off the low-side FET gate
drive at low load currents to prevent the inductor current from
Connector and jumpers are shown in Figure 10.
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M1
ZL9101M
VIN
VIN=FET input voltage
3 V to 12V
VIN
VIN
15
C1
330u
16V
J1
VIN Monitor
1
2
C2
22uF
16V
VIN
VOUT
C10
680uF
6.3V
17
C3
22uF
16V
M1
C4
47uF
6.3V
C5
47uF
6.3V
C6
47uF
6.3V
C7
47uF
6.3V
C8
47uF
6.3V
C11
680uF
6.3V
C12
680uF
6.3V
VOUT
VOUT
C9
47uF
6.3V
FB+
FB-
VDD
VDD= ZL8100 supply voltage
VDD
3 V to 12V
VDD
XX2
12
VDD
FBFB+
XX3
J2
FBFB+
18
19
1
2
C13
10uF
25V
4
VDRV
J3
VDRV = ZL1505 driver supply voltage
VDRV
4.5V to 6.5V
VDRV
13
VOUT
ZL9101
Module
VDRV
C14
10uF
25V
VR
8
VR
C15
4.7uF
16V
SGND
C18
4.7uF
16V
PG_0
HW_EN
SCL
SDA
DDC
PG
SYNC
VTRK
PG_0
2
1
7
5
4
20
SCL
SDA
DDC
PG
SYNC
VTRK
V25
11
V25
EN
6
C17
0.1µF
25V
J13
SW
14
SW
SW
SW
1
2
3
C16
10uF
25V
EN
PGND
PGND
4
16
10
GND
Terminate SW Node to a floating
pad, for thermal relief
J14
SYNC
JP1
SA
3
R2
R3
R4
R5
R6
51.1K
56.2K
61.9K
68.1K
75.0K
Add.
0x2A
0x2B
0x2C
0x2D
0x2E
21
1
3
5
7
9
1
3
5
7
9
J5 Output Voltage Select
R1
100K
J4
J5
2
4
6
8
10
Ref Value
9
2
4
6
8
10
J4 Address Selection
SGND VSET
XX1
R2 R3 R4 R5 R6
Ref Value
Vout
R7 21.5K
R8 31.6K
R9 61.9K
R10 110K
R11 147K
1.00 V
1.20 V
1.80 V
2.50 V
3.30 V
R7 R8 R9 R10 R11
SG
FIGURE 2. ZL9101EVAL1Z CIRCUIT SCHEMATIC
SYNC
Application Note 1625
SCL
SDA
DDC
PG
SYNC
VTRK
SG
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February 4, 2011
VOUT
P1
Module Interface
+
VOUT
-
FB+
FBC19
100uF
6.3V
C20
100uF
6.3V
C21
100uF
6.3V
C22
100uF
6.3V
C23
100uF
6.3V
VDD
Vaux
P2
J6
R13
10.0K
1
VDD
2
VDD
Vi2c
R12
10.0K
SCL
5
SALRT
SDA
R14
10.0K
FROM PREQUEL
J7
2
1
4
3
6
5
8
7
10
9
SCL
SALRT
SDA
R15
10.0K
R16
4.75k
1
VTRK
DDC
MSTR_EN
SYNC
PG_0
MSTR_SYNC
TO SEQUEL
J10
2
1
4
3
6
5
8
7
10
9
4
3
2
VOUT 4
VOUT
VIN
1
R19
3.32K
VDRV
2
3
4
+
VDRV
-
3
C27
10uF
25V
R18
909
C28
22uF
16V
1
VIN
1
PIN
P3
VDRV
G-ADJ
1
C26
10uF
25V
VOUT
DDC
MSTR_EN
MSTR_SYNC
PG
SOCKET (5X2 RA)
6
2
J9
2
D2
SS10P4-M3/86A
P4
6
+
VIN
-
VIN
D4
ESDA6V1-4BC6
2
5
J11
2
1
2
3
5
3
C29
22uF
16V
2
2
D3
ESDA6V1-4BC6
J12
1
JACK_BARREL
1
D5
STPS20L45CG
Vi2c
Vaux
D6
GRN
C30
0.1u
SW2
SW_SPDT
Disable
Monitor
Enable
3
2
1
R23
49.9
R24
10.0K
MSTR_EN
R26
49.9
C34
1uF
25V
U3
SN74AUP1G17
10V
C35
0.1uF
10V
392
5
VCC
MSTR_EN_IN 2 A
R27
49.9
R20
Y 4
HW_EN
1 S1
D1
2 G1
G2 5
3 D2
S2 4
C31
10uF
25V
Vaux
D8
BAT54
2
VOUT 4
VOUT
VIN
R22
10.0K
G-ADJ
1
6
1 NC
GND
3
3
R21
392
Q2
FDG6301N
D7
BAT54
U2
REG1117A
VOUT
Q3
FDG6301N
1 S1
D1
6
D9
BAT54
1
R25
115
PG
2 G1
R28
187
FIGURE 3. ZL9101EVAL1Z INTERFACE SCHEMATIC
C36
10uF
25V
3 D2
G2 5
S2 4
6
S1
D1
G1
G2
D2
S2
2
5
3
4
Q1
FDG6304P
C32
0.1u
10V
C33
10u
25V
Application Note 1625
3
1
SYNC
PG_0
2
D1
SS10P4-M3/86A
VDRV
U1
REG1117A
J8
R17
49.9
HEADER (5X2 RA)
1
VTRK
DDC
+
VDD
-
3
C24
22uF
16V
C25
330u
16V
AN1625.0
February 4, 2011
Application Note 1625
Default Configuration File
The following text is loaded into the ZL9101M devices on the ZL9101EVAL1Z evaluation board as the default settings. This
configuration file can be loaded using the PowerNavigator™ software, ConfigCheck™ software, or a user-created application. The
# symbol denotes a comment line.
# Intersil ZL9101M 12/20/2010
# ZL Configuration File Revision 2
# Schematic revision level
# BOM revision level
# ZL Author
# Change log:
RESTORE_FACTORY
STORE_DEFAULT_ALL
STORE_USER_ALL
RESTORE_DEFAULT_ALL
MFR_ID
Intersil
MFR_MODEL
ZL9101EVAL1Z
MFR_REVISION
REV_2.0
MFR_LOCATION
Austin
MFR_DATE
12_20_2010
MFR_SERIAL
1p2V_15A
ON_OFF_CONFIG
0x1A
#VOUT_COMMAND
#VOUT_OV_FAULT_LIMIT
#VOUT_MAX
#VOUT_UV_FAULT_LIMIT
#VOUT_MARGIN_HIGH
#VOUT_MARGIN_LOW
#VOUT_DROOP
#POWER_GOOD_ON
5
#POWER_GOOD_DELAY
5
IOUT_SCALE
1.556
IOUT_CAL_OFFSET
-2.30
TON_DELAY
5
TON_RISE
5
TOFF_DELAY
5
TOFF_FALL
5
FREQUENCY_SWITCH
615
VOUT_OV_FAULT_RESPONSE
0x80
VOUT_UV_FAULT_RESPONSE
0x80
OVUV_CONFIG
0x80
IOUT_OC_FAULT_LIMIT
25
IOUT_AVG_OC_FAULT_LIMIT
25
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Application Note 1625
IOUT_UC_FAULT_LIMIT
-20
IOUT_AVG_UC_FAULT_LIMIT
-20
MFR_IOUT_OC_FAULT_RESPONSE
0x80
MFR_IOUT_UC_FAULT_RESPONSE
0x80
MFR_VMON_OV_FAULT_LIMIT
7.0
VMON_OV_FAULT_RESPONSE
0x80
MFR_VMON_UV_FAULT_LIMIT
4.5
VMON_UV_FAULT_RESPONSE
0x80
VIN_OV_WARN_LIMIT
14.3
VIN_OV_FAULT_LIMIT
14.5
VIN_OV_FAULT_RESPONSE
0x80
VIN_UV_WARN_LIMIT
4.2
VIN_UV_FAULT_LIMIT
4.0
VIN_UV_FAULT_RESPONSE
0x80
OT_WARN_LIMIT
110.0
OT_FAULT_LIMIT
125
OT_FAULT_RESPONSE
0x80
UT_WARN_LIMIT
-20
UT_FAULT_LIMIT
-40
UT_FAULT_RESPONSE
0x00
PID_TAPS
A=16133.25, B=-27119.00, C=10998.50
DEADTIME
0x3838
DEADTIME_CONFIG
0x8C06
DEADTIME_MAX
0x2828
MAX_DUTY
92
#TRACK_CONFIG
#XTEMP_SCALE
1.0
#XTEMP_OFFSET
10.0
MFR_CONFIG
0x8311
NLR_CONFIG
0x00000000
USER_CONFIG
0x0031
TEMPCO_CONFIG
0x28
MISC_CONFIG
0x8880
ISHARE_CONFIG
0x0000
INTERLEAVE
0x0000
SEQUENCE
0x0000
DDC_GROUP
0x00000000
DDC_CONFIG
0x0000
INDUCTOR
0.30
STORE_DEFAULT_ALL
RESTORE_DEFAULT_ALL
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Application Note 1625
FIGURE 4. TOP LAYER
FIGURE 5. INNER_1
8
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Application Note 1625
FIGURE 6. INNER_2
FIGURE 7. INNER_3
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Application Note 1625
FIGURE 8. INNER_4
FIGURE 9. BOTTOM
10
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Application Note 1625
FIGURE 10. PHOTO SHOWING JUMPERS AND CONNECTORS
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is
cautioned to verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
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