DATASHEET

X40626
®
64K, 8K x 8 Bit
Data Sheet
PRELIMINARY
March 28, 2005
Dual Voltage CPU Supervisor with 64K
Serial EEPROM
FN8119.0
• 2.7V to 5.5V power supply operation
• Available Packages
—14-lead SOIC
—14-lead TSSOP
FEATURES
• Dual voltage monitoring
—V2Mon operates independent of VCC
• Watchdog timer with selectable timeout intervals
• Low VCC detection and reset assertion
—Four standard reset threshold voltages
—User programmable VTRIP threshold
—Reset signal valid to VCC=1V
• Low power CMOS
—20µA max standby current, watchdog on
—1µA standby current, watchdog OFF
• 64Kbits of EEPROM
—64 byte page size
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2, all or 64, 128, 256 or 512
bytes of EEPROM array with programmable
Block Lock™ protection
• 400kHz 2-wire interface
—Slave addressing supports up to 4 devices on
the same bus
DESCRIPTION
The X40626 combines four popular functions, Power-on
Reset Control, Watchdog Timer, Dual Supply Voltage
Supervision, and Serial EEPROM Memory in one package. This combination lowers system cost, reduces
board space requirements, and increases reliability.
Applying power to the device activates the power-on
reset circuit which holds RESET active for a period of
time. This allows the power supply and oscillator to stabilize before the processor can execute code.
The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable timeout interval, the device activates the RESET signal. The
user selects the interval from three preset values. Once
selected, the interval does not change, even after cycling
the power.
BLOCK DIAGRAM
V2 Monitor
Logic
Watchdog Transition
Detector
WP
V2FAIL
+
VTRIP2
-
V2MON
Watchdog
Timer Reset
Protect Logic
RESET
Data
Register
Command
Decode &
Control
Logic
SCL
S0
S1
VCC Threshold
Reset logic
Status
Register
Block Lock Control
SDA
64KB
EEPROM
Array
VCC
+
VTRIP
1
-
Reset &
Watchdog
Timebase
Power-on and
Low Voltage
Reset
Generation
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X40626
The device’s low VCC detection circuitry protects the
user’s system from low voltage conditions, resetting the
system when VCC falls below the set minimum VCC trip
point. RESET is asserted until VCC returns to proper
operating level and stabilizes. Four industry standard
Vtrip thresholds are available. However, Intersil’s unique
circuits allow the threshold to be reprogrammed to meet
custom requirements or to fine-tune the threshold for
applications requiring higher precision.
The memory portion of the device is a CMOS Serial
EEPROM array with Intersil’s Block Lock™ Protection.
The array is internally organized as 64 bytes per page.
The device features an 2-wire interface and software protocol allowing operation on an I2C bus.
The device utilizes Intersil’s proprietary Direct Write™
cell, providing a minimum endurance of 100,000 page
write cycles and a minimum data retention of 100 years.
PIN CONFIGURATION
14 Pin SOIC/TSSOP
NC
S0
S1
NC
RESET
NC
VSS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VCC
NC
WP
V2MON
V2FAIL
SCL
SDA
PIN FUNCTION
Pin
Name
Function
1, 4, 6, 13
NC
No Internal Connections
2
S0
Device Select Input
3
S1
Device Select Input
5
RESET
7
VSS
Ground
8
SDA
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an
open drain output and may be wire ORed with other open drain or open collector outputs. This
pin requires a pull up resistor and the input buffer is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is HIGH) restarts the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog time-out
period results in RESET going active.
9
SCL
Serial Clock. The Serial Clock controls the serial bus timing for data input and output.
10
V2FAIL
V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than VTRIP2
and goes HIGH when V2MON exceeds VTRIP2. There is no power-up reset delay circuitry on
this pin. This circuit works independently from the Low VCC reset and battery switch circuits.
Connect V2FAIL to VSS when not used.
11
V2MON
V2 Voltage Monitor Input. When the V2MON input is less than the VTRIP2 voltage, V2FAIL
goes LOW. This input can monitor an unregulated power supply with an external resistor
divider or can monitor a second power supply with no external components. Connect V2MON
to VSS or VCC when not used. There is no hysteresis in the V2MON comparator circuits.
12
WP
Write Protect. WP HIGH used in conjunction with WPEN bit prevents writes to the control register.
14
VCC
Supply Voltage
Reset Output. RESET is an active LOW, open drain output which goes active whenever VCC
falls below the minimum VCC sense level. It will remain active until VCC rises above the minimum VCC sense level for typically 200ms. RESET goes active if the Watchdog Timer is
enabled and SDA remains either HIGH or LOW longer than the selectable Watchdog time-out
period. A falling edge on SDA, while SCL is HIGH, resets the Watchdog Timer. RESET goes
active on power-up and remains active for typically 200ms after the power supply
stabilizes.
2
FN8119.0
March 28, 2005
X40626
EEPROM INADVERTENT WRITE PROTECTION
PRINCIPLES OF OPERATION
Power-on Reset
Application of power to the X40626 activates a poweron Reset Circuit that pulls the RESET pin active. This
signal provides several benefits.
– It prevents the system microprocessor from starting
to operate with insufficient voltage.
– It prevents the processor from operating prior to stabilization of the oscillator.
– It allows time for an FPGA to download its configuration prior to initialization of the circuit.
– It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power-up.
When VCC exceeds the device VTRIP threshold value
for tPURST (200ms nominal) the circuit releases
RESET allowing the system to begin operation.
LOW VOLTAGE MONITORING
During operation, the X40626 monitors the VCC level
and asserts RESET if supply voltage falls below a preset minimum VTRIP. The RESET signal prevents the
microprocessor from operating in a power fail or
brownout condition. The RESET signal remains active
until the voltage drops below 1V. It also remains active
until VCC returns and exceeds VTRIP for 200ms.
WATCHDOG TIMER
The Watchdog Timer circuit monitors the microprocessor activity by monitoring the SDA and SCL pins. The
microprocessor must toggle the SDA pin HIGH to
LOW periodically, while SCL is HIGH (this is a start bit)
prior to the expiration of the watchdog time-out period to
prevent a RESET signal. The state of two nonvolatile
control bits in the Status Register determine the watchdog timer period. The microprocessor can change
these watchdog bits, or they may be “locked” by tying
the WP pin HIGH.
When RESET goes active as a result of a low voltage
condition or Watchdog Timer Time-Out, any inprogress communications are terminated. While
RESET is active, no new communications are allowed
and no non-volatile write operation can start. Non-volatile writes in-progress when RESET goes active are
allowed to finish.
Additional protection mechanisms are provided with
memory Block Lock and the Write Protect (WP) pin.
These are discussed elsewhere in this document.
VCC/V2MON THRESHOLD RESET PROCEDURE
The X40626 is shipped with a standard VCC threshold
(VTRIP) voltage. This value will not change over normal
operating and storage conditions. However, in applications where the standard VTRIP is not exactly right, or if
higher precision is needed in the VTRIP value, the
X40626 threshold may be adjusted. The procedure is
described below, and uses the application of a nonvolatile control signal.
Setting the VTRIP Voltage
This procedure is used to set the VTRIP to a higher or
lower voltage value. It is necessary to reset the trip
point before setting the new value.
The VCC and V2MON must be tied together during this
sequence.
To set the new VTRIP voltage, start by setting the WEL
bit in the control register, then apply the desired VTRIP
threshold voltage to the VCC pin and the programming
voltage, VP , to the WP pin and 2 byte address and 1
byte of “00” data. The stop bit following a valid write
operation initiates the VTRIP programming sequence.
Bring WP LOW to complete the operation.
Figure 1. Set VTRIP Level Sequence (VCC/V2MON = desired VTRIP values, WP = 12-15V when WEL bit set)
VP = 12-15V
WP
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
xxH*
00H
SCL
SDA
A0H
00H
*for VVTRIP2 address is 0DH
for VTRIP address is 01H
3
FN8119.0
March 28, 2005
X40626
To reset the new VTRIP voltage start by setting the
WEL bit in the control register, apply the desired VTRIP
threshold voltage to the VCC pin and the programming
voltage, VP , to the WP pin and 2 byte address and 1
byte of “00” data. The stop bit of a valid write operation
initiates the VTRIP programming sequence. Bring WP
LOW to complete the operation.
Resetting the VTRIP Voltage
This procedure is used to set the VTRIP to a “native”
voltage level. For example, if the current VTRIP is 4.4V
and the new VTRIP must be 4.0V, then the VTRIP must
be reset. When VTRIP is reset, the new VTRIP is something less than 1.7V. This procedure must be used to
set the voltage to a lower value.
Figure 2. Reset VTRIP Level Sequence (VCC/V2MON > 3V, WP = 12-15V, WEL bit set)
VP = 12-15V
WP
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
SCL
SDA
A0H
xxH*
00H
00H
*for VTRIP2 address is 0FH
for VTRIP address is 03H
Figure 3. Sample VTRIP Reset Circuit
VP
1
4.7K
RESET
VTRIP
Adj.
4
14
13
2
12
3
4
X40626
5
6
9
7
8
Adjust
µC
Run
SCL
SDA
FN8119.0
March 28, 2005
X40626
Figure 4. VTRIP Programming Sequence
VTRIPX Programming
Vx = VCC, V2MON
Let: MDE = Maximum Desired Error
No
Desired
VTRIPX
Present Value
MDE+
Acceptable
Desired Value
YES
Error Range
MDE–
Set VX = Desired VTRIPX
Error = Actual - Desired
Execute
Set Higher VTRIPX Sequence
New VX applied =
Old VX applied + | Error |
Execute
Set Higher VX Sequence
New VX applied =
Old VX applied - | Error |
Apply VCC and Voltage
> Desired VTRIPX to VX
Execute Reset VTRIPX
Sequence
NO
Decrease VX
Output Switches?
YES
Error < MDE–
Actual VTRIPX Desired VTRIPX
Error > MDE+
| Error | < | MDE |
DONE
5
FN8119.0
March 28, 2005
X40626
Control Register
BP2, BP1, BP0: Block Protect Bits - (Nonvolatile)
The Control Register provides the user a mechanism
for changing the Block Lock and Watchdog Timer settings. The Block Lock and Watchdog Timer bits are
nonvolatile and do not change when power is
removed.
The Block Protect Bits, BP2, BP1 and BP0, determine
which blocks of the array are write protected. A write to
a protected block of memory is ignored. The block protect bits will prevent write operations to one of eight
segments of the array.
0
000h - 03FH (64 bytes)
First Page (P1)
0
1
000h - 07FH (128 bytes)
First 2 pgs (P2)
1
1
0
000h - 0FFH (256 bytes)
First 4 pgs (P4)
1
1
1
000h - 1FFH (512 bytes)
First 8 Pgs (P8)
The state of the Control Register can be read at any
time by performing a random read at address FFFFh.
Only one byte is read by each register read operation.
The X40626 resets itself after the first byte is read.
The master should supply a stop condition to be consistent with the bus protocol, but a stop is not required
to end this operation.
7
6
5
4
3
2
1
0
WPEN WD1 WD0 BP1 BP0 RWEL WEL BP2
BP0
0
1
BP1
1
The user must issue a stop after sending this byte to
the register to initiate the nonvolatile cycle that stores
WD1, WD0, BP2, BP1, and BP0. The X40626 will not
acknowledge any data bytes written after the first byte
is entered.
BP2
The Control Register is accessed at address FFFFh. It
can only be modified by performing a byte write operation directly to the address of the register and only one
data byte is allowed for each register write operation.
Prior to writing to the Control Register, the WEL and
RWEL bits must be set using a two step process, with
the whole sequence requiring 3 steps. See "Writing to
the Control Register" below.
Protected Addresses
(Size)
0
0
0
None (factory setting)
0
0
1 1800h - 1FFFH (2K bytes)
0
1
0 1000h - 1FFFH (4K bytes) Upper 1/2 (Q3,Q4)
0
1
1 0000h - 1FFFH (8K bytes)
Array Lock
None
Upper 1/4 (Q4)
Full Array (All)
WD1, WD0: Watchdog Timer Bits
The bits WD1 and WD0 control the period of the
Watchdog Timer. The options are shown below.
WD1
WD0
Typ. Watchdog Time-out Period
0
0
1.4 Seconds
0
1
600 milliseconds
1
0
200 milliseconds
1
1
Disabled (factory setting)
RWEL: Register Write Enable Latch (Volatile)
Write Protect Enable
The RWEL bit must be set to “1” prior to a write to the
Control Register.
These devices have an advanced Block Lock scheme
that protects one of eight blocks of the array when
enabled. It provides hardware write protection through
the use of a WP pin and a nonvolatile Write Protect
Enable (WPEN) bit. Four of the 8 protected blocks
match the original Block Lock segments and this protection scheme is fully compatible with the current
devices using 2 bits of block lock control (assuming
the BP2 bit is set to 0).
WEL: Write Enable Latch (Volatile)
The WEL bit controls the access to the memory and to
the Register during a write operation. This bit is a volatile latch that powers up in the LOW (disabled) state.
While the WEL bit is LOW, writes to any address,
including any control registers will be ignored (no
acknowledge will be issued after the Data Byte). The
WEL bit is set by writing a “1” to the WEL bit and
zeroes to the other bits of the control register. Once
set, WEL remains set until either it is reset to 0 (by
writing a “0” to the WEL bit and zeroes to the other bits
of the control register) or until the part powers up
again. Writes to the WEL bit do not cause a nonvolatile
write cycle, so the device is ready for the next operation immediately after the stop condition.
6
The Write Protect (WP) pin and the Write Protect
Enable (WPEN) bit in the Control Register control the
programmable Hardware Write Protect feature. Hardware Write Protection is enabled when the WP pin and
the WPEN bit are HIGH and disabled when either the
WP pin or the WPEN bit is LOW. When the chip is
Hardware Write Protected, nonvolatile writes as well as
to the block protected sections in the memory array
cannot be written. Only the sections of the memory
array that are not block protected can be written. Note
that since the WPEN bit is write protected, it cannot be
changed back to a LOW state; so write protection is
enabled as long as the WP pin is held HIGH.
FN8119.0
March 28, 2005
X40626
Table 1. Write Protect Enable Bit and WP Pin Function
WP
WPEN
Memory Array not
Block Protected
Memory Array
Block Protected
Block Protect
Bits
WPEN Bit
Protection
LOW
X
Writes OK
Writes Blocked
Writes OK
Writes OK
Software
HIGH
0
Writes OK
Writes Blocked
Writes OK
Writes OK
Software
HIGH
1
Writes OK
Writes Blocked
Writes Blocked
Writes Blocked
Hardware
Writing to the Control Register
Changing any of the nonvolatile bits of the control register requires the following steps:
– Write a 02H to the Control Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation proceeded by a start and ended with a stop).
– Write a 06H to the Control Register to set both the
Register Write Enable Latch (RWEL) and the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation proceeded by a start
and ended with a stop).
– Write a value to the Control Register that has all the
control bits set to the desired state. This can be represented as 0xys t01r in binary, where xy are the
WD bits, and rst are the BP bits. (Operation preceeded by a start and ended with a stop). Since this
is a nonvolatile write cycle it will take up to 10ms to
complete. The RWEL bit is reset by this cycle and
the sequence must be repeated to change the nonvolatile bits again. If bit 2 is set to ‘1’ in this third step
(0xys t11r) then the RWEL bit is set, but the WD1,
WD0, BP2, BP1 and BP0 bits remain unchanged.
Writing a second byte to the control register is not
allowed. Doing so aborts the write operation and
returns a NACK.
– A read operation occurring between any of the previous operations will not interrupt the register write
operation.
7
– The RWEL bit cannot be reset without writing to the
nonvolatile control bits in the control register, power
cycling the device or attempting a write to a write
protected block.
To illustrate, a sequence of writes to the device consisting of [02H, 06H, 02H] will reset all of the nonvolatile bits in the Control Register to 0. A sequence of
[02H, 06H, 06H] will leave the nonvolatile bits
unchanged and the RWEL bit remains set.
SERIAL INTERFACE
Serial Interface Conventions
The device supports a bidirectional bus oriented protocol. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data
transfers, and provides the clock for both transmit and
receive operations. Therefore, the devices in this family operate as slaves in all applications.
Serial Clock and Data
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 5.
FN8119.0
March 28, 2005
X40626
Figure 5. Valid Data Changes on the SDA Bus
SCL
SDA
Data Stable
Data Change
Data Stable
Serial Start Condition
Serial Stop Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL
is HIGH. The device continuously monitors the SDA
and SCL lines for the start condition and will not
respond to any command until this condition has been
met. See Figure 6.
All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the device into the Standby power mode after a read
sequence. A stop condition can only be issued after the
transmitting device has released the bus. See Figure 6.
Figure 6. Valid Start and Stop Conditions
SCL
SDA
Start
Serial Acknowledge
Acknowledge is a software convention used to indicate successful data transfer. The transmitting device,
either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Refer to Figure 7.
The device will respond with an acknowledge after
recognition of a start condition and if the correct
Device Identifier and Select bits are contained in the
Slave Address Byte. If a write operation is selected,
the device will respond with an acknowledge after the
receipt of each subsequent eight bit word. The device
will acknowledge all incoming data and address bytes,
except for the Slave Address Byte when the Device
Identifier and/or Select bits are incorrect.
8
Stop
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. The device will terminate
further data transmissions if an acknowledge is not
detected. The master must then issue a stop condition
to return the device to Standby mode and place the
device into a known state.
FN8119.0
March 28, 2005
X40626
Figure 7. Acknowledge Response From Receiver
SCL from
Master
1
8
9
Data Output
from
Data Output
from Receiver
Start
Acknowledge
Serial Write Operations
Byte Write
For a write operation, the device requires the Slave
Address Byte and a Word Address Byte. This gives the
master access to any one of the words in the array. After
receipt of the Word Address Byte, the device responds
with an acknowledge, and awaits the next eight bits of
data. After receiving the 8 bits of the Data Byte, the
device again responds with an acknowledge. The master
then terminates the transfer by generating a stop condition, at which time the device begins the internal write
cycle to the nonvolatile memory. During this internal write
cycle, the device inputs are disabled, so the device will
not respond to any requests from the master. The SDA
output is at high impedance. See Figure 8.
Figure 8. Byte Write Sequence
S
T
A
R
T
Signals from
the Master
Word Address
Byte 1
Slave
Address
Word Address
Byte 0
S
T
O
P
Data
S 1 0 1 0 0 S1 S0 0
SDA Bus
P
A
C
K
Signals from
the Slave
A write to a protected block of memory will suppress
the acknowledge bit.
Page Write
The device is capable of a page write operation. It is
initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the
first data byte is transferred, the master can transmit
an unlimited number of 8-bit bytes. After the receipt of
each byte, the device will respond with an acknowledge, and the address is internally incremented by
one. The page address remains constant. When the
9
A
C
K
A
C
K
A
C
K
counter reaches the end of the page, it “rolls over” and
goes back to ‘0’ on the same page. This means that
the master can write 64 bytes to the page starting at
any location on that page. If the master begins writing
at location 60, and loads 12 bytes, then the first 4
bytes are written to locations 60 through 63, and the
last 8 bytes are written to locations 0 through 7. Afterwards, the address counter would point to location 8 of
the page that was just written. If the master supplies
more than 64 bytes of data, then new data over-writes
the previous data, one byte at a time.
FN8119.0
March 28, 2005
X40626
Figure 9. Page Write Operation
(I ≤ n ≤ 63)
Signals from
the Master
SDA Bus
S
T
A
R
T
Data
(0)
Word Address
Byte 0
Word Address
Byte 1
Slave
Address
Data
(n)
S
T
O
P
S 1 0 1 0 0 S1 S0 0
P
A
C
K
Signals from
the Slave
A
C
K
A
C
K
A
C
K
A
C
K
Figure 10. Writing 12 bytes to a 64-byte page starting at location 60 (Wrap around).
8 Bytes
address
=7
4 Bytes
address pointer
ends here
Addr = 8
The master terminates the Data Byte loading by issuing
a stop condition, which causes the device to begin the
nonvolatile write cycle. As with the byte write operation,
all inputs are disabled until completion of the internal
write cycle. See Figure 9 for the address, acknowledge,
and data transfer sequence.
Stops and Write Modes
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte plus the subsequent ACK signal. If a stop is
issued in the middle of a data byte, or before 1 full
data byte plus its associated ACK is sent, then the
device will reset itself without performing the write. The
contents of the array will not be effected.
10
address
60
address
63
Acknowledge Polling
The disabling of the inputs during nonvolatile cycles
can be used to take advantage of the typical 5mS write
cycle time. Once the stop condition is issued to indicate the end of the master’s byte load operation, the
device initiates the internal nonvolatile cycle. Acknowledge polling can be initiated immediately. To do this,
the master issues a start condition followed by the
Slave Address Byte for a write or read operation. If the
device is still busy with the nonvolatile cycle then no
ACK will be returned. If the device has completed the
write operation, an ACK will be returned and the host
can then proceed with the read or write operation.
Refer to the flow chart in Figure 11.
FN8119.0
March 28, 2005
X40626
Figure 11. Acknowledge Polling Sequence
Serial Read Operations
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the Slave Address Byte is set to one. There are three
basic read operations: Current Address Reads, Random Reads, and Sequential Reads.
Byte load completed
by issuing STOP.
Enter ACK Polling
Issue START
Current Address Read
Issue Slave Address
Byte (Read or Write)
Internally the device contains an address counter that
maintains the address of the last word read incremented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n+1. On power-up, the address in the
address counter is 00H.
Issue STOP
NO
ACK
returned?
Upon receipt of the Slave Address Byte with the R/W bit
set to one, the device issues an acknowledge and then
transmits the eight bits of the Data Byte. The master
terminates the read operation when it does not respond
with an acknowledge during the ninth clock and then
issues a stop condition. Refer to Figure 12 for the
address, acknowledge, and data transfer sequence.
YES
Nonvolatile Cycle
complete. Continue
command sequence?
NO
Issue STOP
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
YES
Continue Normal
Read or Write
Command Sequence
PROCEED
Figure 12. Current Address Read Sequence
Signals from
the Master
SDA Bus
Signals from
the Slave
11
S
t
a
r
t
Slave
Address
S
t
o
p
1 0 1 0 0 S1 S0 1
A
C
K
Data
FN8119.0
March 28, 2005
X40626
Random Read
Random read operation allows the master to access
any memory location in the array. Prior to issuing the
Slave Address Byte with the R/W bit set to one, the
master must first perform a “dummy” write operation.
The master issues the start condition and the Slave
Address Byte, receives an acknowledge, then issues
the Word Address Bytes. After acknowledging receipts
of the Word Address Bytes, the master immediately
issues another start condition and the Slave Address
Byte with the R/W bit set to one. This is followed by an
acknowledge from the device and then by the eight bit
word. The master terminates the read operation by not
responding with an acknowledge and then issuing a
stop condition. Refer to Figure 13 for the address,
acknowledge, and data transfer sequence.
Figure 13. Random Address Read Sequence
Signals from
the Master
SDA Bus
S
T
A
R
T
Word Address
Byte 1
Slave
Address
S
T
A
R
T
Word Address
Byte 0
S 1 0 1 0 0 S1 S0 0
S 1 0 1 0 0 S1 S0 1
A
C
K
Signals from
the Slave
S
T
O
P
Slave
Address
A
C
K
There is a similar operation, called “Set Current
Address” where the device does no operation, but
enters a new address into the address counter if a
stop is issued instead of the second start shown in Figure 13. The device goes into standby mode after the
stop and all bus activity will be ignored until a start is
detected. The next Current Address Read operation
reads from the newly loaded address. This operation
could be useful if the master knows the next address it
needs to read, but is not ready for the data.
A
C
K
P
A
C
K
Data
The data output is sequential, with the data from address
n followed by the data from address n + 1. The address
counter for read operations increments through all page
and column addresses, allowing the entire memory contents to be serially read during one operation. At the end
of the address space the counter “rolls over” to address
0000H and the device continues to output data for each
acknowledge received. Refer to Figure 14 for the
acknowledge and data transfer sequence.
Sequential Read
Sequential reads can be initiated as either a current
address read or random address read. The first Data
Byte is transmitted as with the other modes; however,
the master now responds with an acknowledge, indicating it requires additional data. The device continues to
output data for each acknowledge received. The master
terminates the read operation by not responding with an
acknowledge and then issuing a stop condition.
12
FN8119.0
March 28, 2005
X40626
Figure 14. Sequential Read Sequence
Signals from
the Master
SDA Bus
Slave
Address
A
C
K
S
t
o
p
A
C
K
A
C
K
S1 S0 1
A
C
K
Signals from
the Slave
Data
(1)
Data
(2)
Data
(n-1)
Data
(n)
(n is any integer greater than 1)
X40626 Addressing
Slave Address Byte
Following a start condition, the master must output a
Slave Address Byte. This byte consists of several
parts:
– a device type identifier that is ‘1010’ to access the
array
– one bit of ‘0’.
– next two bits are the device address. (S1 and S0)
– After loading the entire Slave Address Byte from the
SDA bus, the device compares the input slave byte
data to the proper slave byte. Upon a correct compare,
the device outputs an acknowledge on the SDA line.
Word Address
The word address is either supplied by the master or
obtained from an internal counter. The internal counter
is 00H on a power-up condition.
The master must supply the two word address byte as
shown in Figure 15.
– one bit of the slave command byte is a R/W bit. The
R/W bit of the Slave Address Byte defines the operation to be performed. When the R/W bit is a one,
then a read operation is selected. A zero selects a
write operation. Refer to Figure 15.
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X40626
Figure 15. X40626 Addressing
Device Identifier
1
0
1
Device Select
0
0
S1
S0
R/W
Slave Address Byte
High Order Word Address
A15
A14
A13
A12
A11
A10
A9
A8
A1
A0
D1
D0
Word Address Byte 1
Low Order Word Address
A7
A6
A5
A4
A3
A2
Word Address Byte 0
D7
D6
D5
D4
D3
D2
Data Byte
Operational Notes
The device powers-up in the following state:
– The device is in the low power standby state.
– The WEL bit is set to ‘0’. In this state it is not possible to write to the device.
– SDA pin is in the input mode.
– Communication to the device is inhibited while
RESET is active and any in-progress communication is terminated.
– Block Lock bits can protect sections of the memory
array from write operations.
Symbol Table
– RESET Signal is active for tPURST.
WAVEFORM
INPUTS
OUTPUTS
The following circuitry has been included to prevent
inadvertent writes:
Must be
steady
Will be
steady
– The WEL bit must be set to allow write operations.
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
Data Protection
– The proper clock count and bit sequence is required
prior to the stop bit in order to start a nonvolatile
write cycle.
– A three step sequence is required before writing into
the Control Register to change Watchdog Timer or
Block Lock settings.
– The WP pin, when held HIGH, and WPEN bit at logic
HIGH will prevent all writes to the Control Register.
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X40626
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias ................... -65°C to +135°C
Storage temperature ........................ -65°C to +150°C
Voltage on any pin with respect to VSS... -1.0V to +7V
D.C. output current (sink) ................................... 10mA
Lead temperature (soldering, 10 seconds) ........ 300°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 2. Recommended Operating Conditions
Temp
Commercial
Industrial
Min.
0°C
-40°C
Max.
70°C
+85°C
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
VCC = 2.7 to 5.5V
Symbol
Parameter
Min
Max
Unit
Test Conditions
VIL = VCC x 0.1, VIH = VCC x 0.9
fSCL = 400kHz, SDA = Open
ICC1(1)
Active Supply Current Read
1.0
mA
ICC2(2)
Active Supply Current Write
3.0
mA
ISB1(2)
Standby Current DC (WDT off)
1
µA
VSDA=VSCL=VCC
Others=GND or VCC
ISB2(3)
Standby Current DC (WDT on)
30
µA
VSDA=VSCL=VCC
Others=GND or VCC
ILI
Input Leakage Current
10
µA
VIN = GND to VCC
ILO
Output Leakage Current
10
µA
VSDA = GND to VCC
Device is in Standby
VIL
Input LOW Voltage
-1
VCC x 0.3
V
VIH
Input HIGH Voltage
VCC x 0.7
VCC +0.5
V
VHYS
Schmitt Trigger Input Hysteresis
Fixed input level
VCC related level
0.2
.05 x VCC
VOL
Output LOW Voltage
V
V
0.4
V
IOL = 1.0mA (VCC=3V)
IOL = 3.0mA (VCC=5V)
Notes: (1) The device enters the Active state after any start, and remains active until: (a) 9 clock cycles later if the Device Select Bits in the Slave
Address Byte are incorrect; or (b) 200nS after a stop ending a read operation.
(2) The device enters the Active state after any start, and remains active until tWC after a stop ending a write operation.
(3) The device goes into Standby: (a) 200nS after any stop, except those that initiate a nonvolatile write cycle; or (b) tWC after a stop that
initiates a nonvolatile cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address
Byte.
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X40626
CAPACITANCE (TA = 25°C, f = 1.0 MHz, VCC = 5V)
Symbol
Parameter
(4)
COUT
CIN
(4)
Max.
Units
Test Conditions
Output Capacitance (SDA, RESET, V2FAIL)
8
pF
VOUT = 0V
Input Capacitance (SCL, WP, S0, S1)
6
pF
VIN = 0V
Notes: (4) This parameter is periodically sampled and not 100% tested.
EQUIVALENT A.C. LOAD CIRCUIT
5V
A.C. TEST CONDITIONS
V2MON
1.53kΩ
1533Ω
SDA
RESET
Input pulse levels
0.1VCC to 0.9VCC
Input rise and fall times
10ns
Input and output timing levels
0.5VCC
Output load
Standard Output Load
V2FAIL
30pF
30pF
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Symbol
Parameter
Min.
Max.
Units
400
kHz
fSCL
SCL Clock Frequency
0
tIN
Pulse width Suppression Time at inputs
50
tAA
SCL LOW to SDA Data Out Valid
0.1
tBUF
Time the bus free before start of new transmission
1.3
µs
tLOW
Clock LOW Time
1.3
µs
tHIGH
Clock HIGH Time
0.6
µs
tSU:STA
Start Condition Setup Time
0.6
µs
tHD:STA
Start Condition Hold Time
0.6
µs
tSU:DAT
Data In Setup Time
100
ns
tHD:DAT
Data In Hold Time
0
µs
tSU:STO
Stop Condition Setup Time
0.6
µs
tDH
Data Output Hold Time
50
ns
SDA and SCL Rise Time
20 +
0.1Cb(2)
300
ns
20 +
0.1Cb(2)
300
ns
tR
ns
0.9
µs
tF
SDA and SCL Fall Time
tSU:WP
WP Setup Time
0.6
µs
tHD:WP
WP Hold Time
0
µs
Cb
Capacitive load for each bus line
400
pF
Notes: (1) Typical values are for TA = 25°C and VCC = 5.0V
(2) Cb = total capacitance of one bus line in pF.
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X40626
TIMING DIAGRAMS
Bus Timing
tF
tHIGH
SCL
tR
tLOW
tSU:DAT
tSU:STA
SDA IN
tHD:DAT
tHD:STA
tSU:STO
tAA
tDH
tBUF
SDA OUT
WP Pin Timing
START
SCL
Clk 1
Clk 9
Slave Address Byte
SDA IN
tSU:WP
WP
tHD:WP
Write Cycle Timing
SCL
SDA
8th bit of Last Byte
ACK
tWC
Stop
Condition
Start
Condition
Nonvolatile Write Cycle Timing
Symbol
tWC
Parameter
(1)
Write Cycle Time
Min.
Typ.(1)
Max.
Units
5
10
mS
Notes: (1) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is
the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
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March 28, 2005
X40626
Power-Up and Power-Down Timing
VTRIP/VTRIP2
VCC/V2MON
tPURST
0 Volts
tPURST
tR
tF
tRPD
VRVALID
RESET/V2FAIL
RESET Output Timing
Symbol
tPURST
tRPD(8)
tF(8)
tR
(8)
VRVALID(8)
VTRIP Range
Parameter
Power-up Reset Timeout
VCC Detect to Reset/Output (Falling Edge)
VCC/V2MON Fall Time
VCC/V2MON Rise Time
Reset Valid VCC or V2FAIL Valid V2MON
Voltage Range over which VTRIP/VTRIP2 can be set
Min.
100
Typ.
200
Max.
400
500
Units
ms
ns
µs
µs
V
V
100
100
1.0
2.0
VCC
Notes: (8) This parameter is periodically sampled and not 100% tested.
SDA vs. RESET Timing
Start
Start
tRSP
< tWDO
SCL
Timer Start
SDA
tRST
tWDO
tRST
RESET
Timer Start
18
Timer
Restart
FN8119.0
March 28, 2005
X40626
RESET Output Timing
Symbol
Parameter
tWDO
Watchdog Timeout Period,
WD1 = 1, WD0 = 1 (factory setting)
WD1 = 1, WD0 = 0
WD1 = 0, WD0 = 1
WD1 = 0, WD0 = 0
Reset Timeout
tRST
Min.
Typ.
Max.
Units
Disabled
100
450
1.0
Disabled
200
600
1.4
Disabled
400
850
2.0
Factory Setting
ms
ms
sec
100
250
400
ms
VTRIP Programming Timing Diagram (WEL = 1)
VCC/V2MON
VCC/V2MON
(VTRIP/VTRIP2)
tTSU
tTHD
VP
WP
tVPS
tVPO
01 2
7
0
7
0
7
0
7
SCL
data
SDA
AS1S000h
Start
19
0001H*: set VTRIP
000DH: set VTRIP2
0003H: Resets VTRIP
000FH: Resets VTRIP2
00h
tWC
FN8119.0
March 28, 2005
X40626
Packaging Information
14-Lead Plastic Small Outline Gullwing Package Type S
0.150 (3.80) 0.228 (5.80)
0.158 (4.00) 0.244 (6.20)
Pin 1 Index
Pin 1
0.014 (0.35)
0.020 (0.51)
0.336 (8.55)
0.345 (8.75)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.10)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
0.020 (0.50)
0.050" Typical
X 45°
0.050" Typical
0° - 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
FOOTPRINT
0.030" Typical
14 Places
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
20
FN8119.0
March 28, 2005
X40626
PACKAGING INFORMATION
14-Lead Plastic, TSSOP, Package Code V14
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.193 (4.9)
.200 (5.1)
.041 (1.05)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° - 8°
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
21
FN8119.0
March 28, 2005
X40626
Ordering Information
VCC Range
VTRIP Range
VTRIP2
Range
4.5-5.5V
4.5-4.75
2.85-3.0
Package
Operating
Temperature
Range
Part Number RESET
(Active LOW)
Park
Mark
14L SOIC
0°C-70°C
X40626S14-4.5A
AL
-40°C-85°C
X40626S14I-4.5A
AM
0°C-70°C
X40626V14-4.5A
AL
-40°C-85°C
X40626V14I-4.5A
AM
14L TSSOP
4.5-5.5V
4.25-4.5
2.85-3.0
14L SOIC
14L TSSOP
2.7-5.5V
2.85-3.0
2.15-2.30
14L SOIC
14LTSSOP
2.7-5.5V
2.55-2.7
2.55-2.7
14L SOIC
14L TSSOP
0°C-70°C
X40626S14
blank
-40°C-85°C
X40626S14I
I
0°C-70°C
X40626V14
blank
-40°C-85°C
X40626V14I
I
0°C-70°C
X40626S14-2.7A
AN
-40°C-85°C
X40626S14I-2.7A
AP
0°C-70°C
X40626V14-2.7A
BN
-40°C-85°C
X40626V14I-2.7A
AP
0°C-70°C
X40626S14-2.7
F
-40°C-85°C
X40626S14I-2.7
G
0°C-70°C
X40626V14-2.7
F
-40°C-85°C
X40626V14I-2.7
G
PART MARK INFORMATION
14-Lead SOIC/TSSOP
X40626 X
YYWWXX
S = SOIC
V = TSSOP
XX – Part Mark
WW – Workweek
YY – Year
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
22
FN8119.0
March 28, 2005
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