DATASHEET

ISL88031
®
Data Sheet
June 9, 2009
FN8227.2
Quintuple Voltage Monitor
Features
The ISL88031 is a quintuple voltage-monitoring supervisor
combining competitive reset threshold accuracy and low
power consumption. This device combines popular functions
such as Power-On Reset, Undervoltage Supply Supervision,
reset signaling and Manual Reset. Monitoring up to five
different voltages in a small 8 Ld MSOP package, the
ISL88031 devices can help to lower system cost, reduce
board space requirements, and increase the reliability of
multi-voltage systems.
• Quintuple Voltage Monitoring
Low VDD detection circuitry protects the user’s system from
low voltage conditions, resetting the system when VDD or
any of the other monitored power supply voltages fall below
their respective minimum voltage thresholds. The reset
signal remains asserted until all of these voltages return to
proper operating levels and stabilize.
• Accurate ±1.8% Voltage Threshold
With two of the five voltage monitors being preset for
common supplies, users can adjust the threshold voltages of
the third, fourth, and fifth voltage monitors in order to meet
specific system level requirements.
• Fixed-Voltage Options Allow Precise Monitoring of +5.0V,
+3.3V, +3.0V, +2.5V and +1.8V Power Supplies
• Adjustable Voltage Inputs Monitor Voltages > 0.6V
• 120ms Nominal Reset Pulse Width
• Manual Reset Capability
• Reset Signals Valid Down to VDD = 1V
• Immune to Power-Supply Transients
• Low 19µA Maximum Supply Current at 5V
• Pb-Free (RoHS Compliant)
Applications
• Telecom and Datacom Systems
• Routers and Servers
• Access Concentrators
Pinout
• Cable/Satellite Applications
ISL88031
(8 LD MSOP)
TOP VIEW
• Desktop and Notebook Computer Systems
• Data Storage Equipment
MR
1
8
RST
VDD
2
7
V5MON
V2MON
3
6
V4MON
GND
4
5
V3MON
• Set-Top Boxes
• Industrial Equipment
• Multi-Voltage Systems
Ordering Information
PART NUMBER
(Notes 1, 2)
PART MARKING
VTH1
VTH2
TEMP RANGE (°C)
PACKAGE
(Pb-free)
PKG. DWG. #
ISL88031IU8HFZ
AMA
4.634V
3.078V
-40 to +85
8 Ld MSOP
M8.118
ISL88031IU8HEZ
ANZ
4.634V
2.955V
-40 to +85
8 Ld MSOP
M8.118
ISL88031IU8HCZ
APR
4.634V
2.333V
-40 to +85
8 Ld MSOP
M8.118
ISL88031IU8HAZ
APS
4.634V
1.683V
-40 to +85
8 Ld MSOP
M8.118
ISL88031IU8ECZ
APT
2.866V
2.333V
-40 to +85
8 Ld MSOP
M8.118
ISL88031IU8EAZ
APZ
2.866V
1.683V
-40 to +85
8 Ld MSOP
M8.118
NOTES:
1. Add “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006, 2008, 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL88031
Pin Descriptions
PIN NUMBER
PIN NAME
FUNCTION
1
MR
Active-Low Open Drain Manual Reset Input with internal pull-up resistor
2
VDD
Chip Bias Input and integrated preset undervoltage monitor
3
V2MON
4
GND
5
V3MON
Adjustable Third Undervoltage Monitor Input
6
V4MON
Adjustable Fourth Undervoltage Monitor Input
7
V5MON
Adjustable Fifth Undervoltage Monitor Input
8
RST
Second Preset Undervoltage Monitor Input
Ground
Active-Low Open Drain Reset Output
Functional Block Diagram
VDD
MR
POR
PB
± VREF
V2MON
RST
± VREF
V4MON
V3MON
± VREF
VREF
±
V5MON
GND
VREF ±
2
FN8227.2
June 9, 2009
ISL88031
Absolute Maximum Ratings
Thermal Information
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Voltage on any Pin With Respect to Gnd. . . . . . . . . . . . -1.0V to +7V
DC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Thermal Resistance (Typical, Note 3)
θJA (°C/W)
8 Ld MSOP Package . . . . . . . . . . . . . . . . . . . . . . . .
175
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Operating Temperature Range (Industrial) . . . . . . . .-40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
3. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
Over the recommended operating conditions, unless otherwise specified. Parameters with MIN and/or MAX
limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
SYMBOL
PARAMETER
TEST CONDITIONS
VDD
Supply Voltage Range
IDD1
VDD Supply Current
VDD = 5.0V
IDD2
V2MON Input Current
IDDA
V3MON, V4MON, V5MON Input Current
MIN
TYP
2.0
MAX UNITS
5.5
V
14
19
µA
V2MON = 3.3V
5.5
7
µA
V3MON, V4MON, V5MON = 1.0V
19
100
nA
VOLTAGE THRESHOLDS
VTH1
ISL88031IU8HxZ Fixed Voltage Trip Point for VDD
ISL88031IU8ExZ Fixed Voltage Trip Point for VDD
VTH1HYST
VTH2
Hysteresis of VTH1
ISL88031IU8xFZ Fixed Voltage Trip Point for V2MON
ISL88031IU8xEZ Fixed Voltage Trip Point for V2MON
ISL88031IU8xCZ Fixed Voltage Trip Point for V2MON
ISL88031IU8xAZ Fixed Voltage Trip Point for V2MON
3
+25°C
4.550
4.634 4.717
V
0°C to +70°C
4.461
4.634 4.807
V
-40°C to +85°C
4.453
4.634 4.815
V
+25°C
2.814
2.866 2.917
V
0°C to +70°C
2.759
2.866 2.973
V
40°C to +85°C
2.754
2.866 2.978
V
VTH1 = 4.64V
46
mV
VTH1 = 2.90V
29
mV
+25°C
3.022
3.078 3.133
V
0°C to +70°C
2.963
3.078 3.193
V
-40°C to +85°C
2.958
3.078 3.198
V
+25°C
2.901
2.955 3.008
V
0°C to +70°C
2.845
2.955 3.065
V
-40°C to +85°C
2.840
2.955 3.070
V
+25°C
2.291
2.333 2.375
V
0°C to +70°C
2.246
2.333 2.420
V
-40°C to +85°C
2.242
2.333 2.424
V
+25°C
1.652
1.683 1.713
V
0°C to +70°C
1.620
1.683 1.746
V
-40°C to +85°C
1.617
1.683 1.749
V
FN8227.2
June 9, 2009
ISL88031
Electrical Specifications
Over the recommended operating conditions, unless otherwise specified. Parameters with MIN and/or MAX
limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested. (Continued)
SYMBOL
VTH2HYST
VREF
VREFHYST
PARAMETER
Hysteresis of VTH2
VTH for V3MON, V4MON, V5MON Adj. Reset Threshold
Voltage
TEST CONDITIONS
MIN
TYP
MAX UNITS
VTH2 = 3.09V
37
mV
VTH2 = 2.92V
29
mV
VTH2 = 2.32V
23
mV
VTH2 = 1.69V
17
mV
+25°C
0.589
0.600 0.611
V
0°C to +70°C
0.578
0.600 0.622
V
-40°C to +85°C
0.577
0.600 0.623
V
Hysteresis Voltage
3
mV
RESET
VOL
Reset Output Voltage Low
tRPD
VTH to Reset Asserted Delay
tPOR
POR Timeout Delay
CLOAD
VDD ≥ 3.3V, Sinking 2.5mA
0.05
0.40
V
VDD < 3.3V, Sinking 1.5mA
0.05
0.40
V
6
80
Load Capacitance on Reset Pins
120
µs
180
5
ms
pF
MANUAL RESET
VMRL
MR Input Voltage Low
VMRH
MR Input Voltage High
tMR
MR Minimum Pulse Width
RPU
Internal Pull-Up Resistor
Pin Descriptions
0.8
V
VDD - 0.6
V
550
ns
10
kΩ
V2MON
RST
The RST output is an open drain output, which is asserted
low whenever:
1. the device is initially powered up to 1V or,
2. VDD, V2MON, V3MON, V4MON, or V5MON fall below
their minimum voltage sense level.
MR
The MR input is an active low debounced input to which a
user can connect a push-button to add manual reset
capability or use a signal to pull low. MR has an internal
pull-up resistor.
VDD
The VDD pin is the IC power supply terminal. The voltage at
this pin is compared against an internal factory-programmed
voltage trip point, VTH1. RST is first asserted low when the
device is initially powered and VDD < 1V and then at any
time thereafter when VDD falls below VTH1. The device is
designed with hysteresis to help prevent chattering due to
noise and is immune to brief power-supply transients.
4
The V2MON input is the second preset monitored voltage
that causes the RST output to go low when the voltage on
V2MON falls below VTH2.
V3MON, V4MON, and V5MON
The VxMON inputs provide monitoring and UV compliance
of three additional voltages through resistor dividers. A reset
is issued on the ISL88031 if the voltage on any VxMON falls
below the internal VREF of 0.6V.
Principles of Operation
The ISL88031 device provides those functions needed for
monitoring critical voltages, such as power-supply and battery
functions in microprocessor systems. It provides such features
as Power-On Reset control, Supply Voltage Supervision, and
Manual Reset Assertion. The integration of all these features
along with competitive reset threshold accuracy and low power
consumption, makes the ISL88031 device suitable for a wide
FN8227.2
June 9, 2009
ISL88031
Manual Reset
variety of applications needing multi-voltage monitoring.
See Figure 1 for the typical application diagram..
RST
VDD
V2MON
V3MON
ISL88031
MR
PB
V4MON
RESET
SIGNAL
The manual-reset input (MR) allows the user to trigger a reset
by using a push-button switch or by signaling the input low. The
MR input is an active low debounced input. Reset is asserted if
the MR pin is pulled low to less than 100mV for the minimum
MR pulse width or longer while the push-button is closed. After
MR is released, the reset output remains asserted low for tPOR
(200ms) and then is released.
Figures 2 and 3 illustrate the ISL88031’s operation. Figure 4
shows the ISL88031EVAL1, the evaluation platform for this
family of voltage monitors. Figures 5 and 6 illustrate the RST
output response times.
V5MON
GND
The ISL88031EVAL1 and Applications
FIGURE 1. TYPICAL APPLICATION DIAGRAM
Low Voltage Monitoring
During normal operation, the ISL88031 monitors the voltage
levels of VDD, V2MON, V3MON, V4MON, and V5MON. If the
voltage on any of these five inputs falls below their respective
voltage trip points, a reset is asserted (RST = low) to prevent
the microprocessor from operating during a power failure or
brownout condition. This reset signal remains low until the
voltages exceeds the voltage threshold settings for the reset
time delay period tPOR.
The ISL88031 allows users to customize the minimum voltage
sense level for three of the five monitored voltages. For
example, the user can adjust the voltage input trip point (VTRIP)
for V3MON, V4MON and V5MON inputs. To do this, connect
an external resistor divider network to the VxMON pin in order
to set the trip point to some other voltage above 600mV
according to Equation 1:
V TRIP = 0.6V × R 1 + R 2 / R 2
(EQ. 1)
Power-On Reset (POR)
Applying power to the ISL88031 activates a POR circuit, which
makes the reset pin(s) active (i.e. RST goes high while RST
goes low). These signals provide several benefits:
• It prevents the system microprocessor from starting to
operate with insufficient voltage.
• It prevents the processor from operating prior to stabilization
of the oscillator.
• It ensures that the monitored device is held out of operation
until internal registers are properly loaded.
• It allows time for an FPGA to download its configuration prior
to initialization of the circuit.
The reset signal remains active until VDD rises above the
minimum voltage sense level for time period tPOR. This
ensures that the supply voltage has stabilized to sufficient
operating levels.
5
The ISL88031EVAL1 supports all variants of the ISL88031
devices, enabling evaluation of basic functional operation
and common application implementations. Figure 4
illustrates the ISL88031EVAL1 in schematic and
photographic forms. The ISL88031EVAL1 has two isolated
circuits; the left circuit is populated with the
ISL88031IU8HFZ (VDD VTH1 = 4.64V, V2MON
VTH2 = 3.08V). The right circuit is unpopulated for the user
to customize to provide a specific voltage monitoring solution
with the accompanying loose packed variants.
With adequate bias on the two preset and the three
adjustable monitor inputs, the RST output will release to pull
high indicating that all supplies are compliant for a minimum
of tPOR. For the ISL88031EVAL1 as shipped, the VDD and
V2MON nominal thresholds are as previously noted with the
voltage thresholds being monitored by V3MON, V4MON and
V5MON being nominally 1.990V, 1.44V and 0.95V
respectively.
Special Application Considerations
Using good decoupling practices on bias and other
monitoring inputs will prevent transients (i.e. due to switching
noises and short duration droops in the supply voltage) from
causing unwanted resets.
In unusually noisy environments or situations where
unwanted signals may be injected into adjustable VMONx
pins, lowering the node impedance and/or positioning a
small valued filter capacitor as close to the pin as possible
can increase noise immunity.
Although the internal ISL88031 threshold references are
guaranteed over the full temp range, accuracy errors due to
external component tolerances and distribution losses will
occur. High tolerance resistors and layout for extreme
accuracy and critical performance must be considered.
FN8227.2
June 9, 2009
ISL88031
VTH1/VTH2
VDD /
V2MON
1V
>tMR
MR
tPOR
tRPD
tPOR
tPOR
RST
>tMD
FIGURE 2. POWER SUPPLY MONITORING DIAGRAM
VMON
VTH
tRPD
tPOR
RST
FIGURE 3. VOLTAGE MONITORING DIAGRAM
5V
RST
RST
MR
MR
C1
R2
VDD
A
R1
23.2k
U1
V5MON
0.1µF
3.3V
V2MON
V4MON
GND
GND
V3MON
V5MON
R3
5.9k
V4MON
14k
R4
V3MON
23.2k
A
ISL88031
R7
10k
R6
10k
R5
10k
A
FIGURE 4. ISL88031EVAL1 SCHEMATIC AND PHOTOGRAPH
6
FN8227.2
June 9, 2009
ISL88031
5V
5V
3.3V
3.3V
2.1V
2.1V
1.5V
1.5V
1V
tPOR = 107ms
20ms/DIV
FIGURE 5. ISL88031 tPOR
7
RST
5V/DIV
1V
tRPD = 7.5µs
RST
5V/DIV
20µs/DIV
FIGURE 6. ISL88031 tRPD
FN8227.2
June 9, 2009
ISL88031
Mini Small Outline Plastic Packages (MSOP)
N
M8.118 (JEDEC MO-187AA)
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1
INCHES
E
-B-
INDEX
AREA
1 2
0.20 (0.008)
A B C
TOP VIEW
4X θ
0.25
(0.010)
R1
R
GAUGE
PLANE
A
SEATING
PLANE -C-
A2
A1
b
-He
D
0.10 (0.004)
4X θ
L1
SEATING
PLANE
C
0.20 (0.008)
C
a
CL
E1
C D
MAX
MIN
MAX
NOTES
0.037
0.043
0.94
1.10
-
A1
0.002
0.006
0.05
0.15
-
A2
0.030
0.037
0.75
0.95
-
b
0.010
0.014
0.25
0.36
9
c
0.004
0.008
0.09
0.20
-
D
0.116
0.120
2.95
3.05
3
E1
0.116
0.120
2.95
3.05
4
0.026 BSC
0.65 BSC
-
E
0.187
0.199
4.75
5.05
-
L
0.016
0.028
0.40
0.70
6
0.037 REF
N
C
0.20 (0.008)
MIN
A
L1
-A-
SIDE VIEW
SYMBOL
e
L
MILLIMETERS
0.95 REF
8
R
0.003
R1
0
α
-
8
-
0.07
0.003
-
5o
15o
0o
6o
7
-
-
0.07
-
-
5o
15o
-
0o
6o
-B-
Rev. 2 01/03
END VIEW
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. - H - Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (0.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Datums -A -H- .
and - B - to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
8
FN8227.2
June 9, 2009
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