DATASHEET

ISL88041
®
Data Sheet
April 29, 2010
Quad Voltage Monitor
Features
The ISL88041 is a quad voltage-monitoring supervisor
designed to monitor voltages ≥0.7V. Low voltage detection
circuitry protects the user 's system from low voltage
conditions, resetting the system when any of the monitored
power supply voltages V1MON-V4MON fall below their
respective minimum voltage thresholds. The reset signal
remains asserted until all of these voltages return to proper
operating levels and stabilize.
• Quad Voltage Monitoring
Each rail’s VMON point is independently adjustable by using
an external resistor divider. The VMON inputs will ignore
transients of less than 30µs on the monitored supplies, and
the RST output is guaranteed to be valid down to VDD = 1V.
The RST output is open-drain to allow ORing of multiple
signals and interfacing to a wide range of logic levels. Also,
the MR input allows the user to assert reset when this input
is pulled low.
Pinout
FN9229.2
• Adjustable Voltage Inputs Monitor Voltages ≥0.7V
• Active-Low RST Output
• Manual Reset Capability
• Reset Signal Valid Down to VDD = 1V
• Integrated 20kΩ Pull-Up Resistor on RST
• Glitch Immunity on Voltage Monitoring Inputs
• Pb-Free (RoHS Compliant)
Applications
• Graphics Cards
• Multi Voltage DSPs and Processors
• µP Voltage Monitoring
• Embedded Control Systems
ISL88041
(8 LD SOIC)
TOP VIEW
• Intelligent Instruments
• Medical Equipment
• Network Routers
VDD
1
8
V1MON
RST
2
7
V2MON
MR
3
6
V3MON
• Telecommunications Systems
GND
4
5
V4MON
Ordering Information
• Portable Battery-Powered Equipment
• Set-Top Boxes
PART
NUMBER
(Note)
ISL88041IBZ*
PART
MARKING
TEMP.
RANGE
(°C)
PACKAGE
(Pb-Free)
88041 IBZ -40 to +85 8 Ld SOIC
(Pb-free)
PKG.
DWG. #
M8.15
*Add “-T” suffix for tape and reel. Please refer to TB347 for details
on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. 2006, 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL88041
Pin Descriptions
ISL88041
PIN NAME
FUNCTION DESCRIPTION
1
VDD
Bias IC from nominal 2.7V to 4V.
2
RST
Active-Low Open Drain Reset Output. Internal 20kΩ pull-up resistor to VDD.
3
MR
Active Low Open Drain MR Input has a 10µA pull-up to VDD.
4
GND
5
V4MON
Fourth Adjustable Undervoltage Monitor Input
6
V3MON
Third Adjustable Undervoltage Monitor Input
7
V2MON
Second Adjustable Undervoltage Monitor Input
8
V1MON
First Adjustable Undervoltage Monitor Input
Ground.
Functional Block Diagram
VDD
MR
POR
V1MON
PB
30µs
FILTER
RST
± VREF
V2MON
30µs
FILTER
30µs
FILTER
VREF
± VREF
±
30µs
FILTER
GND
V4MON
V3MON
VREF ±
VREF = 635mV
2
FN9229.2
April 29, 2010
ISL88041
Absolute Maximum Ratings
Thermal Information
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5V
VMON, RST, MR . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD+0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kV (HBM)
Thermal Resistance (Typical, Note 1)
θJA (°C/W)
8 Ld SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
108
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
VDD Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . +2.7V to +4V
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board. See Tech Brief TB379 for details.
2. All voltages are relative to GND, unless otherwise specified.
Electrical Specifications
SYMBOL
VDD = 3.3V, TA = TJ = -40°C to +85°C, Unless Otherwise Specified.
PARAMETER
TEST CONDITIONS
MIN
(Note 3)
TYP
MAX
(Note 3)
UNIT
4.0
V
1000
µA
BIAS
VDD
Supply Voltage Range
IDD
VDD Supply Current
VMON > VREF
165
VDD Lock Out
VDD low to high
2.6
V
VDD Lock Out Reset
VDD high to low
2.4
V
VDD_LO
VDD_LOR
2.7
VMON
VREF
Adj. Reset Threshold Voltage
VREFHYST
Hysteresis of VREF
VREF_RNG
Range
tFIL
619
635
651
mV
10
mV
VREF (max) - VREF (min)
1.8
mV
Glitch Filter Duration
VMON glitch to RST low Filter
30
µs
IPD
Pull-down Current
RST = 0.5V
2
mA
RPU
Internal Pull-up Resistance
20
kΩ
VOL
Output Low
VDD = 1V
0.05
tRPD
VTH to Reset Asserted Delay
Last valid input = VTH to RST release
1.5
VMR
MR Input Voltage
MR low to high threshold
VMRHYST
Hysteresis of VMR
RESET
0.1
V
µs
MANUAL RESET
0.4VDD
0.5VDD
0.6VDD
V
0.065
V
IPU
Pull-up Current
MR = 0.5V
10
µA
tMD
MR to Deassert Reset Out Delay
MR high to RST release
50
ns
tMR
MR to Assert Reset Out Delay
MR low to RST pulling low
15
ns
NOTE:
3. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
3
FN9229.2
April 29, 2010
ISL88041
ISL88041 Description and Operation
undervoltage threshold (VTRIP) by connecting individual
VMON pins to an external resistor divider according to the
Equation 1:
The ISL88041 is a four voltage detection IC designed to
monitor multiple voltages ≥0.7V. This IC is suitable for
microprocessors or industrial system applications providing
both reset and manual reset functions.
(EQ. 1)
V TRIP = 0.635V ( R1 + R2 ) ⁄ R2
See Figure 8 for a typical application configuration.
VDD Lock Out
Manual Reset
Applying power to the ISL88041 VDD activates a lock out circuit
which disables the reporting function until VDD rises to ~2.6V.
As VDD bias is applied the RST output is held low before
VDD = 1V. If VDD falls below ~2.4V the lock out of monitoring
and reporting functions is invoked.
The manual-reset input (MR) allows the user to trigger a reset
by using a push-button switch or by signaling the input low.
Reset is asserted and deasserted immediately upon MR
transitioning through MRVTH, see Figures 6 and 7.
Low Voltage Monitoring
Figure 1 is the operational timing diagram.
Once biased to 2.7V the IC continuously monitors and
reports from one to four voltages independently through
external resistor dividers comparing each VMON pin voltage
to a nominal internal 0.635V reference. Once all VMON input
voltages rise above this threshold, the RST output is
immediately deasserted by being released to be pulled high
via its internal 20kΩ (or optional external) pull resistor to VDD
indicating that all the minimum voltage conditions have been
met (see Figure 4). The RST output is open-drain to allow
ORing of signals and interfacing to a range of logic levels.
Once any VMON input falls below its respective user-set
threshold, the RST output is pulled low after the glitch filter
delay (tFIL) as the VMON inputs are designed to reject short
undervoltage transients of approximately 30µs (see
Figure 5). The user can customize the individual rail
Using the ISL88041EVAL1
The ISL88041EVAL1 is the evaluation platform for this
product and illustrates the flexibility and simplicity of
monitoring four separate voltages. The RST output can be
monitored once the VDD, GND, and appropriate 3.3V, 2.5V,
1.8V and 1.2V supply voltage inputs are properly biased as
labeled. A Manual Reset (MR) input is also available for
evaluation.
The circuit as shown in Figures 10 and 11 has resistor
dividers chosen to monitor for an undervoltage threshold
level of 89% of the 4 nominal voltages. Figure 1 illustrates
the expected behavior and Figures 4 through 7 illustrate the
actual IC performance in the ISL88041EVAL1.
VTH
VMON
1V
tMR
<tFIL
MR
tRPD
>tFIL
tMD
RST
FIGURE 1. ISL88041 OPERATIONAL TIMING DIAGRAM
4
FN9229.2
April 29, 2010
ISL88041
0.6
0.645
0.5
0.642
VMON THRESHOLD (V)
VDD BIAS CURRENT (mA)
Typical Performance Curves
VMON < VMON_L2H
0.4
0.3
0.2
VMON > VMON_L2H
0.1
0
0.639
0.636
0.633
0.630
0.627
2.6
3.0
3.33
3.66
4.0
2.6
3.3
3.5
3.7
3.9
VDD BIAS VOLTAGE (V)
VDD BIAS VOLTAGE (V)
Figure 2 illustrates the idle and active bias currents levels.
FIGURE 2. VDD CURRENT vs VDD VOLTAGE
Figure 3 shows the VMON threshold shift over the bias range,
demonstrating a PSRR of 105dB.
FIGURE 3. VMON THRESHOLD vs VDD VOLTAGE
VMON
VMON
RST
tFIL ~30µs
RST = 2V/DIV
VMON = 1V/DIV
1µs/DIV
RST = 2V/DIV
VMON = 1V/DIV
FIGURE 4. VMON HIGH TO RST HIGH
RST
10µs/DIV
FIGURE 5. VMON LOW TO RST LOW
RST
RST
MR
MR
RST = 1V/DIV
MR = 1V/DIV
1µs/DIV
FIGURE 6. MR HIGH TO RST HIGH
5
MR = 1V/DIV
RST = 1V/DIV
10ns/DIV
FIGURE 7. MR LOW TO RST LOW
FN9229.2
April 29, 2010
ISL88041
V1 IN
V2 IN
V3 IN
(Continued)
V4 IN
Typical Performance Curves
ISL88041
*OPT
PS1
HIGH VALUE
CIRCUIT
REQUIRING
ACCURATE
VOLTAGE
MONITORING
PS2
1
VDD
VMON1 8
2
RST
VMON2 7
3
MR
VMON3 6
4
GND
VMON4 5
PS3
PS4
VMON 1- 4
ISL88041
MR
ISL88041
0.1µF
FIGURE 9. TYPICAL ISL88041 APPLICATION DIAGRAM
V_3.3
V_2.5
V_1.8
V_1.2
FIGURE 8. ISL88041 TYPICAL APPLICATION SCHEMATIC
RST
36.5k
1
VDD
VMON1 8
2
RST
VMON2 7
3
MR
VMON3 6
4
GND
VMON4 5
6.98k 15.4k 24.9k
10k
10k
10k
FIGURE 10. ISL88041EVAL1 SCHEMATIC
6
10k
FIGURE 11. ISL88041EVAL1 PHOTO
FN9229.2
April 29, 2010
ISL88041
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
N
INDEX
AREA
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
0.25(0.010) M
H
B M
INCHES
E
SYMBOL
-B1
2
3
L
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
MIN
MAX
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.1890
0.1968
4.80
5.00
3
E
0.1497
0.1574
3.80
4.00
4
e
α
B S
0.050 BSC
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
N
α
NOTES:
MILLIMETERS
8
0°
8
8°
0°
7
8°
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
7
FN9229.2
April 29, 2010
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